• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.
    公开号:US20010006848A1
    申请号:US09/738,589
    申请日:2000-12-15
    公开日:2001-07-05
    发明作者:Sudhakar Allada；Chris Foster
    申请人:National Semiconductor Corp；
    IPC主号:H01L21-76807
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] The present invention relates to interconnect integration technology. More specifically, the present invention relates to methylated oxide-type hardmasks for patterning interlayer dielectrics in integrated circuit device fabrication. [0002]
    [0003] 2. Description of the Related Art [0003]
    [0004] Integration of multilevel interconnects becomes increasingly important with ever increasing demands for device miniaturization and speed. In fact, with sub-0.25 μm geometries, interconnect capacitance is much larger than transistor capacitance. A reduction of the interconnect capacitance decreases RC and in turn, delay, thereby increasing device speed. [0004]
    [0005] Efforts to improve device performance include reducing the dielectric constant of interlayer dielectrics and the electrical resistance of interconnects, thereby reducing the wiring delay. Ikeda, et al., [0005] I.E.E.E. Inter. Interconnect Technology Conf. (1998) p. 131, describe a low k polymeric dielectric with a Cu-damascene structure. The polymeric dielectric (Allied Signal's FLARE™) was spin coated on undoped silicon glass (USG). The polymeric dielectric was then patterned through an overlying USG hardmask. Copper lines were formed by sputtering and CMP. Ikeda, et al. reported advantageous use of USG in achieving simultaneous resist ashing and etching of the polymeric dielectric as well as anisotropic O2 RIE etching. In addition, Ikeda, et al. reported relatively decreased wiring resistance of copper metallization formed in the polymeric dielectric with increasing metallization width.
    [0006] However, certain disadvantages attend. As those of skill in the art will appreciate, conventional processing to put a USG hardmask on a polymeric dielectric requires removal of the wafer from spin track equipment after formation of a polymeric dielectric to a different machine in order to create the hardmask. In addition, conventional USG hardmasks do not adhere well to a polymeric interlayer dielectric, which affects subsequent wafer processing. [0006] SUMMARY OF THE INVENTION
    [0007] The present invention addresses these and other problems in the prior art by providing a method of fabricating multilevel interconnects for integrated circuit devices, preferably for copper/dual damascene interconnect structures in integrated circuit devices. In one embodiment, a method according to the present invention includes a step of forming a methylated oxide-type hardmask on an interlayer dielectric, wherein the interlayer dielectric includes a polymeric dielectric material. The hardmasks preferred for the invention are those having dielectric constants of less than 3 and more preferably 2.7 or less. Methods according to the present invention can produce integrated circuit devices having lower effective dielectric constants, which enhances device performance and speed. [0007]
    [0008] In the present invention, both the hardmask and the interlayer dielectric can be spincoated. Alternatively, the hardmask can be prepared by CVD techniques. [0008] BRIEF DESCRIPTION OF THE DRAWINGS
    [0009] The present invention will be better understood by reference to the figures of the drawings, in which like reference numerals represent like elements and in which [0009]
    [0010] FIGS. 1 and 2 schematically illustrate cross sections of an interconnect stack formed according to the present invention. [0010] DESCRIPTION OF PREFERRED EMBODIMENTS
    [0011] The present invention relates to methods of interconnect integration in semiconductor fabrication techniques by eliminating need for removal of the wafer after formation of a polymeric interlayer dielectric to equipment for forming conventional oxide hardmasks on interlayer dielectrics. The present invention increases device speed by reducing the effective dielectric constant in the stack, and the structures created thereby. Instead of a conventional oxide hardmask, the present invention utilizes methylated oxide-type materials as hardmasks for the interlayer dielectric. As a result, methods according to the present invention benefit from increased compatibility and improved adhesion between the hardmask and interlayer polymeric dielectric and ease of subsequent wafer processing, especially chemical mechanical polishing steps. Methylated oxide-type dielectrics contemplated for hardmasks also have similar etching characteristics to conventional oxide hardmasks so that known processing regimes used successfully for SiO[0011] 2 and Cu metallization can be utilized.
    [0012] An interlayer dielectric in accordance with the present invention is suitably a polymeric semiconductor dielectric resin, such as Dow Chemical's SiLK™ material. Advantageously, this material is reported to have a dielectric constant of 2.65, compatible with aluminum/tungsten interconnects and stable to 490° C., and may be processed by conventional spin coating techniques and equipment. The inventors have found that this material is also compatible with copper metallization in dual damascene interconnect structures as well. [0012]
    [0013] Methylated oxide-type dielectrics useful in the present invention are materials exhibiting relatively low dielectric constant (k) of less than 3 and preferably less than about 2.7. These methylated oxide-type dielectrics have k much lower than conventional hardmask materials such as silicon dioxide (k=4) and silicon nitride (k=8), but similar etch and chemical contrast characteristics. Therefore, conventional hardmask thicknesses, etching techniques and chemistries can be used. Exemplary methylated oxide-type dielectrics suitable for the hardmasks prepared in accordance with the present invention include Allied Signal's HOSP™ proprietary materials. [0013]
    [0014] The inventors also have found that significant advantage can be achieved by forming a hardmask from a methylated oxide-type dielectric such as Allied Signal's HOSP™ material by spin coating techniques, since the hardmask may be formed the same equipment immediately following spin-coating of the interlayer dielectric from a polymeric dielectric resin, as described above. In addition, it is contemplated that as many as four layers can be spin coated over the layer adjacent to the wafer without sacrificing performance or processing ease. [0014]
    [0015] The present invention also contemplates formation of methylated oxide-type dielectric by conventional CVD techniques, as an alternative to a spin coated dielectric material. The advantage of spincoated materials compared to CVD deposited materials is reduced cycle time for fabrication since all dielectric layers of the stack can be deposited in the same spin track operation on the same tool. In contrast, the CVD deposited materials require additional process steps and additional tools. [0015]
    [0016] Together, the methylated oxide-type hardmask and the polymeric dielectric material for the interlayer dielectric can significantly reduce the effective dielectric constant, and therefore the capacitance between metal lines, improving device speed, depending on device architecture. [0016]
    [0017] FIGS. 1 and 2 illustrate exemplary interconnect stacks prepared according to the present invention. [0017]
    [0018] As shown in FIGS. 1[0018] a and 1 b, a single damascene structure 10 may be fabricated. A silicon nitride diffusion barrier 12 is deposited on a bare silicon substrate 14. A polymeric interlayer dielectric 16 is spun on diffusion barrier 12, followed by a methylated hardmask 18. Dielectric layer 16 is etched and then electroplated with copper to produce the single damascene structure 10 with a copper line 20.
    [0019] Likewise, as shown in FIGS. 2[0019] a and 2 b, dual damascene structure 22 can be formed by spinning four alternating layers of polymeric interlayer dielectric 24, 26 and hardmask 28, 30 followed by etch and copper electroplating to form copper line 32.
    [0020] Table 1 lists typical dimensions of the layers in a stack such as illustrated in FIGS. 1 and 2. As can be appreciated, the thickness of the methylated oxide-type hardmask is consistent with conventional oxide (e.g., USG) hardmask materials. Thickness of the hardmask will depend on the thickness of the underlying dielectric layer and device architecture. [0020] TABLE 1 interlayer diffusion layer dielectric1 hardmask2 barrier3 thickness 7 1 1 (KÅ)
    [0021] While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative, rather than limiting sense. It is contemplated that many modifications within the scope and spirit of the invention will readily occur to those skilled in the art and the appended claims are intended to cover such variations. [0021]
    权利要求:
    Claims (10)
    [1" id="US-20010006848-A1-CLM-00001] 1. A method of fabricating multilevel interconnects for integrated circuit devices, comprising:
    forming a methylated oxide-type hardmask on an interlayer dielectric, wherein the interlayer dielectric includes a polymeric dielectric material.
    [2" id="US-20010006848-A1-CLM-00002] 2. A method according to
    claim 1 , wherein the hardmask is spincoated on the-interlayer dielectric.
    [3" id="US-20010006848-A1-CLM-00003] 3. A method according to
    claim 1 , wherein the hardmask has a dielectric constant of about 2.7 or less.
    [4" id="US-20010006848-A1-CLM-00004] 4. A method according to
    claim 1 , further comprising the step of forming copper metallization lines in the interlayer dielectric.
    [5" id="US-20010006848-A1-CLM-00005] 5. An integrated circuit device fabricated according to the method of
    claim 1 .
    [6" id="US-20010006848-A1-CLM-00006] 6. A method of reducing the effective dielectric constant of integrated circuit devices, comprising:
    forming a methylated oxide-type hardmask on an interlayer dielectric, wherein the interlayer dielectric includes a polymeric dielectric material.
    [7" id="US-20010006848-A1-CLM-00007] 7. A method according to
    claim 6 , wherein the hardmask is spincoated on the interlayer dielectric.
    [8" id="US-20010006848-A1-CLM-00008] 8. A method according to
    claim 6 , wherein the hardmask has a dielectric constant of about 2.7 or less.
    [9" id="US-20010006848-A1-CLM-00009] 9. A method according to
    claim 6 , further comprising the step of forming copper metallization lines in the interlayer dielectric.
    [10" id="US-20010006848-A1-CLM-00010] 10. An integrated circuit device formed according to the method of
    claim 6 .
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    引用文献:
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    US6521533B1|1999-09-14|2003-02-18|Commissariat A L'energie Atomique|Method for producing a copper connection|
    US20060038296A1|2004-08-19|2006-02-23|King Sean W|Integrated low-k hard mask|
    US8900997B2|2012-12-26|2014-12-02|Cheil Industries, Inc.|Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith|US4522681A|1984-04-23|1985-06-11|General Electric Company|Method for tapered dry etching|
    US5924005A|1997-02-18|1999-07-13|Motorola, Inc.|Process for forming a semiconductor device|
    US6218302B1|1998-07-21|2001-04-17|Motorola Inc.|Method for forming a semiconductor device|
    US6100195A|1998-12-28|2000-08-08|Chartered Semiconductor Manu. Ltd.|Passivation of copper interconnect surfaces with a passivating metal layer|
    US6136511A|1999-01-20|2000-10-24|Micron Technology, Inc.|Method of patterning substrates using multilayer resist processing|
    US6028015A|1999-03-29|2000-02-22|Lsi Logic Corporation|Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption|JP3305251B2|1998-02-26|2002-07-22|松下電器産業株式会社|Method of forming wiring structure|
    US6509259B1|1999-06-09|2003-01-21|Alliedsignal Inc.|Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices|
    JP4368498B2|2000-05-16|2009-11-18|Ｎｅｃエレクトロニクス株式会社|Semiconductor device, semiconductor wafer and manufacturing method thereof|
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    US6656532B2|2001-05-17|2003-12-02|Honeywell International Inc.|Layered hard mask and dielectric materials and methods therefor|
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    法律状态:
    2002-08-08| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2002-12-31| CC| Certificate of correction|
    2006-02-27| FPAY| Fee payment|Year of fee payment: 4 |
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    优先权:
    申请号 | 申请日 | 专利标题
    US09/294,914|US6218317B1|1999-04-19|1999-04-19|Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration|
    US09/738,589|US6440853B2|1999-04-19|2000-12-15|Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration|US09/738,589| US6440853B2|1999-04-19|2000-12-15|Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration|
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