美国专利US20010006240A1 Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatu

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专利摘要:
A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.
公开号:US20010006240A1
申请号:US09/789,999
申请日:2001-02-21
公开日:2001-07-05
发明作者:Trung Doan；Gurtej Sandhu；Kirk Prall；Sujit Sharan
申请人:Micron Technology Inc；
IPC主号:H01L21-76843

专利说明:
[0001] The present invention relates to a method for manufacturing semiconductor devices, and in particular, to a method for forming titanium silicide within electrical contacts and apparatuses including such electrical contacts. [0001] BACKGROUND OF THE INVENTION
[0002] Device density in integrated circuits (ICs) is constantly being increased. To enable the increase in density, device dimensions are being reduced. As the dimensions of device contacts get smaller, device contact resistance increases, and device performance is adversely affected. Methods for decreasing device contact resistance in ICs are needed to obtain enhanced device and IC performance. [0002]
[0003] Device contacts with reduced resistance may be created by forming certain metals on a silicon semiconductor base layer. These metals react with the underlying silicon, for example, to form silicides. Silicide device contacts are desirable because they reduce the native oxide on silicon. The native oxide is undesirable because it increases the contact resistance. [0003]
[0004] Titanium is preferably used to form silicide device contacts for two reasons. First, titanium silicide has superior gettering qualities. Also, titanium silicide forms low resistance contacts on both polysilicon and single-crystal silicon. [0004]
[0005] Device contacts are normally formed with the following process. First, a thin layer of titanium is formed on top of the silicon base layer, such as a substrate. The titanium adjoins active regions exposed by contact holes in an isolating layer, such as an oxide, above the silicon base layer. Then, the silicon base layer is annealed. As a result, the titanium reacts with the active regions of silicon to form titanium silicide. [0005]
[0006] Ultimately, an electrically conductive plug material, such as tungsten, fills the contact hole to facilitate external electrical connection to the contact. However, plug materials, such as tungsten, adhere poorly to titanium silicide. Additionally, to ensure low contact resistivity, aluminum or polysilicon plug materials should not be intermixed with the titanium silicide and underlying silicon base layer. Accordingly, a barrier layer is formed over the titanium silicide to prevent diffusion of the titanium silicide and silicon base layer into the plug material. The barrier layer also causes the plug material to adhere to the IC. [0006]
[0007] Titanium nitride is a desirable barrier layer because it is an impermeable barrier for silicon, and because the activation energy required for the diffusion of other impurities is very high. Titanium nitride is also chemically and thermodynamically stable, and has a relatively low resistivity. Titanium nitride can be formed on the substrate by (1) evaporating titanium in a nitrogen ambient, (2) reactively sputtering titanium in an argon and nitrogen mixture, (3) sputtering from a titanium nitride target in an inert argon ambient, (4) sputter depositing titanium in an argon ambient, and converting the titanium to titanium nitride subsequently by plasma nitridation, or (5) low pressure chemical vapor deposition (CVD). [0007]
[0008] The resistance of device contacts can also be adversely increased by the formation of titanium silicide having small step coverage in the contact hole. As device dimensions shrink, the contact holes become relatively deeper and narrower. Also, the walls of the contact holes become steeper, and closer to vertical. As a result, most metal deposition techniques form conductive layers having relatively small step coverage. As a result, a void, or keyhole, forms in the plug material. The void increases contact resistivity and diminishes contact reliability. Hence, IC performance is degraded. Thus, there is a need for forming contacts with reduced resistivity. Specifically, there is a need for a method of forming contacts without voids. [0008] SUMMARY OF THE INVENTION
[0009] The present invention solves the above-mentioned problems in the art and other problems which will be understood by those skilled in the art upon reading and understanding the present specification. The present invention includes a method for forming titanium silicide and/or titanium by chemical vapor deposition (CVD), and apparatus formed by such a method. The method comprises cleaning a contact hole. A titanium precursor and a silicon precursor are combined in the presence of hydrogen (H[0009] ₂). Titanium silicide is formed by CVD.
[0010] In another embodiment, the method includes combining a titanium precursor in the presence of hydrogen (H[0010] ₂). Then, titanium silicide is formed by CVD on an exposed silicon surface of a contact hole.
[0011] In another embodiment, the method includes forming titanium by CVD on a conductor according to the following chemical process:[0011]
[0012] In yet another embodiment, the method includes forming titanium by CVD on an insulator according to the following chemical process:[0012]
[0013] In yet another embodiment, the method includes forming titanium silicide according to the following chemical process: [0013]
[0014] wherein TiCl[0014] ₄is the titanium precursor, Si_nH_2n+2is the silicon precursor, x is less than or equal to 2, and n is greater than or equal to 1.
[0015] In yet another embodiment, the titanium suicide is also formed according to the following chemical process:[0015]
[0016] wherein x is less than or equal to 2. [0016]
[0017] In one embodiment, the apparatus is a memory, comprising a memory array, a control circuit, operatively coupled to the memory array, and address logic, operatively coupled to the memory array and the control logic. The memory array, control circuit and address logic, each including a contact. The contact includes titanium silicide. Titanium nitride is formed on the titanium silicide. A plug material is formed on the titanium nitride. The plug material is substantially solid. In another embodiment, the titanium silicide formed on an exposed silicon base layer, and the exposed silicon base layer is not substantially depleted. [0017]
[0018] In yet another embodiment, the apparatus is a system, comprising a memory, and a processor coupled to the memory. The memory includes a contact. The contact includes titanium silicide. Titanium nitride is formed on the titanium silicide. A plug material is formed on the titanium nitride. The plug material is substantially solid. In yet another embodiment, the titanium silicide formed on an exposed silicon base layer, and the exposed silicon base layer is not substantially depleted. [0018]
[0019] It is an advantage of the present invention that the contacts have reduced resistivity. It is a further benefit that the contacts have increased reliability. [0019] BRIEF DESCRIPTION OF THE FIGURES
[0020] FIG. 1A is a cross-sectional view of a contact hole that has been etched through an insulator to an underlying semiconductor substrate. [0020]
[0021] FIG. 1B is a cross-sectional view of the contact hole of FIG. 1A, comprising a silicide film formed thereon by one aspect of the present invention. [0021]
[0022] FIG. 1C is a cross-sectional view of the contact hole of FIG. 1B, further comprising a barrier layer and plug material. [0022]
[0023] FIG. 2A is a cross-sectional view of the contact hole of FIG. 1A, comprising a silicide film formed thereon by another aspect of the invention. [0023]
[0024] FIG. 2B is a cross-sectional view of the contact hole of FIG. 2A, further comprising a barrier layer and plug material. [0024]
[0025] FIG. 2C is a cross-sectional view of a contact hole comprising a conductor, a barrier layer, and plug material. [0025]
[0026] FIG. 3A is a cross-sectional view of a contact hole that has been etched into an insulator. [0026]
[0027] FIG. 3B is a cross-sectional view of the contact hole of FIG. 3A, further comprising a silicide film, a barrier layer and plug material formed thereon by another aspect of the invention. [0027]
[0028] FIG. 4 is a block diagram of a memory. [0028]
[0029] FIG. 5 is a block diagram of a memory coupled to an external system. [0029] DETAILED DESCRIPTION OF THE INVENTION
[0030] In order to manufacture a contact in an integrated circuit (IC) [0030] 11, a contact hole 10, as illustrated in FIG. 1A, is etched through an insulator 12, such as borophosphosilicate glass (BPSG) or silicon dioxide, to expose a portion of the underlying silicon base layer 14, to which electrical contact is to be made. The exposed silicon base layer 14 is generally an active region 15 of a transistor in the IC 11. An optional in-situ clean of the contact hole 10 may then be performed with a wet chemical clean, or a plasma, such as a high density Ar/NF₃plasma.
[0031] Chemical vapor deposition (CVD) is then used to form titanium silicide [0031] 16, such as TiSi_x, at the bottom of contact hole 10, as shown in FIG. 1B. CVD permits accurately controlled formation of films, including conformal films.
[0032] CVD techniques are well known by persons skilled in the art, and are described in Panson et al., [0032] Appl. Phys. Lett., 53, 1756 (1988) and Cowher et al., J. Cryst. Growth, 46, 399 (1979), hereby incorporated by reference. Any CVD apparatus design may be used when practicing the present invention including hot wall reactors, cold wall reactors, radiation beam assisted reactors, and plasma-assisted reactors. These CVD apparatuses are disclosed in C. E. Morosanu, “Thin Films by Chemical Vapor Deposition,” Elsevier, N.Y. (1990), pages 42-54; I. P. Herman, Chemical Reviews, 89, 1323 (1989); U.S. Pat. No. 4,876,112; U.S. Pat. No. 5,005,519; U.S. Pat No. 4,340,617; U.S. Pat No. 4,713,258; U.S. Pat. No. 4,721,631; U.S. Pat. No. 4,923,717; U.S. Pat No. 5,022,905; U.S. Pat. No. 4,868,005; U.S. Pat. No. 5,173,327, and Bachman et al., MRS Bull., 13, 52 (1988), hereby incorporated by reference.
[0033] For blanket depositions, a cold wall-hot substrate reactor is sometimes preferred, as this design is efficient in regard to precursor consumption. For depositions on selection areas, a radiation beam assisted reactor may be preferred as the radiation beam may be used to selectively deposit metal containing films onto small areas of the substrate. [0033]
[0034] Different embodiments for forming titanium silicide, which may use plasma-assisted CVD (PACVD) and non-plasma CVD, are subsequently described. In a first embodiment, CVD is utilized to deposit a film of titanium silicide [0034] 16 on the top and side walls of the insulator 12, as illustrated in FIG. 1B. The titanium silicide 16 is preferably formed as a conformal film, and thus has high step coverage. This embodiment will now be described in further detail.
[0035] The IC [0035] 11 is mounted on a substrate holder in a chamber of the CVD apparatus. A titanium precursor, such as titanium tetrachloride (TiCl₄) and a silicon precursor, such as silane (Si_nH_2n+2), for example either SiH₄or Si₂H₆, are combined with hydrogen (H₂) in the CVD apparatus to form the titanium silicide 16 in and around the contact hole 10, as illustrated in FIG. 1B. The following general chemical process (I) is used:
[0036] wherein, generally, n is greater than or equal to 1, and x is less than or equal to 2. [0036]
[0037] When PACVD is used, the deposition takes place in a water cooled quench chamber having a volume of approximately 6 liters. The power supply for generating a plasma can be any type of energy source, such as radio frequency (RF) or direct current (DC). When a RF power source is used, the radio frequency is approximately 13.6 MHZ. However, the present invention envisions using higher or lower frequencies. The power of the energy source used to create the plasma is between approximately 10 and 1,000 Watts, preferably approximately 600 Watts. The IC [0037] 11 is heated to a temperature between approximately 300 and 800 degrees Celsius, preferably approximately 500 degrees Celsius.
[0038] In the first embodiment, the precursor gases TiCl[0038] ₄and Si_nH_2n+2are delivered to a plasma flame. TiCl₄is introduced at a flow rate of between approximately 1 and 40 sccm, preferably approximately 20 sccm. If SiH₄is used, the SiH₄is introduced at a flow rate of between approximately 0.5 and 100 sccm, preferably approximately 50 sccm. Alternatively, Si₂H₆may be used, and is introduced at a flow rate of between approximately 0.05 and 50 sccm, preferably approximately 25 sccm. A sheath gas, selected from a group consisting of the noble gases and hydrogen, is employed in order to direct the plasma flame. In this example, hydrogen is introduced at a flow rate between approximately 500 and 5,000 sccm, preferably approximately 3,000 sccm. Optionally, a carrier gas, such as argon, is also introduced at a flow rate between approximately 500 and 5,000 sccm, preferably approximately 2,000 sccm.
[0039] A precursor compound, including silicon and titanium precursors, becomes a plasma gas. The precursor compound is transported via a reactor tube to the chamber. The precursor plasma, upon coming into contact with the heated IC [0039] 11, pyrolyzes and deposits a film of TiSi_x 16 on the exposed surfaces of the insulator 12. The chamber pressure is between approximately 0.1 and 100 Torr, preferably approximately 5 Torr. The reaction products from the pyrolysis of the precursor compound exit from the chamber via an exhaust manifold.
[0040] For this embodiment, x is typically 2. However, x may be less than 2 when the silane flow rate is relatively low, and when TiCl[0040] ₄precursor flow rate is relatively high.
[0041] Alternatively, when using a non-plasma CVD method, the process parameters generally remain the same. However, in the absence of the plasma, the process temperature is increased to between approximately 600 and 900 degrees Celsius, preferably approximately 700 degrees Celsius. [0041]
[0042] Titanium silicide is typically formed on the exposed surface of the silicon base layer [0042] 14 when the titanium precursor and hydrogen contact the silicon base layer 14. This reaction is described by the following general chemical process (II):
[0043] However, process (II) may remove exposed silicon base layer that is the active region [0043] 15. Titanium silicide 16 will then intrude into the active region where the exposed silicon base layer was removed. The active region 15 is highly doped to reduce contact resistance. As a result of the removal, the contact resistance will undesirably increase. Therefore, preferably, sufficient silane is preferably added to the precursor compound by regulating the silane flow rate. As a result, titanium silicide over the exposed silicon base layer is at least partially formed according to process (I). Hence, the exposed silicon will not be substantially depleted. Therefore, the contact resistance will not be detrimentally increased.
[0044] In a second embodiment, CVD is used to selectively deposit a film of titanium silicide [0044] 16 on the exposed silicon base layer according to process (II), described above. If PACVD is used, the IC 11 is heated to between approximately 400 and 800 degrees Celsius. Simultaneously, a substantially thinner layer of titanium 17 is deposited on the sidewalls of the contact hole 10, as illustrated in FIG. 2A. The titanium 17 is deposited according to chemical process (III):
[0045] As illustrated in FIG. 2B, the titanium [0045] 17 formed on the sidewalls of the insulator 12 is substantially thinner than the titanium silicide 16 formed on the base of the contact hole 10. Thus, in the event the titanium 17 on the sidewalls is formed with a retrograde, a there will be substantially no voids in the subsequently formed plug material 20, illustrated in FIG. 2C. Hence, the plug-material 20 is substantially solid. The titanium 17 formed on the top of the insulator 12 is substantially thicker than the titanium 17 formed on the sidewalls of the conductor 12.
[0046] The second embodiment may be implemented, for example, at a temperature of approximately 630 degrees Celsius, a pressure of approximately 5 Torr, an H[0046] ₂flow rate of approximately 5 slm, and a TiCl₄flow rate of approximately 40 sccm. A carrier gas, such as argon, having a flow rate of approximately 5 slm, may also be used. As a result, a 500 Angstrom layer of titanium 17 is formed on the exterior surfaces 22 of the insulator 12. Little or no titanium 17 is formed in the contact hole 10, such as on the sidewalls 24 and over the active region 15, as illustrated in FIG. 2A. Additionally, approximately 2500 Angstroms of titanium silicide 16 is formed over the active region 15. Alternatively, the second embodiment may be implemented at a temperature of less than about 550 degrees Celsius. As a result, about 1250 Angstroms of titanium 17, rather than titanium silicide 16, are formed over the active region 15. The titanium 17 is subsequently converted to titanium silicide during an anneal.
[0047] Chemical process (III), described above, may also be used to form a contact to a conductor [0047] 21 on an IC 11, as illustrated in FIG. 2C. The conductor 21 is typically formed over a second insulator 23 on the IC 11. The titanium 17 formed on the sidewalls of the contact hole 10 is substantially thinner than the titanium 17 formed on the base of the contact hole 10. Thus, in the event the titanium 17 on the sidewalls is formed with a retrograde, a there will be substantially no voids in the subsequently formed plug material 20, illustrated in FIG. 2C.
[0048] In a third embodiment, titanium silicide [0048] 16 can be formed in a contact hole 10 in insulator 14, where no silicon base layer 12 is exposed, as illustrated in FIG. 3A. A conformal layer of titanium silicide 16 having high step coverage is formed in the contract hole 10, according to general chemical process (I) described above. For the first, second and third embodiments, the reaction products of general chemical processes (I) and (II) may also include SiCl₄.
[0049] Typically, after the titanium silicide [0049] 16 has been formed according to one of the embodiments described above, the barrier layer 18 is then formed in the contact hole, as illustrated in FIGS. 1C, 2B and 3B. The IC 11 may be heated before or after barrier layer 18 formation. Heating may be accomplished, for example, in a rapid thermal annealer or a furnace, in a manner known to persons skilled in the art. The heating step can convert titanium 17 proximate to exposed silicon to titanium silicide 16. Additionally, heating of previously formed titanium silicide 16 is desirable because it reduces native oxides. The plug material 20 is then formed over the barrier layer 18 to complete contact formation. The barrier layer 18 and plug material 20 may each be formed by CVD.
[0050] The aforementioned processes may be used to form contacts in an integrated circuit [0050] 11 that is a memory 400, such as a dynamic random access memory. The memory 400 may include a memory array 402, control logic 404, and address logic 406 coupled in a manner known to one skilled in the art and exemplified in FIG. 4. Each of the aforementioned elements of the memory 400 includes contacts formed in the manner described above. The memory 400 may be coupled to an external system 524, such as a processor, as illustrated in FIG. 5.
[0051] The present invention provides a method for forming low resistivity, high reliability contacts. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. For example, other titanium precursors, such as tetradimethyl amino titanium (TDMAT) can be used to form titanium [0051] 17 and titanium silicide 16. Additionally, the present invention may be implemented with any CVD apparatus 29, including hot wall reactors, cold wall reactors, radiation beam assisted reactors, plasma-assisted reactors, and the like. Hence, the scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

权利要求:
Claims (37)
[1" id="US-20010006240-A1-CLM-00001] 1. A method of forming a contact, comprising the steps of:
cleaning a contact hole prior to forming titanium silicide;
combining a titanium precursor and a silicon precursor in the presence of hydrogen (H₂); and
forming the titanium silicide by CVD on an exposed silicon base layer.
[2" id="US-20010006240-A1-CLM-00002] 2. The method of
claim 2 , wherein the step of forming the titanium silicide comprises the step of forming titanium silicide according to chemical process (I):
TiCl₄+Si_nH_2n+2+H₂→TiSi_x+HCl (I);and
wherein TiCl₄is the titanium precursor, Si_nH_2n+2is the silicon precursor, and n is greater than or equal to 1.
[3" id="US-20010006240-A1-CLM-00003] 3. The method of
claim 2 , wherein the step of forming titanium silicide further comprises the step of forming the titanium silicide according to chemical process (II):
TiCl₄+Si+H₂→TiSi_x+HCl (II);and
wherein x is less than or equal to 2.
[4" id="US-20010006240-A1-CLM-00004] 4. The method of
claim 3 , wherein the step of forming the titanium silicide comprises optimizing the amount of Si_nH_2n+2added to a precursor compound to diminish removal of the exposed silicon base layer.
[5" id="US-20010006240-A1-CLM-00005] 5. The method of
claim 2 , wherein the step of forming the titanium silicide further comprises forming titanium silicide according to chemical process (I) which additionally includes SiCl₄as a reaction product.
[6" id="US-20010006240-A1-CLM-00006] 6. The method of
claim 3 , wherein the step of forming the titanium silicide further comprises forming titanium silicide according to chemical processes (I) and (II) which additionally include SiCl₄as a reaction product.
[7" id="US-20010006240-A1-CLM-00007] 7. The method of
claim 2 , wherein the step of combining further comprises the step of combining the silicon precursor that is SiH₄, which is introduced into a CVD chamber at a flow rate between approximately 0.5 and 100 sccm.
[8" id="US-20010006240-A1-CLM-00008] 8. The method of
claim 2 , wherein the step of combing comprises the step of combining the silicon precursor that is Si₂H₆, which is introduced into a CVD chamber at a flow rate of approximately 0.05 to 50 sccm.
[9" id="US-20010006240-A1-CLM-00009] 9. The method of
claim 2 , wherein the step of combining comprises the step of combining in a CVD chamber that is plasma-assisted; and
wherein the step of forming titanium silicon comprises heating a contact hole to between approximately 300 and 800 degrees Celsius.
[10" id="US-20010006240-A1-CLM-00010] 10. The method of
claim 2 , wherein the step of combining comprises the step of combining in a CVD chamber that is plasma-assisted; and
wherein the plasma is created by an energy source that uses between approximately 10 and 1,000 Watts.
[11" id="US-20010006240-A1-CLM-00011] 11. The method of
claim 2 , wherein the step of combining comprises the step of combining in a CVD chamber is a non-plasma chamber; and
wherein the step of forming titanium silicide comprises heating a contact hole to between approximately 600 and 900 degrees Celsius.
[12" id="US-20010006240-A1-CLM-00012] 12. The method of
claim 2 , wherein the step of combining comprises the step of introducing the TiCl₄in a CVD chamber at a flow rate between approximately 1 and 40 sccm.
[13" id="US-20010006240-A1-CLM-00013] 13. The method of
claim 2 , wherein the step of combining comprises the step of introducing the H₂in a CVD chamber at a flow rate between approximately 500 and 5,000 sccm.
[14" id="US-20010006240-A1-CLM-00014] 14. The method of
claim 13 , wherein the step of combining comprises the step of introducing argon into a CVD chamber at a flow rate between approximately 500 and 5,000 sccm.
[15" id="US-20010006240-A1-CLM-00015] 15. The method of
claim 2 , further comprising the step of operating a CVD chamber at a pressure between approximately 0.1 and 100 Torr.
[16" id="US-20010006240-A1-CLM-00016] 16. The method of
claim 2 , further comprising the steps of:
forming a barrier layer on the titanium silicide; and
forming a plug material on the barrier layer.
[17" id="US-20010006240-A1-CLM-00017] 17. A method for forming a contact, comprising the steps of:
cleaning a contact hole prior to forming titanium silicide;
combining a titanium precursor in the presence of hydrogen (H₂); and
forming titanium silicide by CVD on an exposed silicon base layer.
[18" id="US-20010006240-A1-CLM-00018] 18. The method of
claim 17 , further comprising the step of forming titanium on an insulator according to chemical process (III):
TiCl₄+H₂→Ti+HCl (I);and
wherein the step of forming the titanium silicide comprises the step of forming the titanium silicide according to chemical process (IV):
TiCl₄+Si+H₂→TiSi_x+HCl (IV),
wherein the titanium precursor is TiCl₄; and x is less than or equal to 2.
[19" id="US-20010006240-A1-CLM-00019] 19. The method of
claim 18 , wherein the step of forming titanium silicide comprises the step of forming titanium silicide according to chemical process (IV), which additionally includes SiCl₄as a reaction product.
[20" id="US-20010006240-A1-CLM-00020] 20. The method of
claim 18 , wherein the step of combining comprises the step of combining a CVD chamber that is plasma-assisted; and
wherein the step of forming titanium silicide comprises heating a contact hole to between approximately 400 and 800 degrees Celsius.
[21" id="US-20010006240-A1-CLM-00021] 21. The method of
claim 18 , wherein the step of combining comprises the step of combining a CVD chamber that is plasma-assisted; and wherein the plasma is created by an energy source that uses between approximately 10 and 1,000 Watts.
[22" id="US-20010006240-A1-CLM-00022] 22. The method of
claim 18 , wherein the step of combining comprises the step of combining a CVD chamber that is a non-plasma chamber; and
wherein the step of forming titanium silicide comprises heating a contact hole to between approximately 600 and 900 degrees Celsius.
[23" id="US-20010006240-A1-CLM-00023] 23. The method of
claim 18 , wherein the step of combining comprises the step of introducing the TiCl₄in a CVD chamber at a flow rate between approximately 1 and 40 sccm.
[24" id="US-20010006240-A1-CLM-00024] 24. The method of
claim 18 , wherein the step of combining comprises the step of introducing the H₂in a CVD chamber at a flow rate between approximately 500 and 5,000 sccm.
[25" id="US-20010006240-A1-CLM-00025] 25. The method of
claim 18 , wherein the step of combining comprises the step of introducing argon into a CVD chamber at a flow rate between approximately 500 and 5,000 sccm.
[26" id="US-20010006240-A1-CLM-00026] 26. The method of
claim 18 , further comprising the step of operating a CVD chamber at a pressure between approximately 0.1 and 100 Torr.
[27" id="US-20010006240-A1-CLM-00027] 27. The method of
claim 18 , further comprising the steps of:
forming a barrier layer on the titanium silicide; and
forming a plug material on the barrier layer.
[28" id="US-20010006240-A1-CLM-00028] 28. The method of
claim 18 , wherein the step of forming titanium comprises the step of forming titanium on sidewalls of a contact hole that is substantially thinner than the titanium silicide on the base of the contact hole.
[29" id="US-20010006240-A1-CLM-00029] 29. The method of
claim 17 , wherein the step of forming titanium silicide further comprises the steps of:
forming titanium on an insulator and an exposed silicon base layer according to chemical process (V):
TiCl₄+H₂→Ti+HCl (V);and
annealing the titanium.
[30" id="US-20010006240-A1-CLM-00030] 30. A method for forming a contact, comprising the steps of:
cleaning a contact hole prior to forming titanium;
forming the titanium by CVD on a conductor according to chemical process (VI):
TiCl₄+H₂→Ti+HCl (VI);
forming a barrier layer on the titanium; and
forming a plug material on the barrier layer.
[31" id="US-20010006240-A1-CLM-00031] 31. The method of
claim 30 , wherein the step of forming titanium comprises the step of forming titanium on sidewalls of a contact hole that is substantially thinner than the titanium on the base of the contact hole.
[32" id="US-20010006240-A1-CLM-00032] 32. A method for forming a contact, comprising the steps of:
cleaning a contact hole prior to forming titanium;
forming the titanium by CVD on an insulator according to chemical process (VII):
TiCl₄+H₂→Ti+HCl (VII);
forming by a barrier layer on the titanium; and
forming by a plug material on the barrier layer.
[33" id="US-20010006240-A1-CLM-00033] 33. A method of forming a contact, comprising the steps of:
cleaning a contact hole with a high density Ar/NF₃plasma;
operating a CVD chamber at a pressure between approximately 0.1 and 100 Torr;
heating the contact hole to between approximately 300 and 700 degrees Celsius;
introducing TiCl₄into the CVD chamber at a flow rate between approximately 5 and 40 sccm;
introducing H₂into a CVD chamber at a flow rate between approximately 1,000 and 5,000 sccm;
introducing argon into a CVD chamber at a flow rate between approximately 500 and 5,000 sccm;
forming titanium silicide by plasma assisted CVD in the CVD chamber according to chemical processes (VII) and (IX): TiCl 4 + Si n  H 2  n + 2+ H 2 → TiSi x + HCl , and ( VIII ) TiCl 4 + Si + H 2 → TiSi x + HCl ; ( IX )
[34" id="US-20010006240-A1-CLM-00034] 34. A memory, comprising:
a memory array;
a control circuit, operatively coupled to the memory array;
address logic, operatively coupled to the memory array and the control logic;
wherein the memory array, control circuit and address logic each include a contact comprising,
titanium silicide,
titanium nitride on the titanium silicide, and
plug material on the titanium nitride; and
wherein the plug material is substantially solid.
[35" id="US-20010006240-A1-CLM-00035] 35. A memory, comprising:
a memory array;
a control circuit, operatively coupled to the memory array;
address logic, operatively coupled to the memory array and the control logic;
wherein the memory array, control circuit and address logic each include a contact comprising,
titanium silicide formed on an exposed silicon base layer,
titanium nitride on the titanium silicide, and
plug material on the titanium nitride; and
wherein the exposed silicon base layer is not substantially depleted.
[36" id="US-20010006240-A1-CLM-00036] 36. A system, comprising:
a memory; and
a processor coupled to the memory;
wherein the memory array, control circuit and address logic each include a contact comprising,
titanium silicide,
titanium nitride on the titanium silicide, and
plug material on the titanium nitride; and
wherein the plug material is substantially solid.
[37" id="US-20010006240-A1-CLM-00037] 37. A system, comprising:
a memory; and
a processor coupled to the memory; wherein the memory array, control circuit and address logic each include a contact comprising,
titanium silicide formed on an exposed silicon base layer,
titanium nitride on the titanium silicide, and
plug material on the titanium nitride; and
wherein the exposed silicon base layer is not substantially depleted.

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US6822303B2|2004-11-23|Titanium boride gate electrode and interconnect

US7923322B2|2011-04-12|Method of forming a capacitor

US6888252B2|2005-05-03|Method of forming a conductive contact

US20060261421A1|2006-11-23|Boron incorporated diffusion barrier material

US6372643B1|2002-04-16|Method for forming a selective contact and local interconnect in situ and semiconductor devices carrying the same

US20050233577A1|2005-10-20|High aspect ratio contact structure with reduced silicon consumption

US6696368B2|2004-02-24|Titanium boronitride layer for high aspect ratio semiconductor devices

US6433434B1|2002-08-13|Apparatus having a titanium alloy layer

KR20060032919A|2006-04-18|Chemical vapor deposition methods of forming an ohmic layer and a barrier metal layer in a semiconductor device using plasma

JPH08195440A|1996-07-30|Preparation of wiring metallic thin film of semiconductor element

同族专利:

公开号 | 公开日

WO1999009586A2|1999-02-25|

JP2003525520A|2003-08-26|

KR100380598B1|2003-04-18|

US6472756B2|2002-10-29|

US6255216B1|2001-07-03|

US6208033B1|2001-03-27|

AU9029598A|1999-03-08|

WO1999009586A3|1999-04-15|

US6255209B1|2001-07-03|

KR20010023123A|2001-03-26|

US6171943B1|2001-01-09|

US5976976A|1999-11-02|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US20030042606A1|2001-08-29|2003-03-06|Ammar Derraa|Method of forming a conductive contact|

US6649518B2|1999-02-18|2003-11-18|Micron Technology, Inc.|Method of forming a conductive contact|

US20060127601A1|2003-08-11|2006-06-15|Tokyo Electron Limited|Film formation method|

US7407882B1|2004-08-27|2008-08-05|Spansion Llc|Semiconductor component having a contact structure and method of manufacture|

US20140242802A1|2013-02-25|2014-08-28|United Microelectronics Corp.|Semiconductor process|

TWI637443B|2013-12-25|2018-10-01|日商東京威力科創股份有限公司|Contact layer formation method|US4340617A|1980-05-19|1982-07-20|Massachusetts Institute Of Technology|Method and apparatus for depositing a material on a surface|

US4359490A|1981-07-13|1982-11-16|Fairchild Camera & Instrument Corp.|Method for LPCVD co-deposition of metal and silicon to form metal silicide|

JPH0359980B2|1984-08-06|1991-09-12|Shingijutsu Jigyodan||

US4721631A|1985-02-14|1988-01-26|Sharp Kabushiki Kaisha|Method of manufacturing thin-film electroluminescent display panel|

US4868005A|1986-04-09|1989-09-19|Massachusetts Institute Of Technology|Method and apparatus for photodeposition of films on surfaces|

US4884123A|1987-02-19|1989-11-28|Advanced Micro Devices, Inc.|Contact plug and interconnect employing a barrier lining and a backfilled conductor material|

US4957777A|1988-07-28|1990-09-18|Massachusetts Institute Of Technology|Very low pressure chemical vapor deposition process for deposition of titanium silicide films|

GB8824102D0|1988-10-14|1988-11-23|Pilkington Plc|Apparatus for coating glass|

US5015330A|1989-02-28|1991-05-14|Kabushiki Kaisha Toshiba|Film forming method and film forming device|

JP2537413B2|1989-03-14|1996-09-25|三菱電機株式会社|Semiconductor device and manufacturing method thereof|

US4923717A|1989-03-17|1990-05-08|Regents Of The University Of Minnesota|Process for the chemical vapor deposition of aluminum|

US4971655A|1989-12-26|1990-11-20|Micron Technology, Inc.|Protection of a refractory metal silicide during high-temperature processing using a dual-layer cap of silicon dioxide and silicon nitride|

US5005519A|1990-03-14|1991-04-09|Fusion Systems Corporation|Reaction chamber having non-clouded window|

US5032233A|1990-09-05|1991-07-16|Micron Technology, Inc.|Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point metal as an anti-reflective coating during laser planarization|

US5196360A|1990-10-02|1993-03-23|Micron Technologies, Inc.|Methods for inhibiting outgrowth of silicide in self-aligned silicide process|

US5136362A|1990-11-27|1992-08-04|Grief Malcolm K|Electrical contact with diffusion barrier|

JP2660359B2|1991-01-30|1997-10-08|三菱電機株式会社|Semiconductor device|

DE69225082T2|1991-02-12|1998-08-20|Matsushita Electronics Corp|Semiconductor device with improved reliability wiring and method of manufacture|

US5147819A|1991-02-21|1992-09-15|Micron Technology, Inc.|Semiconductor metallization method|

US5124780A|1991-06-10|1992-06-23|Micron Technology, Inc.|Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planarization|

US5173327A|1991-06-18|1992-12-22|Micron Technology, Inc.|LPCVD process for depositing titanium films for semiconductor devices|

US5192589A|1991-09-05|1993-03-09|Micron Technology, Inc.|Low-pressure chemical vapor deposition process for depositing thin titanium nitride films having low and stable resistivity|

US5571572A|1991-09-05|1996-11-05|Micron Technology, Inc.|Method of depositing titanium carbonitride films on semiconductor wafers|

EP0536664B1|1991-10-07|1997-01-15|Sumitomo Metal Industries, Ltd.|A method for forming a thin film|

US5227334A|1991-10-31|1993-07-13|Micron Technology, Inc.|LPCVD process for depositing titanium nitride films and silicon substrates produced thereby|

US5278100A|1991-11-08|1994-01-11|Micron Technology, Inc.|Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers|

US5275715A|1992-01-23|1994-01-04|Micron Technology Inc.|Electroplating process for enhancing the conformality of titanium and titanium nitride films in the manufacture of integrated circuits and structures produced thereby|

US5474949A|1992-01-27|1995-12-12|Matsushita Electric Industrial Co., Ltd.|Method of fabricating capacitor or contact for semiconductor device by forming uneven oxide film and reacting silicon with metal containing gas|

US5227331A|1992-02-10|1993-07-13|Micron Technology, Inc.|CVD method for semiconductor manufacture using rapid thermal pulses|

US5252518A|1992-03-03|1993-10-12|Micron Technology, Inc.|Method for forming a mixed phase TiN/TiSi film for semiconductor manufacture using metal organometallic precursors and organic silane|

US5306951A|1992-05-14|1994-04-26|Micron Technology, Inc.|Sidewall silicidation for improved reliability and conductivity|

US5254499A|1992-07-14|1993-10-19|Micron Technology, Inc.|Method of depositing high density titanium nitride films on semiconductor wafers|

US5240739A|1992-08-07|1993-08-31|Micron Technology|Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers|

US5258096A|1992-08-20|1993-11-02|Micron Semiconductor, Inc.|Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths|

US5320880A|1992-10-20|1994-06-14|Micron Technology, Inc.|Method of providing a silicon film having a roughened outer surface|

US5416045A|1993-02-18|1995-05-16|Micron Technology, Inc.|Method for chemical vapor depositing a titanium nitride layer on a semiconductor wafer and method of annealing tin films|

US5358901A|1993-03-01|1994-10-25|Motorola, Inc.|Process for forming an intermetallic layer|

US5344792A|1993-03-04|1994-09-06|Micron Technology, Inc.|Pulsed plasma enhanced CVD of metal silicide conductive films such as TiSi2|

KR100320364B1|1993-03-23|2002-04-22|가와사키 마이크로 엘렉트로닉스 가부시키가이샤|Metal wiring and its formation method|

US5273783A|1993-03-24|1993-12-28|Micron Semiconductor, Inc.|Chemical vapor deposition of titanium and titanium containing films using bis titanium as a precursor|

US5381302A|1993-04-02|1995-01-10|Micron Semiconductor, Inc.|Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same|

US5246881A|1993-04-14|1993-09-21|Micron Semiconductor, Inc.|Low-pressure chemical vapor deposition process for depositing high-density, highly-conformal, titanium nitride films of low bulk resistivity|

US5399379A|1993-04-14|1995-03-21|Micron Semiconductor, Inc.|Low-pressure chemical vapor deposition process for depositing high-density, highly-conformal titanium nitride films of low bulk resistivity|

US5393564A|1993-05-14|1995-02-28|Micron Semiconductor, Inc.|High efficiency method for performing a chemical vapor deposition utilizing a nonvolatile precursor|

US5425392A|1993-05-26|1995-06-20|Micron Semiconductor, Inc.|Method DRAM polycide rowline formation|

US5341016A|1993-06-16|1994-08-23|Micron Semiconductor, Inc.|Low resistance device element and interconnection structure|

US5384289A|1993-06-17|1995-01-24|Micron Semiconductor, Inc.|Reductive elimination chemical vapor deposition processes utilizing organometallic precursor compounds in semiconductor wafer processing|

US5384284A|1993-10-01|1995-01-24|Micron Semiconductor, Inc.|Method to form a low resistant bond pad interconnect|

JP2684979B2|1993-12-22|1997-12-03|日本電気株式会社|Semiconductor integrated circuit device and method of manufacturing the same|

US5496762A|1994-06-02|1996-03-05|Micron Semiconductor, Inc.|Highly resistive structures for integrated circuits and method of manufacturing the same|

US5665640A|1994-06-03|1997-09-09|Sony Corporation|Method for producing titanium-containing thin films by low temperature plasma-enhanced chemical vapor deposition using a rotating susceptor reactor|

US5747116A|1994-11-08|1998-05-05|Micron Technology, Inc.|Method of forming an electrical contact to a silicon substrate|

US5575708A|1995-06-07|1996-11-19|Alligiance Corporation|Belt grinding machine and method for forming cutting edges on surgical instruments|

US5641545A|1995-06-07|1997-06-24|Micron Technology, Inc.|Method to deposit highly conformal CVD films|

US5644166A|1995-07-17|1997-07-01|Micron Technology, Inc.|Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts|

US5595784A|1995-08-01|1997-01-21|Kaim; Robert|Titanium nitride and multilayers formed by chemical vapor deposition of titanium halides|

JP3443219B2|1995-11-14|2003-09-02|株式会社日立製作所|Semiconductor integrated circuit device and method of manufacturing the same|

US5773890A|1995-12-28|1998-06-30|Nippon Steel Corporation|Semiconductor device that prevents peeling of a titanium nitride film|

US5607722A|1996-02-09|1997-03-04|Micron Technology, Inc.|Process for titanium nitride deposition using five-and six-coordinate titanium complexes|

DE19612725A1|1996-03-29|1997-10-02|Siemens Ag|Process for the metallization of submicron contact holes in semiconductor bodies|

US5633200A|1996-05-24|1997-05-27|Micron Technology, Inc.|Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer|

JP3105788B2|1996-07-15|2000-11-06|日本電気株式会社|Method for manufacturing semiconductor device|

US5834371A|1997-01-31|1998-11-10|Tokyo Electron Limited|Method and apparatus for preparing and metallizing high aspect ratio silicon semiconductor device contacts to reduce the resistivity thereof|

US5976976A|1997-08-21|1999-11-02|Micron Technology, Inc.|Method of forming titanium silicide and titanium by chemical vapor deposition|US5976976A|1997-08-21|1999-11-02|Micron Technology, Inc.|Method of forming titanium silicide and titanium by chemical vapor deposition|

US5930671A|1997-10-20|1999-07-27|Industrial Technology Research Institute|CVD titanium silicide for contract hole plugs|

US6215186B1|1998-01-12|2001-04-10|Texas Instruments Incorporated|System and method of forming a tungstein plug|

US6143362A|1998-02-25|2000-11-07|Micron Technology, Inc.|Chemical vapor deposition of titanium|

US6284316B1|1998-02-25|2001-09-04|Micron Technology, Inc.|Chemical vapor deposition of titanium|

JP3514423B2|1998-10-23|2004-03-31|沖電気工業株式会社|Method of forming TiSi2 layer|

US6245674B1|1999-03-01|2001-06-12|Micron Technology, Inc.|Method of forming a metal silicide comprising contact over a substrate|

US6444556B2|1999-04-22|2002-09-03|Micron Technology, Inc.|Chemistry for chemical vapor deposition of titanium containing films|

US7060584B1|1999-07-12|2006-06-13|Zilog, Inc.|Process to improve high performance capacitor properties in integrated MOS technology|

US20020009880A1|1999-08-27|2002-01-24|Qing-Tang Jiang|Metal barrier for copper interconnects that incorporates silicon in the metal barrier or at the copper/metal barrier interface|

US7388289B1|1999-09-02|2008-06-17|Micron Technology, Inc.|Local multilayered metallization|

KR100407684B1|2000-06-28|2003-12-01|주식회사 하이닉스반도체|Method of manufacturing a semiconductor device|

US6355561B1|2000-11-21|2002-03-12|Micron Technology, Inc.|ALD method to improve surface coverage|

KR100385947B1|2000-12-06|2003-06-02|삼성전자주식회사|Method of forming thin film by atomic layer deposition|

US6838380B2|2001-01-26|2005-01-04|Fei Company|Fabrication of high resistivity structures using focused ion beams|

US6696368B2|2001-07-31|2004-02-24|Micron Technology, Inc.|Titanium boronitride layer for high aspect ratio semiconductor devices|

US6746952B2|2001-08-29|2004-06-08|Micron Technology, Inc.|Diffusion barrier layer for semiconductor wafer fabrication|

US6664181B2|2001-12-07|2003-12-16|Matsushita Electric Industrial Co., Ltd.|Method for fabricating semiconductor device|

US6586285B1|2002-03-06|2003-07-01|Micron Technology, Inc.|Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers|

US6730355B2|2002-03-06|2004-05-04|Micron Technology, Inc.|Chemical vapor deposition method of forming a material over at least two substrates|

US6767823B2|2002-03-06|2004-07-27|Micron Technology, Inc.|Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers|

US6991653B2|2002-03-21|2006-01-31|Sdgi Holdings, Inc.|Vertebral body and disc space replacement devices|

GB0218417D0|2002-08-08|2002-09-18|Seagate Technology Llc|Combined atomic layer deposition and damascene processing for definition of narrow trenches|

KR100476939B1|2003-06-05|2005-03-16|삼성전자주식회사|Method for forming contact in semiconductor resistor device|

KR100714269B1|2004-10-14|2007-05-02|삼성전자주식회사|Method for forming metal layer used the manufacturing semiconductor device|

KR100604089B1|2004-12-31|2006-07-24|주식회사 아이피에스|Method for depositing thin film on wafer by in-situ|

JP4778765B2|2005-10-07|2011-09-21|富士通セミコンダクター株式会社|Semiconductor device and manufacturing method thereof|

EP1969153A2|2005-11-28|2008-09-17|Pacific Biosciences of California, Inc.|Uniform surfaces for hybrid material substrates and methods for making and using same|

US20080080059A1|2006-09-28|2008-04-03|Pacific Biosciences Of California, Inc.|Modular optical components and systems incorporating same|

JP5211503B2|2007-02-16|2013-06-12|富士通セミコンダクター株式会社|Manufacturing method of semiconductor device|

JP2007294994A|2007-06-25|2007-11-08|Renesas Technology Corp|Method of manufacturing semiconductor device|

US8617668B2|2009-09-23|2013-12-31|Fei Company|Method of using nitrogen based compounds to reduce contamination in beam-induced thin film deposition|

US10971366B2|2018-07-06|2021-04-06|Applied Materials, Inc.|Methods for silicide deposition|

KR20210046079A|2018-09-18|2021-04-27|어플라이드 머티어리얼스, 인코포레이티드|In-situ integrated chambers|

US11114320B2|2018-12-21|2021-09-07|Applied Materials, Inc.|Processing system and method of forming a contact|

US11195923B2|2018-12-21|2021-12-07|Applied Materials, Inc.|Method of fabricating a semiconductor device having reduced contact resistance|

KR20210111894A|2019-02-08|2021-09-13|어플라이드 머티어리얼스, 인코포레이티드|Semiconductor devices, methods of manufacturing semiconductor devices, and processing systems|

KR102045277B1|2019-05-27|2019-11-15|주식회사 오투|Detachable oxygen concentration and hazardous gas alarm using band|

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2003-07-22| CC| Certificate of correction|

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优先权:

申请号 | 申请日 | 专利标题

US08/915,986|US5976976A|1997-08-21|1997-08-21|Method of forming titanium silicide and titanium by chemical vapor deposition|

US09/377,253|US6208033B1|1997-08-21|1999-08-19|Apparatus having titanium silicide and titanium formed by chemical vapor deposition|

US09/789,999|US6472756B2|1997-08-21|2001-02-21|Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus|US09/789,999| US6472756B2|1997-08-21|2001-02-21|Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus|

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