 Semiconductor device and a method of manufacturing the same
专利摘要:
Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes. Since the separation of the hole-free support substrate from the support substrate having the holes depends on heating and sliding, it can be carried out in a short time. Since the adhesive layer is melted by solvent which enters through the holes, the separation of the wafer in a short time is allowed. Both work do not put a load on the wafer and hence damage is prevented from occurring. 公开号:US20010005043A1 申请号:US09/734,927 申请日:2000-12-13 公开日:2001-06-28 发明作者:Masaki Nakanishi；Susumu Sorimachi；Kiichi Yamashita；Hiroji Yamada；Kikuo Fukushima 申请人:Hitachi Ltd；Hitachi Tohbu Semiconductor Ltd； IPC主号:H01L21-6835
专利说明:
[0001] The present invention relates to a semiconductor device and a method of manufacturing it, and particularly to a technology effective for application to a technology for grinding the back of a semiconductor substrate (semiconductor wafer) with semiconductor elements formed thereon to thereby thin the semiconductor substrate. [0001] [0002] As semiconductor elements operated at high speed, for example, a GaAs-MESFET (Metal Semiconductor Field Effect Transistor), an HEMT (High Electron Mobility Transistor), and an HBT (Hetero Junction Bipolar Transistor) are used in a high-frequency power amplifying module built in a radio communication apparatus such as a cellular phone system. [0002] [0003] As for these semiconductor elements, there is known one which adopts a so-called PHS (Plated Heat Sink) wherein via holes extending from the surface (main surface) of a semiconductor substrate to the back thereof are provided and conductors are provided in the via holes to electrically connect predetermined electrodes on the surface of the semiconductor substrate to a metal layer provided on the back of the semiconductor substrate, and in which the thickness of the semiconductor substrate is made thin and the length of each via hole is shortened to reduce inductance, whereby an increase in high-frequency characteristic is achieved. [0003] [0004] A technology for thinning the semiconductor substrate to 100 μm or less has been disclosed in, for example, Japanese Patent Application Laid-Open Nos. Hei 10(1998)-294246 and Hei 5(1993)-335292. The former publication has described a method of increasing the temperature of wax to the neighborhood of a melting point after the thinning of a semiconductor substrate bonded to a reinforcing plate with wax has been completed, and peeling the semiconductor substrate from the reinforcing plate while the wax is being melted. [0004] [0005] A technology for thinning the semiconductor substrate to 25 μm has been disclosed in Japanese Patent Application Laid-Open No. Hei 7(1995)-221051. This reference describes a GaAsFET used for ultra high-frequency applications. The GaAsFET has a PHS structure wherein a metal layer, which acts as a heat sink, is provided on the reverse side (back) of a semiconductor substrate. Further, the present reference also discloses a technology for bonding the surface of the semiconductor substrate to a protective plate such as glass with wax and thereafter the wax is melted by solvent to separate a semiconductor chip brought to a PHS structure from a glass substrate. [0005] SUMMARY OF THE INVENTION [0006] Thinning a semiconductor element (semiconductor chip) built in a high-frequency power amplifying module (high-frequency power amplifier) is essential for improvements in high-frequency characteristics and heat dissipation. [0006] [0007] Conventionally, a compound semiconductor substrate (semiconductor wafer: also called simply “wafer”) such as GaAs or the like on which transistors such as a GaAs-MESFET, an HEMT, an HBT, etc. are formed, is prepared and thereafter the semiconductor wafer is fixed to a support substrate such as a glass substrate with an adhesive layer such as wax, followed by thinning of the semiconductor wafer. [0007] [0008] (1) A method of heating and melting the wax to peel the semiconductor wafer from the glass substrate and (2) a method of melting the wax by solvent to separate the semiconductor wafer from the glass substrate have been adopted for the separation of the semiconductor wafer from the glass substrate. [0008] [0009] In the former heating method, however, the semiconductor wafer must be separated by applying an external force thereto, and the thinned wafer is often cracked and broken, thus interfering with an improvement in yields. [0009] [0010] In the latter solvent-based melting method, since the solvent is hard to sink in the wax, the time required to perfectly separate the semiconductor wafer from the glass substrate is spent and hence productivity is low. In the case of a wafer having a diameter of 3 inches, for example, about one week is required for its separation. Incidentally, there is known a technique (Japanese Patent Application Laid-Open No. Hei 7(1995)-37768) wherein trenches are defined in the surface of a reinforcing member (support substrate) and bubbles developed in an adhesive for bonding the reinforcing member and a wafer to each other are caused to escape to the outside through the trenches. When the reinforcing member is used for the support substrate, a manufacturing process (e.g., PHS structure manufacturing process) for effecting back processing such as plating on the back of a wafer after the thinning of the wafer to thereby form an electrode layer has the potential of melting out wax from trenches and thereby deteriorating the quality of a plated film. [0010] [0011] An object of the present invention is to provide a technology for manufacturing a semiconductor device, which is capable of performing the thinning of a semiconductor wafer and the separation of it from a support substrate with high yields. [0011] [0012] Another object of the present invention is to provide a technology for manufacturing a semiconductor device, which is capable of performing the thinning of a semiconductor wafer and the separation of it from a support substrate in a short time. [0012] [0013] A further object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of manufacturing a semiconductor chip having a PHS structure with high yields and in a short time. [0013] [0014] The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. [0014] [0015] A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows: [0015] [0016] The present invention includes the steps of: [0016] [0017] preparing a support substrate having a first surface and a second surface opposite to the first surface and having a plurality of holes extending from the first surface to the second surface, a hole-free support substrate having a first surface and a second surface opposite to the first surface, and a semiconductor wafer which has a main surface and a back opposite to the main surface, and semiconductor elements formed in each individuals of a plurality of semiconductor chip forming areas, and which has, on the main surface, an etching stopper layer comprised of a conductor electrically connected to a predetermined electrode constituting each semiconductor element, and a metal layer provided so as to overlap with a scribing area around each semiconductor chip forming areas [0017] [0018] bonding the hole-free support substrate to the second surface of the support substrate having the holes with an adhesive layer melted by heating so as to block the holes; [0018] [0019] bonding the main surface of the semiconductor wafer to the first surface of the support substrate having the holes with an adhesive layer melted by solvent; [0019] [0020] thinning the back of the semiconductor wafer to a predetermined thickness by grinding and wet-etching; [0020] [0021] selectively etching the back of the semiconductor wafer to define first trenches (separation trenches for division into pieces of semiconductor chips) which reach the metal layer formed in the scribing area, and second trenches (via holes) which reach the etching stopper layer; [0021] [0022] forming a electrode layer on the whole range of the back of the semiconductor wafer to provide a PHS structure; [0022] [0023] melting the adhesive layer by heating and sliding the support substrate having the holes with respect to the hole-free support substrate to thereby separate the support substrate having the holes therefrom; [0023] [0024] supplying solvent from the second surface of the support substrate having the holes through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate and the semiconductor wafer to each other; [0024] [0025] peeling a group of the semiconductor chips arranged in plate form, which are mutually connected by the electrode layer and the metal layer formed in the scribing area, from the support substrate having the holes; [0025] [0026] bonding a support tape (ultraviolet-ray cured adhesion type resin tape) to the electrode layer forming surface of the semiconductor chip group arranged in plate form; and [0026] [0027] cutting the electrode layer and metal layer for connecting the respective semiconductor chips of the semiconductor chip group arranged in plate form to one another to thereby separate the respective semiconductor chips. [0027] [0028] According to the present invention, a support substrate having holes or perforated support substrate, and a hole-free support substrate are separated from each other by heating and melting an adhesive layer provided therebetween and sliding the perforated support substrate with respect to the hole-free support substrate. Afterwards, an adhesive layer for bonding a semiconductor wafer and the perforated support substrate to each other is melted by solvent through the use of holes defined in the perforated support substrate. Therefore, the semiconductor wafer can be separated from the perforated support substrate in a time shorter than ever, and hence an improvement in productivity can be achieved. [0028] [0029] Since the separation of the semiconductor wafer depends on the melting of the adhesive layer by the solvent, no load is placed on the semiconductor wafer, cracks and breaks become hard to occur, and hence an improvement in yields can be achieved. [0029] [0030] Since separation trenches and via holes for bringing the semiconductor wafer into pieces of semiconductor chips are defined by etching after the thinning of the semiconductor wafer, and an electrode layer is formed on the back of the semiconductor wafer, a thinned PHS structure can easily be manufactured. [0030] BRIEF DESCRIPTION OF THE DRAWINGS [0031] While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: [0031] [0032] FIGS. [0032] 1(a) to 1(c) are typical diagrams showing a method of manufacturing a semiconductor device, according to one embodiment (first embodiment) of the present invention; [0033] FIG. 2 is a typical diagram illustrating a perforated support substrate and a semiconductor wafer employed in the first embodiment; [0033] [0034] FIG. 3 is a cross-sectional view of a semiconductor chip manufactured by a method of manufacturing a semiconductor device, according to another embodiment (second embodiment) of the present invention; [0034] [0035] FIG. 4 is a typical plan view of the semiconductor chip; [0035] [0036] FIG. 5 is a flowchart for describing the method of manufacturing the semiconductor device, according to the second embodiment; [0036] [0037] FIG. 6 is an enlarged cross-sectional view of the bilayer-structured support substrate and a wafer attached to the substrate; [0037] [0038] FIG. 7 is a cross-sectional view showing a wafer and a substrate thin-layered in the manufacturing method according to the first embodiment; [0038] [0039] FIG. 8 is a cross-sectional view showing a wafer in which etching is done from the back of the wafer to separate chip forming areas from one another, whereby a plurality of semiconductor chips are formed therein, and via holes are defined in the respective semiconductor chips, and a support substrate both employed in the manufacturing method according to the first embodiment; [0039] [0040] FIG. 9 is a cross-sectional view showing the state in which a metal layer is formed over the whole area on the first surface side, of the support substrate on which the semiconductor chips exist, in the manufacturing method according to the first embodiment; [0040] [0041] FIG. 10 is a cross-sectional view illustrating the state in which the perforated support substrate is separated from the hole-free support substrate in the manufacturing method according to the first embodiment; [0041] [0042] FIG. 11 is a cross-sectional view showing the state in which the perforated support substrate and a semiconductor chip group brought into integral form by the metal layer are separated from each other in the manufacturing method according to the first embodiment; [0042] [0043] FIG. 12 is a cross-sectional view depicting the state in which the semiconductor chip group brought into integral form by the metal layer is attached to a support tape in the manufacturing method according to the first embodiment; [0043] [0044] FIG. 13 is a cross-sectional view showing the state in which the metal layer lying between the semiconductor chips on the support tape is cut off to provide chip separation in the manufacturing method according to the first embodiment; [0044] [0045] FIG. 14 is a typical plan view illustrating the semiconductor chips on the support tape; [0045] [0046] FIG. 15 is a typical cross-sectional view of a high-frequency power amplifying module in which the semiconductor chips manufactured by the manufacturing method according to the first embodiment are built; [0046] [0047] FIG. 16 is a typical cross-sectional view showing the semiconductor chip fixed with a thick adhesive in the high-frequency power amplifying module; [0047] [0048] FIG. 17 is a typical diagram showing part of a method of manufacturing a semiconductor device according to a further embodiment (third embodiment) of the present invention; [0048] [0049] FIG. 18 is a typical plan view of a perforated support substrate used in a method of manufacturing a semiconductor device, according to a still further embodiment (fourth embodiment) of the present invention; [0049] [0050] FIG. 19 is a typical plan view showing the state in which a wafer and a support substrate employed in a method of manufacturing a semiconductor device, according to a still further embodiment (fifth embodiment) of the present invention are applied to each other; [0050] [0051] FIG. 20 is a flowchart showing a method of manufacturing a semiconductor device, according to a still further embodiment (sixth embodiment) of the present invention; [0051] [0052] FIG. 21 is a cross-sectional view showing the state in which a metal layer formed on the back of a wafer is cut in dicing areas to provide chip separation in the manufacturing method according to the sixth embodiment; [0052] [0053] FIG. 22 is a cross-sectional view illustrating the state in which a support tape is applied onto a semiconductor chip group separated in the manufacturing method according to the sixth embodiment; [0053] [0054] FIG. 23 is a cross-sectional view depicting the state in which a support substrate (hole-free support substrate) is separated from the semiconductor chip group in the manufacturing method according to the sixth embodiment; and [0054] [0055] FIG. 24 is a cross-sectional view showing the semiconductor chip group applied to the support tape in the manufacturing method according to the sixth embodiment. [0055] DESCRIPTION OF THE PREFERRED EMBODIMENTS [0056] Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings. Incidentally, elements of structure or components each having the same function in all the drawings for describing the embodiments of the present invention are identified by the same reference numerals and their repeated description will therefore be omitted. [0056] [0057] (First embodiment) [0057] [0058] FIGS. [0058] 1(a) through 1(c) and FIG. 2 are respectively diagrams related to a method of manufacturing a semiconductor device, according to one embodiment (first embodiment) of the present invention. FIGS. 1(a) through 1(c) are typical diagrams showing a thickness reduction in a semiconductor wafer and a method of separating the semiconductor wafer from a support substrate, and FIG. 2 is a typical diagram showing the semiconductor wafer applied onto a perforated support substrate, respectively. [0059] As shown in FIG. 1([0059] a), a semiconductor wafer 30 is first applied or bonded to a bilayer-structured support substrate. In the semiconductor wafer 30, although not illustrated in the drawing, scribing areas are provided so as to extend on the main surface side thereof in all directions. Semiconductor elements such as an HBT, etc. are formed in a rectangular area surrounded by the scribing areas. The main surface of the semiconductor wafer 30 is bonded to a first surface of a perforated support substrate 32 with or by an adhesive layer 36 interposed therebetween. The back opposite to the main surface of the semiconductor wafer 30 serves as a processing surface for a reduction in thickness thereof. The semiconductor wafer 30 has a thickness of 600 μm, for example. [0060] As shown in FIG. 1([0060] a), the bilayer-structured support substrate has a structure wherein a support substrate free of holes 31 (called “non-perforated or hole-free support substrate 34”) and a support substrate with the holes 31 defined therein (called “perforated support substrate 32”) are bonded to each other with an adhesive layer 33 interposed therebetween. The holes 31 are through holes which extend from a first surface of the perforated support substrate 32 to a second surface thereof corresponding to the back thereof opposite to the first surface. The second surface of the perforated support substrate 32 is bonded to a first surface of the hole-free support substrate 34 with the adhesive layer 33 interposed therebetween. A second surface of the hole-free support substrate 34, which is opposite to the first surface of the hole-free support substrate 34, serves as an exposed surface. [0061] As shown in FIG. 2, the perforated support substrate [0061] 32 takes the shape of a circular disc whose part is linearly cut away. This linear portion serves as orientation flat (OF) indicative of an orientation. Further, the holes 31 are arranged in the perforated support substrate 32 so as not to exist in the edge of the semiconductor wafer 30 and outside it. Thus, one ends of the holes 31 are blocked by the hole-free support substrate 34, whereas the other ends thereof are blocked by the semiconductor wafer 30. [0062] This is done to prevent the trouble that if the holes [0062] 31 exist in the edge of the semiconductor wafer 30 and in an area out of the semiconductor wafer 30 where plating or the like is done according to the semiconductor device manufacturing method, the adhesive layer 33 for applying the perforated support substrate 32 and the hole-free support substrate 34 to each other exists in the bottom of each hole 31, whereby the adhesive layer 33 is melted by a plating solution and a plating bath is contaminated, so that satisfactory plating formation cannot be carried out. [0063] The perforated support substrate [0063] 32 and the hole-free support substrate 34 are identical in size to each other although their outer shapes are not limited in particular. Further, they are respectively formed of a material resistant to heat and excellent in resistance-to-chemicals, e.g., a glass plate such as quartz glass. The adhesive layer 33 for bonding the perforated support substrate 33 and the hole-free support substrate 34 to each other makes use of a material melted by heating, e.g., wax. The adhesive layer 36 for bonding the semiconductor wafer 30 to the first surface of the perforated support substrate 32 makes use of a material melted by a solvent, e.g., wax. [0064] Since priority is given to flatness, liquid wax is used for these adhesive layers [0064] 33 and 36 and rotated at high speed by a spin coater to provide their flatnesses. As the wax, is used one which is 30 cps in viscosity at 25° C. and has a flow start temperature of about 72° C. [0065] Next, the back of the semiconductor wafer [0065] 30 bonded to the bilayer-structured support substrate is removed by a predetermined thickness although not shown in the drawing to thereby achieve a reduction in the thickness of the wafer. Namely, the reverse side of the semiconductor wafer 30 is ground and wet-etched so that the thickness of the semiconductor wafer 30 reaches a predetermined thickness. For example, the thickness of the semiconductor wafer 30 is set to about 30 μm. [0066] Next, the hole-free support substrate [0066] 34 is removed as shown in FIG. 1(b). In the present step, the adhesive layer 33 for bonding the hole-free support substrate 34 and the perforated support substrate 32 to each other is heated and melted. Further, the perforated support substrate 32 is slid (slid in the direction indicated by arrow) relative to the hole-free support substrate 34 to separate the perforated support substrate 32 form the hole-free support substrate 34. For example, the adhesive layer 33 is heated to about 110° C. and melted. [0067] Since no external force acts on the semiconductor wafer [0067] 30, the semiconductor wafer 30 is not cracked or broken. Further, since the present working is short-time slide working except for the time required to perform heating at a predetermined temperature, working time can be shortened. [0068] Next, the perforated support substrate [0068] 32 is removed as shown in FIG. 1(c). In the present step, the adhesive layer 36 for bonding the semiconductor wafer 30 and the perforated support substrate 32 to each other is melted with an solvent to thereby separate the perforated support substrate 32 from the semiconductor wafer 30. For example, the perforated support substrate 32 with the semiconductor wafer 30 attached thereto is immersed in IPA (Isopropyl alcohol) to solve the adhesive layer 36. At this time, supersonic vibrations are applied to accelerate its dissolution. Since the solvent reaches the adhesive layer 36 through the respective holes 31 defined in the perforated support substrate 32, and the holes 31 are densely defined in their corresponding locations, the time required to separate the perforated support substrate 32 from the semiconductor wafer 30 is greatly shortened as compared with the conventional one. While the conventional method needed about one week in the case of a wafer having a diameter of 3 inches, for example, the separation time can be reduced to about 4 hours in the first embodiment. [0069] According to the method of manufacturing the semiconductor device, according to the first embodiment, the following advantageous effects are brought about: [0069] [0070] (1) When the semiconductor wafer [0070] 30 is separated from the bilayer-structured support substrate after the reduction in the thickness of the semiconductor wafer 30, the following is done as a first-stage job. Namely, the adhesive layer 33 for bonding the perforated support substrate 32 and the hole-free support substrate 34 to each other is melted by heating, and the perforated support substrate 32 free from the need for mutual care of the break and cracks between the perforated support substrate 32 and the hole-free support substrate 32 is slid relative to the hole-free support substrate 34 for their separation. Thereafter, the following is done as a second-stage job. Namely, the solvent is caused to pass through the holes 31 defined in the perforated support substrate 32 to melt and disappear or eliminate the adhesive layer 36 for bonding the semiconductor wafer 30 and the perforated support substrate 32 to each other. Thus, since no external force acts on the semiconductor wafer 30, the semiconductor wafer 30 is separated from the perforated support substrate 32. Accordingly, the semiconductor wafer 30 can be separated without developing cracks and breaks in the thinned semiconductor wafer 30, thus enhancing yields. [0071] (2) Since the separation of the semiconductor wafer [0071] 30 from the support substrate is done using the holes defined in the perforated support substrate 32, such separation can be carried out in a short time as compared with the conventional one, and the manufacturing cost of the semiconductor device can be reduced. [0072] (3) While the perforated support substrate [0072] 32 is used, the holes 31 defined in the perforated support substrate 32 are blocked by the semiconductor wafer 30 and the hole-free support substrate 34 in a process up to the separation of the semiconductor wafer 30. Therefore, the adhesive layer 36 for bonding the perforated support substrate 32 and the semiconductor wafer 30 to each other, and the adhesive layer 33 for bonding the perforated support substrate 32 and the hole-free support substrate 34 to each other are melted without contact with the plating solution or the like used in processing and hence the adhesive is diffused into the solution. The exposed surface of the semiconductor wafer 30 is prevented from being subjected to damage and contaminated by the adhesive. Accordingly, a semiconductor device excellent in quality can be manufactured. [0073] (Second embodiment) [0073] [0074] FIGS. 3 through 16 are respectively diagrams related to a method of manufacturing a semiconductor device, according to another embodiment (second embodiment) of the present invention. [0074] [0075] In the present embodiment, an example in which the present invention is applied to the technology of manufacturing an HBT, will be explained. The HBT manufactured by the manufacturing method according to the second embodiment will now be described with reference to FIGS. 3 and 4. FIG. 3 is a cross-sectional view of an HBT semiconductor chip, and FIG. 4 is a typical plan view showing respective semiconductor regions (emitter, base and collector) and partial electrodes of the HBT semiconductor chip, respectively. [0075] [0076] A semiconductor chip [0076] 20 with the HBT formed therein is formed on the basis of a semi-insulating GaAs substrate 1 as shown in FIG. 3. Namely, an n+type GaAs sub-collector layer 2 and an n type GaAs collector layer 3 formed on the n+type GaAs sub-collector layer 2 are selectively provided on a main surface of the semi-insulating GaAs substrate 1. Further, the n type GaAs collector layer 3 has a peripheral portion etched to a depth at a midpoint in the same layer, and a central portion formed as an protruded mesa portion. In an area in which the thin n type GaAs collector layer 3 away from the mesa portion is formed, the n type GaAs collector layer 3 is partly removed by etching, and collector electrodes 4 are respectively formed at the removed portions. [0077] A p[0077] +type GaAs base layer 5, an n type InGaP emitter layer 6, and an n+type GaAs cap layer 7 are successively provided on the mesa portion so as to overlap each other. The p+type GaAs base layer 5 and the n type InGaP emitter layer 6 are coincidentally superimposed on each other with substantially the same size. However, the n+type GaAs cap layer 7 is formed in the center of the mesa portion in the form of a slender rectangle. [0078] In a mesa area out of the n[0078] +type GaAs cap layer 7, the n type InGaP emitter layer 6 and the p+type GaAs base layer 5 are selectively removed by etching to form contact holes. Base electrodes 8 are provided in their corresponding contact holes. [0079] Further, an emitter electrode [0079] 9 is formed on the upper surface of the n+type GaAs cap layer 7. An emitter wiring layer 10 is formed on the emitter electrode 9. Some of the emitter wiring layer 10 extends even to the surface of the semi-insulating GaAs substrate 1 away from the n+type GaAs sub collector layer 2 and the n type GaAs collector layer 3. [0080] The respective portions on the main surface side of the semi-insulating GaAs substrate [0080] 1 are covered with an insulating film 11 to achieve device or element protection. While the insulating film 11 is represented as a single layer in the drawing, it is actually represented as a plurality of layers, and their patterns are different from each other in the respective layers. [0081] Since the HBT fabricated in the second embodiment is used as a PHS, an electrode layer [0081] 12 is formed on the back side of the semi-insulating GaAs substrate 1 over its overall area. In order to electrically connect the electrode layer 12 and the emitter wiring layer 10 placed over the semi-insulating GaAs substrate 1, a second trench (via hole) 13 is defined over the range of the main surface of the semi-insulating GaAs substrate 1 to the back thereof. An end on the main surface side of the semi-insulating GaAs substrate 1, of the via hole 13 is blocked by its corresponding etching stopper layer 14 formed of a conductor. The etching stopper layer 14 is provided on the main surface side of the semi-insulating GaAs substrate 1 before the via hole 13 is defined. The etching stopper layer 14 and the emitter wiring layer 10 are electrically connected to each other by a wiring layer 15 extending over the insulating film 11. [0082] The electrode layer [0082] 12 has a structure which cover even the peripheral surface of the semiconductor chip 20. A tip or leading portion thereof is superimposed on a metal layer 16 (see FIG. 4) provided on the main surface of the semi-insulating GaAs substrate 1. In a state of the semiconductor wafer prior to the formation of the semiconductor chip 20, the metal layer 16, which serves as the etching stopper layer, is formed so as to overlap with its corresponding scribing area (also called dicing area) on the main surface of the semiconductor wafer. Upon etching of each scribing area on the back side of the semiconductor wafer brought into semiconductor chip form, etching is done so as to reach the metal layer 16. Finally, the metal layer 16 and the electrode layer 12 superimposed on the metal layer 16 are cut off along the scribing area to thereby form each semiconductor chip. [0083] Incidentally, the scribing area has a predetermined width and is provided on the main surface of the semiconductor wafer in lattice form. For example, the scribing area is cut by dicing. In the second embodiment, the metal layer [0083] 16 and the electrode layer 12 are formed of gold. Since, at this time, gold is excellent in malleability upon the dicing, projections 12 called burrs are apt to occur in their cut-off ends (see FIG. 16). [0084] Thus, when the semiconductor chip [0084] 20 is fixed to a mounted board or substrate 22 with the adhesive layer interposed therebetween to thereby a semiconductor device (electronic equipment), gaps or the like occur in their bonded portion due to projections if the adhesive layer is thin. Thus, it is not possible to allow heat generated in the semiconductor chip to effectively escape to the mounted substrate. A reduction in the life of the HBT and a reduction in reliability occur. [0085] Therefore, the following is carried out in the second embodiment. While it is one of the characteristics of the present invention, a semiconductor chip [0085] 20 is fixed to its corresponding mounted substrate 22 with an adhesive layer 23 thicker than a produced projection 21 longest in length as shown in FIG. 16. Since the adhesive layer 23 effectively transfers heat generated in the semiconductor chip 20 to the mounted substrate 22, it makes use of an adhesive material having high thermal conductivity. [0086] The method of manufacturing the semiconductor chip [0086] 20 will next be explained. In the method of manufacturing the semiconductor device, work is started [Step 101 (S101)] as shown in a flowchart of FIG. 5. Thereafter, a semiconductor wafer is bonded to a support substrate [corresponding to a bilayer-structured support substrate comprised of perforated support substrate and hole-free support substrate] (S102), the semiconductor wafer is thinned (S103), holes are defined in a via/scribing area (S104), an electrode layer is formed (S105), the hole-free support substrate is removed by heating and melting (S106), a solvent is melted to remove the perforated support substrate (S107), a support tape is applied or bonded to the wafer (S108), and chip separation using dicing is carried out (S109) . The present work is finished through these (S110). [0087] The method will be described below in accordance with the respective steps and with reference to the respective drawings. Incidentally, for convenience of description, the method will be explained in a state in which only two HBT (semiconductor elements) are drawn as viewed in a cross section of the semiconductor wafer. [0087] [0088] As shown in FIG. 6, a support substrate [0088] 32 having a plurality of holes 31 (perforated support substrate) is first laminated with a support substrate free of holes (hole-free support substrate) 34 with an adhesive layer 33 interposed therebetween. Further, a semiconductor wafer (wafer) 30 is bonded or applied to one surface (first surface) of the perforated support substrate 32 with an adhesive layer 36 interposed therebetween (S102). [0089] The semiconductor wafer [0089] 30 is provided with scribing areas so as to extend on the main surface side thereof in all directions. The aforementioned HBT (semiconductor elements) 19 are formed in a rectangular area surrounded by the scribing areas. The main surface of the semiconductor wafer 30 is bonded to the first surface of the perforated support substrate 32 with the adhesive layer 36 interposed therebetween. [0090] In this state, however, the exposed back of the semiconductor wafer (semi-insulating GaAs substrate [0090] 1) is not processed, and no via holes and electrode layer are formed. Thus, the back of the semi-insulating GaAs substrate 1 is kept flat. Further, the thickness of the semiconductor wafer 30 is set to about 600 μm, for example. As shown in FIG. 6, a metal layer 16 used as an etching stopper layer is provided at a portion corresponding to the scribing area on the main surface side in a subsequent process. An etching stopper layer 14 is provided so as to correspond to each via hole forming portion. Finally, the semiconductor wafer 30 is diced along the center of the scribing area so as to be brought into a plurality of semiconductor chips. Thus, the area prior to being separated by dicing becomes a semiconductor chip forming area. [0091] The holes [0091] 31 are through holes which extend from the first surface of the perforated support substrate 32 to a second surface thereof corresponding to the back thereof opposite to the first surface. The second surface of the perforated support substrate 32 is bonded to a first surface of the hole-free support substrate 34 with the adhesive layer 33 interposed therebetween. The first surface of the hole-free support substrate 34 serves as an exposed surface. Owing to the bonding of the two, a bilayer-structured support substrate is formed. [0092] In a manner similar to the first embodiment, the perforated support substrate [0092] 32 comprises a disc having orientation flat at its part. Further, the holes 31 are arranged in the perforated support substrate 32 so as not to exist in the edge of the semiconductor wafer 30 and outside it (see FIG. 2). This results in that if the holes 31 exist in the edge of the semiconductor wafer 30 and in an area out of the semiconductor wafer 30 upon the formation of the electrode layer by plating to be done in a subsequent process, the adhesive layer 33 for bonding the perforated support substrate 32 and the hole-free support substrate 34 to each other exists in the bottom of each hole 31, whereby the adhesive layer 33 is dissolved or melted by a plating solution, thus interfering with satisfactory plating formation. One ends of the holes 31 are blocked by the hole-free support substrate 34, whereas the other ends thereof are blocked by the semiconductor wafer 30. [0093] No particular restrictions are imposed on outside dimensions of the perforated support substrate [0093] 32 and the hole-free support substrate 34. Further, the perforated support substrate 32 and the hole-free support substrate 34 are respectively formed of a material resistant to heat and excellent in resistance-to-chemicals, e.g., a glass plate such as quartz glass. The adhesive layer 33 for applying the perforated support substrate 33 and the hole-free support substrate 34 to each other makes use of a material melted by heating, e.g., wax. The adhesive layer 36 for bonding the semiconductor wafer 30 to the first surface of the perforated support substrate 32 makes use of a material melted by solvent, e.g., wax. [0094] Since priority is given to flatness, liquid wax is used for these adhesive layers [0094] 33 and 36 and rotated at high speed by a spin coater to provide their flatnesses. As the wax, is used one which is 30 cps in viscosity at 25° C. and has a flow start temperature of about 72° C. [0095] Next, as shown in FIG. 7, the back of the semiconductor wafer [0095] 30 is removed by a predetermined thickness. Namely, the reverse side of the semiconductor wafer 30 is ground and wet-etched so that the thickness of the semi-insulating GaAs substrate 1 reaches a predetermined thickness a (S103). For example, the thickness a thereof is set to about 30 μm. The above grinding is done using a grinding stone of #2000, for example, until the semi-insulating GaAs substrate 1 reaches 80 μm. Afterwards, the semi-insulating GaAs substrate 1 is etched to reach a thickness of 30 μm by wet etching with a mixture of, for example, H2SO4, H2O2 and H2O as an etchant. [0096] Next, an etching mask [0096] 37 is formed on the back of the semiconductor wafer 30 (semi-insulating GaAs substrate 1) as shown in FIG. 8. Thereafter, the semi-insulating GaAs substrate 1 is selectively etched by etching to thereby form separation trenches (first trenches) 38 and via holes (second trenches) 39. The etching mask 37 has such a shape as to expose an area corresponding to each scribing area and part (via hole forming area) of each semiconductor chip forming area. [0097] The etching is done according to, for example, two-stage etching of wet etching and dry etching. The wet etching is done using the etchant based on the mixture of, for example, H[0097] 2SO4, H2O2 and H2O. Holes defined by the etching are caused to reach the metal layer 16 provided in the scribing area and the etching stopper layer 14 provided in the via hole forming area. Afterwards, the dry etching is done using a mixed gas of Cl2 and SiCl4, for example, to ensure hole dimensions. [0098] The semiconductor wafer [0098] 30 is separated every semiconductor chip forming areas by the etching of the scribing area. Thus, the semiconductor wafer 30 is substantially divided into a plurality of semiconductor chips 20. After the completion of the etching, the etching mask 37 is removed. [0099] Next, an electrode layer [0099] 12 is formed over the entire range of the back of the semi-insulating GaAs substrate 1 as shown in FIG. 9 (S105) . The electrode layer 12 is formed by a sputtering method, e.g., by forming a species electrode (underelectrode) comprised of, for example, Pt, Ti, Pt and Au and thereafter plating Au on the species electrode. The thickness b of the electrode layer 12 formed by the species electrode and the plated layer is about 15 μm, for example. It is of importance that Au is reliably applied within the via holes 39 upon this plating. The electrode layer 12 extending on the back side of each semiconductor chip 20, and the emitter electrode of each HBT (semiconductor element) 19 are electrically connected to each other by the electrode layer 12 lying within each via hole 39 to provide a PHS structure. Further, the metal layer 16 and the electrode layer 12 overlap each other in the scribing area. Thus, even if the hole-free support substrate 34 is removed from the respective semiconductor chips 20, the respective semiconductor chips 20 become integral with the metal layer 16 and the electrode layer 12 to thereby make a single semiconductor chip group. [0100] Next, the hole-free support substrate [0100] 34 is removed as shown in FIG. 10 (S106). In the present step, a second surface of the hole-free support substrate 34 is placed on an unillustrated table heated to a predetermined temperature to melt the adhesive layer 33 for bonding the hole-free support substrate 34 and the perforated support substrate 32 to each other and thereby slide the perforated support substrate 32 (slide it in the direction indicated by arrow) with respect to the hole-free support substrate 34, thus separating the perforated support substrate 32 from the hole-free support substrate 34. For example, the hole-free support substrate 34 is placed on an iron plate heated to 110° C. to melt the adhesive layer 33. [0101] Next, as shown in FIG. 11, the perforated support substrate [0101] 32 is removed (S107). In the present step, the adhesive layer 36 for bonding the semiconductor chip 20 and the perforated support substrate 32 to each other is melted by solvent to thereby separate the perforated support substrate 32 form the semiconductor chip 20. For example, the perforated support substrate 32 with the semiconductor wafer 30 attached thereto is immersed in IPA (Isopropyl alcohol) to solve the adhesive layer 36. At this time, ultrasonic vibrations are applied to accelerate its dissolution. Since the solvent reaches the adhesive layer 36 through the respective holes 31 defined in the perforated support substrate 32, and the holes 31 are densely defined in their corresponding locations, the time required to separate the perforated support substrate 32 from the semiconductor wafer 30 is greatly shortened as compared with the conventional one. While the conventional method needed about one week in the case of a wafer having a diameter of 3 inches, for example, the separation time can be reduced to about 4 hours in the second embodiment. [0102] Next, as shown in FIG. 12, a support tape [0102] 40 is attached to the back (electrode layer 12) of each semiconductor chip 20 (S108). As the support tape 40, a normally-used dicing tape applied to the wafer upon dicing to support the wafer is used. For example, adhesion type resin tape cured in response to ultraviolet rays is used for the support tape 40. At this time, one uncured after the application of ultraviolet rays to the resin tape is used as paste for the ultraviolet-ray cured adhesion type resin tape. This is used to prevent paste from being put on Au-based burrs (projections 21) developed upon dicing in a subsequent process. [0103] Next, as shown in FIG. 13, the metal layer [0103] 16 and the electrode layer 12 superimposed thereon are cut by dicing along the center of each scribing area (cut points are indicated by arrows) to provide chip separation (S109). Namely, since the metal layer 16 and the electrode layer 12 having connected the respective semiconductor chips 20 are cut away, the semiconductor chips 20 are separated for every semiconductor chips 20. FIG. 14 is a plan view showing the four semiconductor chips 20 separated on the support tape 40. [0104] Since gold is excellent in malleability as described above upon the dicing, projections [0104] 12 called burrs are apt to occur long in their cut-off ends (see FIG. 16). However, since the paste of the ultraviolet-ray cured adhesion type resin tape makes use of one uncured after the application of the ultraviolet rays, the projections 21 are prevented from sticking to the paste. After the completion of a chip separating process, the work is ended (S110). [0105] Thereafter, the respective semiconductor chips [0105] 20 kept in a state of being attached to the support tape 40 are vacuum-absorbed and held by a normally-used vacuum absorption type pickup tool upon assembly of a semiconductor device such as a high-frequency power amplifying module. Thus, the semiconductor chips 20 are peeled off from the support tape 40 and chip-bonded to a mounted substrate. [0106] A high-frequency power amplifying module in which the semiconductor chips [0106] 20 are built, will now be described in brief. FIG. 15 is a typical cross-sectional view of a high-frequency power amplifying module 45. [0107] The high-frequency power amplifying module [0107] 45 has a module substrate (mounted or printed circuit board) 46 made up of a multilayer interconnection board, and a cap 47 for covering the main surface of the module substrate 46, and takes a rectangular structure flat as seen in appearance. A plurality of semiconductor chips 20 with HBT employed in the first embodiment incorporated therein are mounted in the module substrate 46. The respective transistors are successively cascade-connected to form amplifiers provided in a multistage configuration. Each of the semiconductor chips 20 is connected to a thermal diffusion plate 48 formed of a metal plate satisfactory in thermal conductivity at a hollow bottom provided in the main surface of the module substrate 46 by or with an adhesive layer 23 having high thermal conductivity. Since there may be cases in which the projections 21 are formed on the back side of each semiconductor chip 20 as described above, the adhesive layer 23 is formed so as to become thicker than the maximum one of protruded lengths of the projections 21. Further, the adhesive layer 23 causes even the tips or leading ends of the projections 21 to be reliably placed therewithin and prevents an adhesive failure developed due to the projections 21. The adhesive layer 23 is formed of silver paste, for example. [0108] Further, thermal vias [0108] 49 each charged with a metal satisfactory in thermal conductivity are formed at the hollow bottom in large numbers. The thermal vias 49 are connected to one of conductors 50 provided on the back of the module substrate 46. The conductors 50 are provided on the back of the module substrate 46 as appropriate and form surface-mounted external terminals respectively. Although not illustrated in particular, the external terminals constitute an input terminal, an output terminal, a control terminal (bias supply terminal), a first voltage terminal supplied with a source voltage, and a second voltage terminal used as ground. [0109] Other ends of conductive wirings [0109] 51 whose one ends are connected to their corresponding wirings 52 provided on the main surface of the module substrate 46, are connected to respective electrodes provided on the main surface of the semiconductor chip 20. A semiconductor chip 20 section including the wirings 51 is covered with an insulating resin 53 for the purpose of improving resistance to moisture. [0110] Chip resistors [0110] 54 and chip capacitors 55, which constitute a bias circuit, an impedance matching circuit, etc. are mounted on the main surface of the module substrate 46. Electrodes of these chip parts are respectively connected to unillustrated wirings. [0111] In the high-frequency power amplifying module [0111] 45, heat generated in each semiconductor chip 20 is successively transferred to the adhesive layer 23, the thermal diffusion plate 48, the thermal vias 49 and the conductor 50 and allowed to efficiently escape to a wiring board with the high-frequency power amplifying module 45 placed thereon. It is therefore possible to increase the life of the HBT and enhance the reliability thereof. [0112] Such a high-frequency power amplifying module [0112] 45 inputs or receives input power from an input terminal and outputs amplified output power from an output terminal although its circuit configuration is not shown. Further, a control voltage supplied to a control terminal is supplied to transistors provided in respective stages through a gate bias circuit to control an output voltage. [0113] According to the method of manufacturing the semiconductor device, according to the second embodiment, the following advantageous effects are brought about. [0113] [0114] (1) The semiconductor wafer [0114] 30 is thinned and brought into semiconductor chip form. Afterwards, the electrode layer 12 for providing the PHS structure is formed, and the semiconductor chips separated by the metal layer 16 used as the portion corresponding to the scribing area superimposed on the electrode layer 12 are formed as the single semiconductor chip group. In this condition, the single semiconductor chip group can be separated from the bilayer-structured support substrate by using the method similar to the first embodiment. It is therefore possible to prevent damage to the respective semiconductor chips. As a result, manufacturing yields can be enhanced and a reduction in the manufacturing cost of the semiconductor device can be achieved. [0115] (2) Since the adhesive layer [0115] 36 is melted by the solvent through the use of the holes defined in the perforated support substrate 32 to separate the single semiconductor chip group from the perforated support substrate 32, they can be separated from each other in a time shorter than ever, and the manufacturing cost of the semiconductor device can be reduced. [0116] (3) While the perforated support substrate [0116] 32 is used, the holes 31 of the perforated support substrate 32 are blocked by the semiconductor wafer 30 and the hole-free support substrate 34 in the process up to the separation of the semiconductor wafer 30. Therefore, the adhesive layer 36 for bonding the perforated support substrate 32 and the semiconductor wafer 30 to each other, and the adhesive layer 33 for bonding the perforated support substrate 32 and the hole-free support substrate 34 to each other are melted without contacting the plating solution or the like used in processing and hence the adhesive is diffused into the solution. The exposed surface of the semiconductor wafer 30 is prevented from being subjected to damage and contaminated by the adhesive. Accordingly, a semiconductor device excellent in quality can be manufactured. [0117] (4) Since the method of manufacturing the semiconductor device adopts a technique for connecting and holding up the divided plural semiconductor chips through the use of the electrode layer [0117] 12 of the PHS structure to form the single semiconductor chip group, applying the single semiconductor chip group to the support tape 40 after the separation of it from the support substrate, and cutting the electrode layer 12 and the metal layer 16 for connecting the respective semiconductor chips in the state in which the single semiconductor chip group is being bonded to the support tape 40 to thereby bring the single semiconductor chip group into the semiconductor chips 20, productivity is improved. [0118] (Third embodiment) [0118] [0119] FIG. 17 is a typical diagram showing part of a method of manufacturing a semiconductor device, according to a further embodiment (third embodiment) of the present invention. As shown in FIG. 17, holes [0119] 31 defined in a perforated support substrate 32 are provided as taper holes whose diameters gradually increase as they extend from a first surface to a second surface. Thus, the metabolism of solvent in each hole 31 is improved, and an adhesive layer 36 for bonding the perforated support substrate 32 and a semiconductor wafer 30 to each other is melted in a shorter time, thus shortening the time required to separate the semiconductor wafer 30 from the perforated support substrate 32. [0120] (Fourth embodiment) [0120] [0121] FIG. 18 is a typical plan view of a support substrate having holes used in a method of manufacturing a semiconductor device, according to a still further embodiment (fourth embodiment) of the present invention. As shown in FIG. 18, trenches [0121] 60 for allowing holes 31 to connect (communicate with) to a first surface thereof on which a semiconductor wafer is applied, are defined in a perforated support substrate 32 employed in the fourth embodiment in all directions. Since solvent can be transferred between the holes 31 through the trenches 60 in the present structure, an area where the solvent and an adhesive layer make contact with each other, increases, and the metabolism of the solvent is improved. Further, the adhesive layer is melted in a shorter time, whereby the time required to separate the semiconductor wafer from the perforated support substrate is shortened. [0122] (Fifth embodiment) [0122] [0123] FIG. 19 is a diagram related to a method of manufacturing a semiconductor device, according to a still further embodiment (fifth embodiment) of the present invention. In the present embodiment, a semiconductor wafer [0123] 30 is applied to a first surface of a perforated support substrate 32 with an adhesive layer 36, and an adhesive layer 61 melted by solvent is formed on a second surface of the perforated support substrate 32. When the semiconductor wafer 30 is separated from the perforated support substrate 32, the adhesive layer 61 is melted by the solvent so as to disappear, and the solvent is supplied through the opened holes 31 to melt the adhesive layer 36, thereby separating the semiconductor wafer 30 from the support substrate 32. As the adhesive layer 61, may be used, for example, an acrylic resin melted by a resist (acqueous ammonia: NH4OH). [0124] In a manner similar to the respective embodiments even in the case of the present embodiment, the semiconductor wafer [0124] 30 can be separated from the perforated support substrate 32 in a short time without damage to the semiconductor wafer 30. [0125] (Sixth embodiment) [0125] [0126] FIGS. 20 through 24 are respectively diagrams related to a method of manufacturing a semiconductor device, according to a still further embodiment (sixth embodiment) of the present invention. FIG. 20 is a flowchart showing the method of manufacturing the semiconductor device, FIG. 21 is a cross-sectional view showing the state in which a metal layer formed on the back of a wafer is cut off in dicing areas to provide chip separation, FIG. 22 is a cross-sectional view illustrating the state in which a support tape is applied onto the separated semiconductor chip group, FIG. 23 is a cross-sectional view depicting the state in which a support substrate (hole-free support substrate) is separated from the semiconductor chip group, and FIG. 24 is a cross-sectional view showing the semiconductor chip group applied to the support tape, respectively. [0126] [0127] As shown in the flowchart of FIG. 20, the method of manufacturing the semiconductor device, according to the present embodiment follows process steps similar to the second embodiment as in the case of the bonding of a semiconductor wafer to a support substrate (hole-free support substrate) (S[0127] 202) after work is started (S201), the thinning of the semiconductor wafer (S203), the definition of holes in a via/scribing area (S204), and the formation of an electrode layer (S205). However, the subsequent process steps are different from the second embodiment as in the case of the conversion into semiconductor chip form by chip separation (S206), support-tape bonding (S207) and the removal of a support substrate by solvent (S208). Afterwards, the work is finished (S209). In the sixth embodiment, the hole-free support substrate is used as the support substrate. [0128] Points different from the method of manufacturing the semiconductor device, according to the second embodiment will be explained below with reference to FIGS. [0128] 21 through 24. In the present embodiment, a main surface of a semiconductor wafer 30 is bonded to a first surface of a hole-free support substrate 34 by an adhesive layer 36 so as to be opposed to each other as shown in FIG. 21. The adhesive layer 36 is an adhesive layer melted by solvent and makes use of wax in a manner similar to the second embodiment. [0129] The semiconductor wafer [0129] 30 bonded to the hole-free support substrate 34 follows process steps similar to the second embodiment as in the case of the wafer thinning (S203), the definition of the holes in the via/scribing area (S204) and the formation of the electrode layer (S205). [0130] Next, as shown in FIG. 21, an electrode layer [0130] 12 provided on the back of the semiconductor wafer is cut by dicing along the centers of separation trenches (first trenches) 38 to form semiconductor chips 20 (S206). [0131] Next, as shown in FIG. 22, a support tape [0131] 65 is applied to the back of a semiconductor chip group attached to an adhesive layer 33 (S207). The support tape 65 is a resin tape having adhesion similar to that employed in the second embodiment. [0132] Next, as shown in FIG. 23, the adhesive layer [0132] 36 for bonding the semiconductor chips 20 and the hole-free support substrate 34 to each other is melted by solvent to separate the semiconductor chips 20 from the hole-free support substrate 34 (S208). For example, a perforated support substrate 32 with the semiconductor chips 20 attached thereto is immersed in IPA (Isopropyl alcohol) to solve the adhesive layer 36. After IPS has reached the surface of the adhesive layer 36 through the separation trenches 38, it promotes melting toward the center of each semiconductor chip while the adhesive layer 36 lying on the periphery of each semiconductor chip 20 is being melted. At this time, ultrasonic vibrations are applied to accelerate the solving of the adhesive layer. [0133] Since the semiconductor chip [0133] 20 is extremely small in size as compared with the semiconductor wafer, the time required for IPA to reach from the periphery of the semiconductor chip 20 to its center is drastically shortened as compared with the semiconductor wafer. As a result, the separation of the semiconductor chip group is greatly cut down as compared with a semiconductor wafer on which a semiconductor chip group is formed. [0134] Since no external force is applied to each semiconductor chip [0134] 20, damage such as cracks, breaking is not developed in each semiconductor chip upon separation. [0135] FIG. 24 is a diagram showing the semiconductor chips [0135] 20 kept in a state of being applied to the support tape 65. [0136] Afterwards, the respective semiconductor chips [0136] 20 kept in the state of being attached to the support tape 65 are vacuum-absorbed and held by a normally-used vacuum absorption type pickup tool upon assembly of a semiconductor device such as a high-frequency power amplifying module. Thus, the semiconductor chips 20 are peeled off from the support tape 65 and chip-bonded to a mounted substrate. [0137] The present embodiment can also obtain an effect similar to the second embodiment. Namely, the semiconductor chips [0137] 20 can be separated from the hole-free support substrate 34 in a short time without being subjected to damage. [0138] While the invention made by the present inventors has been described above specifically based on the embodiments, the present invention is not limited to the above-described embodiments. It is needless to say that various changes can be made thereto without the scope not departing from the substance thereof. The present invention can similarly be applied even to a method of manufacturing semiconductor devices such as GaAs-MESFET, HEMT, etc. and can bring about effects similar to the embodiments. [0138] [0139] Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be explained as follows: [0139] [0140] The thinning of a semiconductor wafer and the separation thereof from a support substrate can be carried out with high yields and in a short time, and hence a reduction in manufacturing cost of a semiconductor device can be achieved. [0140] [0141] The thinning of a semiconductor wafer and the separation of each semiconductor chip from a support substrate can be carried out with high yields and in a short time, and hence a reduction in manufacturing cost of a semiconductor device can be achieved. [0141] [0142] Thinned semiconductor chips each having a PHS structure can be manufactured with high yields and in a short time, and hence a reduction in manufacturing cost of a semiconductor device can be achieved. [0142]
权利要求:
Claims (32) [1" id="US-20010005043-A1-CLM-00001] 1. A method of manufacturing a semiconductor device, comprising the steps of: a) preparing a support substrate having a first surface and a second surface opposite to the first surface and having a plurality of holes which extend from the first surface to the second surface; b) preparing a semiconductor wafer which has a main surface and a back opposite to the main surface and in which a plurality of semiconductor elements are formed; c) fixing the main surface of the semiconductor wafer to the first surface of the support substrate with an adhesive layer in an area in which the plurality of holes of the support substrate are defined; d) removing the back of the semiconductor wafer by a predetermined thickness to thereby thin the thickness of the semiconductor wafer; e) supplying solvent from the second surface of the support substrate through the plurality of holes to thereby reduce adhesive power of the adhesive layer; and f) peeling the thinned semiconductor wafer from the support substrate. [2" id="US-20010005043-A1-CLM-00002] 2. The method according to claim 1 , wherein in said step c), a hole-free support substrate is bonded to the second surface of the support substrate having the holes with an adhesive layer melted by heating so as to block the holes, and thereafter the main surface of the semiconductor wafer is fixed to the first surface of the support substrate with an adhesive layer melted by solvent, and in said step e), the adhesive layer for bonding the support substrate having the holes and the hole-free support substrate to each other is melted by heating to thereby separate the hole-free support substrate from the support substrate having the holes, and thereafter solvent is supplied from the second surface of the support substrate through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate having the holes and the semiconductor wafer to each other. [3" id="US-20010005043-A1-CLM-00003] 3. The method according to claim 1 , wherein in said step c), an adhesive layer melted by solvent is formed on the second surface of the support substrate having the holes so as to block the holes, and the main surface of the semiconductor wafer is fixed to the first surface of the support substrate, and in said step e), the adhesive layer formed on the second surface of the support substrate having the holes is melted by solvent so as to disappear, and thereafter solvent is supplied from the second surface of the support substrate through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate having the holes and the semiconductor wafer to each other. [4" id="US-20010005043-A1-CLM-00004] 4. The method according to claim 1 , further including, after said step d), a step of selectively etching the semiconductor wafer from the back thereof to divide the semiconductor wafer every semiconductor chip forming areas including the semiconductor elements to thereby form a plurality of semiconductor chips. [5" id="US-20010005043-A1-CLM-00005] 5. The method according to claim 4 , further including the steps of: preparing a semiconductor wafer having a main surface and a back opposite to the main surface, having a plurality of semiconductor elements formed thereon, and having, on the main surface, an etching stopper layer comprised of a conductor electrically connected to a predetermined electrode constituting said each semiconductor element, and a metal layer provided so as to overlap with a corresponding scribing area around said each semiconductor chip forming area; defining first trenches each of which reaches the metal layer in the scribing area and second trenches each of which reaches the etching stopper layer in said step of selectively etching the semiconductor wafer from the back thereof; forming an electrode layer over the whole range of the back of the semiconductor wafer; and supplying solvent from the second surface of the support substrate through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate and the semiconductor wafer to each other. [6" id="US-20010005043-A1-CLM-00006] 6. The method according to claim 1 , wherein the removal of said step d) includes a step of grinding the back of the semiconductor wafer, and a step of further wet-etching the surface thereof exposed by said grinding. [7" id="US-20010005043-A1-CLM-00007] 7. The method according to claim 1 , wherein the holes defined in the support substrate gradually increase in diameter from the first surface to the second surface. [8" id="US-20010005043-A1-CLM-00008] 8. The method according to claim 1 , wherein the respective holes defined in the support substrate are in communication states through trenches. [9" id="US-20010005043-A1-CLM-00009] 9. The method according to claim 1 , wherein in said step e), solvent is supplied from the second surface of the support substrate through the plurality of holes while a ultrasonic wave is being applied, to thereby reduce adhesive power of the adhesive layer for bonding the support substrate and the semiconductor wafer to each other. [10" id="US-20010005043-A1-CLM-00010] 10. The method according to claim 1 , wherein the support substrate is formed of glass. [11" id="US-20010005043-A1-CLM-00011] 11. A method of manufacturing a semiconductor device, comprising the steps of: a) preparing a support substrate having a first surface and a second surface opposite to the first surface; b) preparing a semiconductor wafer having a main surface and a back opposite to the main surface, having a plurality of semiconductor elements formed thereon, and having, on the main surface, an etching stopper layer comprised of a conductor electrically connected to a predetermined electrode constituting said each semiconductor element, and a metal layer provided so as to overlap with a corresponding scribing area around each of semiconductor chip forming areas including the semiconductor elements; c) fixing the main surface of the semiconductor wafer to the first surface of the support substrate with an adhesive layer; d) removing the back of the semiconductor wafer by a predetermined thickness to thereby thin the thickness of the semiconductor wafer; e) forming an etching mask for exposing parts of an area corresponding to the scribing area and said plurality of semiconductor chip forming areas on the back of the thinned semiconductor wafer; and f) selectively etching the semiconductor wafer in an area corresponding to the scribing area exposed from the etching mask and an area corresponding to part of said plurality of semiconductor chip forming areas to thereby form first trenches reaching the metal layer in the area corresponding to the scribing area and second trenches in each individuals of the plurality of semiconductor chip forming areas. [12" id="US-20010005043-A1-CLM-00012] 12. The method according to claim 11 , wherein in said step a), a support substrate having a plurality of holes extending from the first surface to the second surface of the support substrate is prepared as a support substrate, and in said step c), the main surface of the semiconductor wafer is fixed to the first surface of the support substrate with an adhesive layer in an area in which the plurality of holes are defined in the support substrate. [13" id="US-20010005043-A1-CLM-00013] 13. The method according to claim 12 , wherein a hole-free support substrate is bonded to a second surface of the support substrate having the holes with an adhesive layer melted by heating so as to block the holes. [14" id="US-20010005043-A1-CLM-00014] 14. The method according to claim 12 , wherein an adhesive layer melted by solvent is formed on the second surface of the support substrate having the holes so as to block the holes. [15" id="US-20010005043-A1-CLM-00015] 15. The method according to claim 11 , wherein the removal of said step d) includes a step of grinding the back of the semiconductor wafer, and a step of further wet-etching the surface thereof exposed by said grinding. [16" id="US-20010005043-A1-CLM-00016] 16. A method of manufacturing a semiconductor device, comprising the steps of: a) preparing a support substrate having a first surface and a second surface opposite to the first surface and having a plurality of holes extending from the first surface to the second surface; b) preparing a semiconductor wafer having a main surface and a back opposite to the main surface, having a plurality of semiconductor elements formed thereon, and having, on the main surface, an etching stopper layer comprised of a conductor electrically connected to a predetermined electrode constituting said each semiconductor element, and a metal layer provided so as to overlap with a corresponding scribing area around each of the semiconductor elements; c) fixing the main surface of the semiconductor wafer to the first surface of the support substrate with an adhesive layer in an area in which the plurality of holes are defined; d) removing the back of the semiconductor wafer by a predetermined thickness to thereby thin the thickness of the semiconductor wafer; e) selectively etching the back of the semiconductor wafer to thereby define first trenches each of which reaches the metal layer in the scribing area and second trenches each of which reaches the etching stopper layer; f) forming an electrode layer over the whole range of the back of the semiconductor wafer; g) supplying solvent from the second surface of the support substrate through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate and the semiconductor wafer to each other; h) peeling a semiconductor chip group arranged in plate form, which is connected by the electrode layer, from the support substrate; i) bonding a support tape to the electrode layer forming surface side of the semiconductor chip group arranged in plate form; and j) cutting the electrode layer for connecting respective semiconductor chips of the semiconductor chip group arranged in plate form to thereby separate each individual semiconductor chips. [17" id="US-20010005043-A1-CLM-00017] 17. The method according to claim 16 , further including a step of bonding an insulating support tape to one exposed surface of the semiconductor chip group arranged in plate form in said step i) and thereafter inspecting electrical characteristics of the respective semiconductor chips. [18" id="US-20010005043-A1-CLM-00018] 18. The method according to claim 16 , wherein in said step c), a hole-free support substrate is bonded to the second surface of the support substrate having the holes with an adhesive layer melted by heating so as to block the holes and thereafter the main surface of the semiconductor wafer is fixed to the first surface of the support substrate with an adhesive layer melted by solvent, and in said step g), the adhesive layer for bonding the support substrate having the holes and the hole-free support substrate to each other is melted by heating to thereby separate the hole-free support substrate from the support substrate having the holes, and thereafter solvent is supplied from the second surface of the support substrate through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate having the holes and the semiconductor wafer to each other. [19" id="US-20010005043-A1-CLM-00019] 19. The method according to claim 16 , wherein in said step c), an adhesive layer melted by solvent is formed on the second surface of the support substrate having the holes so as to block the holes, and the main surface of the semiconductor wafer is fixed to the first surface of the support substrate with an adhesive layer, and in said step g), the adhesive layer formed on the second surface of the support substrate having holes is melted by solvent so as to disappear, and thereafter solvent is supplied from the second surface of the support substrate through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate having the holes and the semiconductor wafer to each other. [20" id="US-20010005043-A1-CLM-00020] 20. The method according to claim 16 , wherein the removal of said step d) includes a step of grinding the back of the semiconductor wafer, and a step of further wet-etching the surface thereof exposed by said grinding. [21" id="US-20010005043-A1-CLM-00021] 21. The method according to claim 16 , wherein said support substrate is formed of glass. [22" id="US-20010005043-A1-CLM-00022] 22. The method according to claim 16 , wherein said support tape is an insulating ultraviolet-ray cured adhesion type resin tape. [23" id="US-20010005043-A1-CLM-00023] 23. A method of manufacturing a semiconductor device, comprising the steps of: a) preparing a support substrate having a first surface and a second surface opposite to the first surface; b) preparing a semiconductor wafer having a main surface and a back opposite to the main surface, having a plurality of semiconductor elements formed thereon, and having, on the main surface, an etching stopper layer comprised of a conductor electrically connected to a predetermined electrode constituting said each semiconductor element, and a metal layer provided so as to overlap with a corresponding scribing area around semiconductor elements; c) fixing the main surface of the semiconductor wafer to the first surface of the support substrate with an adhesive layer; d) removing the back of the semiconductor wafer by a predetermined thickness to thereby thin the thickness of the semiconductor wafer; e) selectively etching the back of the semiconductor wafer to thereby define first trenches each of which reaches the metal layer in the scribing area and second trenches each of which reaches the etching stopper layer; f) forming an electrode layer over the whole range of the back of the semiconductor wafer; g) cutting the metal layer in the scribing area to thereby set the respective semiconductor elements as semiconductor chips independent of one another on the support substrate; h) applying a support tape to the electrode layer forming surface side of said each semiconductor chip; and i) melting an adhesive layer for bonding the support substrate and the respective semiconductor chips to one another by solvent to separate the support substrate from the semiconductor chips. [24" id="US-20010005043-A1-CLM-00024] 24. The method according to claim 23 , wherein the removal of said step d) includes a step of grinding the back of the semiconductor wafer, and a step of further wet-etching the surface thereof exposed by said grinding. [25" id="US-20010005043-A1-CLM-00025] 25. The method according to claim 23 , wherein said support substrate is formed of glass. [26" id="US-20010005043-A1-CLM-00026] 26. The method according to claim 23 , wherein said support tape is an insulating ultraviolet-ray cured adhesion type resin tape. [27" id="US-20010005043-A1-CLM-00027] 27. A semiconductor device comprising: a mounted board; and a semiconductor chip fixed to said mounted board with an adhesive layer interposed therebetween, wherein an electrode layer is provided on a mounting surface of the semiconductor chip, burrs protruding toward the mounted-board surface side exist in edges of the electrode layer, and the thickness of the adhesive layer is thicker than the protrusion length of said each burr. [28" id="US-20010005043-A1-CLM-00028] 28. The semiconductor device according to claim 27 , wherein the electrode layer is provided on the back of said each semiconductor chip and electrically connected to a predetermined electrode provided on the main surface of said each semiconductor chip through a conductor charged into each via hole provided so as to extend from the main surface of said each semiconductor chip to the back thereof. [29" id="US-20010005043-A1-CLM-00029] 29. The semiconductor device according to claim 27 , wherein the electrode layer on the back of said each semiconductor chip is gold. [30" id="US-20010005043-A1-CLM-00030] 30. The semiconductor device according to claim 29 , wherein the adhesive layer for fixing the semiconductor chip to the mounted board is silver paste. [31" id="US-20010005043-A1-CLM-00031] 31. The semiconductor device according to claim 27 , wherein hollows are provided in a main surface of the mounted board, said semiconductor chips are respectively provided in the hollows, and the respective electrodes provided on the main surfaces of said semiconductor chips and wirings provided on the main surface of the mounted board are connected to one another by conductive wires. [32" id="US-20010005043-A1-CLM-00032] 32. The semiconductor device according to claim 27 , wherein said semiconductor chip comprises GaAs.
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引用文献:
公开号 | 申请日 | 公开日 | 申请人 | 专利标题 US20020171138A1|2001-05-21|2002-11-21|Yasuo Osone|Multilayer wiring board and semiconductor device| US20030032294A1|2001-08-13|2003-02-13|Pascal Gardes|Method for handling a thin silicon wafer| EP1376678A2|2002-06-18|2004-01-02|Sanyo Electric Co., Ltd.|Manufacturing method of semiconductor device| DE10238444A1|2002-08-22|2004-03-04|United Monolithic Semiconductors Gmbh|Production of monolithic integrated semiconductor circuit comprises fixing wafer to rigid substrate after preparing component structures with front side surfaces, and further processing| EP1453090A2|2003-02-25|2004-09-01|Sanyo Electric Co., Ltd.|Manufacturing method of semiconductor device| WO2004090975A1|2003-04-08|2004-10-21|Koninklijke Philips Electronics N.V.|Method of manufacturing semiconductor devices| US20040235270A1|2002-04-23|2004-11-25|Sanyo Electric Co., Ltd.|Method of manufacturing semiconductor device| EP1484795A1|2003-06-04|2004-12-08|Northrop Grumman Corporation|Method for manufacturing a chip scale package at wafer level| US20050130392A1|2003-12-11|2005-06-16|Advanced Semiconductor Engineering, Inc.|Method of dicing a wafer| US20050176235A1|2002-06-18|2005-08-11|Sanyo Electric Co., Ltd.|Manufacturing method of semiconductor device| WO2005093790A2|2004-03-24|2005-10-06|E2V TechnologiesLimited|Method of, and apparatus for manufacturing semiconductor elements| US20060205161A1|2005-01-31|2006-09-14|Interuniversitair Microelektronica Centrum |Method for producing a semiconductor device and resulting device| US20060207967A1|2003-07-03|2006-09-21|Bocko Peter L|Porous processing carrier for flexible substrates| US20060250559A1|2003-07-03|2006-11-09|Bocko Peter L|Glass product for use in ultra-thin glass display applications| US20070026639A1|2002-10-30|2007-02-01|Sanyo Electric Co., Ltd.|Manufacturing method of semiconductor device| WO2007050471A2|2005-10-25|2007-05-03|Freescale Semiconductor Inc.|Method for forming solder contacts on mounted substrates| US20070166957A1|2005-12-28|2007-07-19|Sanyo Electric Co., Ltd|Method of manufacturing semiconductor device| US20070293033A1|2006-06-14|2007-12-20|Hill Darrell G|Microelectronic assembly with back side metallization and method for forming the same| US20080087634A1|2006-10-13|2008-04-17|Eudyna Devices|Manufacturing method of semiconductor device| US20090215226A1|2004-08-20|2009-08-27|Koninklijke Philips Electronics N.V.|Method of Detaching a Thin Semiconductor Circuit From Its Base| US20090325467A1|2006-07-14|2009-12-31|Tokyo Ohka Kogyo Co., Ltd.|Method of Thinning Wafer and Support plate| US20100068453A1|2008-09-18|2010-03-18|Hirofumi Imai|Method for producing processed glass substrate| US20100127306A1|2004-04-16|2010-05-27|Renesas Technology Corp.|Semiconductor device and manufacturing method of the same| US20100159191A1|2008-12-19|2010-06-24|Hirofumi Imai|Processed substrate and method for manufacturing same| EP2238614A2|2008-01-14|2010-10-13|The Regents of the University of California|Vertical outgassing channels| US7919875B2|2003-08-06|2011-04-05|Sanyo Electric Co., Ltd.|Semiconductor device with recess portion over pad electrode| US20110272795A1|2010-05-06|2011-11-10|MOS Art Pack Corporation|Semiconductor device packaging structure and packaging method| US20110294237A1|2010-05-27|2011-12-01|MOS Art Pack Corporation|Packaging method of semiconductor device| WO2012097830A1|2011-01-17|2012-07-26|Ev Group E. Thallner Gmbh|Method for separating a product substrate from a carrier substrate| US8302651B2|2010-04-27|2012-11-06|Tokyo Ohka Kogyo Co., Ltd.|Stripping device and stripping method| FR2980917A1|2011-09-30|2013-04-05|St Microelectronics Crolles 2|METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTIVE THROUGH BOND| CN103208442A|2012-03-15|2013-07-17|江苏汉莱科技有限公司|Immersed type permeating lower piece| CN103325719A|2012-03-22|2013-09-25|株式会社东芝|Supporting substrate, method for fabricating semiconductor device, and method for inspecting semiconductor device| JP2013201251A|2012-03-23|2013-10-03|Toshiba Corp|Substrate separation method and substrate separation apparatus| US8563405B2|2010-05-06|2013-10-22|Ineffable Cellular Limited Liability Company|Method for manufacturing semiconductor device| CN103682176A|2013-12-06|2014-03-26|京东方科技集团股份有限公司|Manufacturing method for rigid substrate and flexible display device and rigid substrate| CN103681398A|2012-09-13|2014-03-26|株式会社东芝|Manufacturing method of semiconductor device, semiconductor device, supporting substrate, and semiconductor manufacturing apparatus| US20140255638A1|2011-10-31|2014-09-11|Tokyo Ohka Kogyo Co., Ltd.|Adhesive composition for bonding a wafer and supporting body for said wafer, adhesive film, and laminate| US20150021666A1|2013-07-17|2015-01-22|Taiwan Semiconductor Manufacturing Company., Ltd.|Transistor having partially or wholly replaced substrate and method of making the same| TWI509739B|2010-05-06|2015-11-21|Xenogenic Dev Ltd Liability Company|Method for manufacturing semiconductor device| US20160079119A1|2014-09-17|2016-03-17|Kabushiki Kaisha Toshiba|Manufacturing method of semiconductor device| WO2016142240A1|2015-03-11|2016-09-15|Nv Bekaert Sa|Carrier for temporary bonded wafers| WO2016142238A1|2015-03-11|2016-09-15|Nv Bekaert Sa|Carrier for temporary bonded wafers| WO2016142237A1|2015-03-11|2016-09-15|Nv Bekaert Sa|Carrier for temporary bonded wafers| WO2016142239A1|2015-03-11|2016-09-15|Nv Bekaert Sa|Carrier for temporary bonded wafers| US20170162460A1|2015-12-03|2017-06-08|Infineon Technologies Ag|Semiconductor substrate-on-semiconductor substrate package and method of manufacturing the same| US10332776B2|2016-09-08|2019-06-25|Boe Technology Group Co., Ltd.|Bearing substrate, fabrication method for flexible display|US3559855A|1969-02-19|1971-02-02|Gen Electric|Shimless scribing| JPH05335292A|1992-05-28|1993-12-17|Nec Corp|Fabrication of semiconductor device| JPH0737768A|1992-11-26|1995-02-07|Sumitomo Electric Ind Ltd|Reinforcing method for semiconductor wafer and reinforced semiconductor wafer| JP3156896B2|1994-01-28|2001-04-16|富士通株式会社|Semiconductor device manufacturing method and semiconductor device manufactured by such manufacturing method| EP0721661B1|1994-07-26|2002-10-09|Koninklijke Philips Electronics N.V.|Method of manufacturing a semiconductor device for surface mounting, and semiconductor device for surface mounting| US5910687A|1997-01-24|1999-06-08|Chipscale, Inc.|Wafer fabrication of die-bottom contacts for electronic devices| JPH10294246A|1997-04-18|1998-11-04|Sumitomo Electric Ind Ltd|Method for thinning of semiconductor substrate| US6013534A|1997-07-25|2000-01-11|The United States Of America As Represented By The National Security Agency|Method of thinning integrated circuits received in die form|US6425971B1|2000-05-10|2002-07-30|Silverbrook Research Pty Ltd|Method of fabricating devices incorporating microelectromechanical systems using UV curable tapes| US6982184B2|2001-05-02|2006-01-03|Silverbrook Research Pty Ltd|Method of fabricating MEMS devices on a silicon wafer| JP2002237515A|2001-02-07|2002-08-23|Mitsubishi Gas Chem Co Inc|Peeling device and peeling method for making semiconductor substrate into thin sheet| US7148125B2|2001-12-12|2006-12-12|Denso Corporation|Method for manufacturing semiconductor power device| CN1703773B|2002-06-03|2011-11-16|3M创新有限公司|Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body| US7535100B2|2002-07-12|2009-05-19|The United States Of America As Represented By The Secretary Of The Navy|Wafer bonding of thinned electronic materials and circuits to high performance substrates| US6780733B2|2002-09-06|2004-08-24|Motorola, Inc.|Thinned semiconductor wafer and die and corresponding method| JP2004153193A|2002-11-01|2004-05-27|Disco Abrasive Syst Ltd|Processing method for semiconductor wafer| JP2004312666A|2003-03-25|2004-11-04|Fuji Photo Film Co Ltd|Solid-state imaging device and method for manufacturing the same| JP4364535B2|2003-03-27|2009-11-18|シャープ株式会社|Manufacturing method of semiconductor device| US10266398B1|2007-07-25|2019-04-23|Hrl Laboratories, Llc|ALD metal coatings for high Q MEMS structures| JP3690407B2|2003-07-31|2005-08-31|セイコーエプソン株式会社|Manufacturing method of semiconductor device| JP2006135272A|2003-12-01|2006-05-25|Tokyo Ohka Kogyo Co Ltd|Substrate support plate and peeling method of support plate| JP2005340655A|2004-05-28|2005-12-08|Shinko Electric Ind Co Ltd|Method for manufacturing semiconductor device, and structure for supporting semiconductor substrate| US7692757B2|2004-07-30|2010-04-06|Intel Corporation|Wafer scale fabrication of liquid crystal on silicon light modulation devices| US7193295B2|2004-08-20|2007-03-20|Semitool, Inc.|Process and apparatus for thinning a semiconductor workpiece| US7288489B2|2004-08-20|2007-10-30|Semitool, Inc.|Process for thinning a semiconductor workpiece| US20060046499A1|2004-08-20|2006-03-02|Dolechek Kert L|Apparatus for use in thinning a semiconductor workpiece| US7354649B2|2004-08-20|2008-04-08|Semitool, Inc.|Semiconductor workpiece| US20060040111A1|2004-08-20|2006-02-23|Dolechek Kert L|Process chamber and system for thinning a semiconductor workpiece| US7268012B2|2004-08-31|2007-09-11|Micron Technology, Inc.|Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby| US7332414B2|2005-06-22|2008-02-19|Freescale Semiconductor, Inc.|Chemical die singulation technique| JP4810904B2|2005-07-20|2011-11-09|ソニー株式会社|High frequency device having high frequency switch circuit| JP4721828B2|2005-08-31|2011-07-13|東京応化工業株式会社|Support plate peeling method| JP2007073798A|2005-09-08|2007-03-22|Tokyo Ohka Kogyo Co Ltd|Method of thinning substrate and method of manufacturing circuit element| JP3859682B1|2005-09-08|2006-12-20|東京応化工業株式会社|Substrate thinning method and circuit element manufacturing method| JP5318324B2|2005-12-06|2013-10-16|東京応化工業株式会社|Lamination method of support plate| US20070155131A1|2005-12-21|2007-07-05|Intel Corporation|Method of singulating a microelectronic wafer| JP4619308B2|2006-03-07|2011-01-26|三洋電機株式会社|Semiconductor device manufacturing method and supporting tape| US7474005B2|2006-05-31|2009-01-06|Alcatel-Lucent Usa Inc.|Microelectronic element chips| JP2007073929A|2006-06-21|2007-03-22|Tokyo Ohka Kogyo Co Ltd|Method of thinning substrate and method of manufacturing circuit element| TWI307915B|2006-06-26|2009-03-21|Univ Nat Cheng Kung|Method for manufacturing heat sink of semiconductor device| JP2008041985A|2006-08-08|2008-02-21|Tokyo Ohka Kogyo Co Ltd|Support plate| US7555824B2|2006-08-09|2009-07-07|Hrl Laboratories, Llc|Method for large scale integration of quartz-based devices| US7851333B2|2007-03-15|2010-12-14|Infineon Technologies Ag|Apparatus comprising a device and method for producing it| CN101779268B|2007-06-25|2013-11-06|布鲁尔科技公司|High-temperature spin-on temporary bonding compositions| US8766745B1|2007-07-25|2014-07-01|Hrl Laboratories, Llc|Quartz-based disk resonator gyro with ultra-thin conductive outer electrodes and method of making same| JP2009177033A|2008-01-25|2009-08-06|Furukawa Electric Co Ltd:The|Circuit element forming method| US8151640B1|2008-02-05|2012-04-10|Hrl Laboratories, Llc|MEMS on-chip inertial navigation system with error correction| US7802356B1|2008-02-21|2010-09-28|Hrl Laboratories, Llc|Method of fabricating an ultra thin quartz resonator component| JP4965485B2|2008-02-29|2012-07-04|東京応化工業株式会社|Treatment liquid permeation unit and treatment apparatus| US7960247B2|2008-04-04|2011-06-14|The Charles Stark Draper Laboratory, Inc.|Die thinning processes and structures| US8273603B2|2008-04-04|2012-09-25|The Charles Stark Draper Laboratory, Inc.|Interposers, electronic modules, and methods for forming the same| US8017451B2|2008-04-04|2011-09-13|The Charles Stark Draper Laboratory, Inc.|Electronic modules and methods for forming the same| CN101728226B|2008-10-23|2011-08-17|亚泰半导体设备股份有限公司|Segregation apparatus and segregation method| US7994877B1|2008-11-10|2011-08-09|Hrl Laboratories, Llc|MEMS-based quartz hybrid filters and a method of making the same| US8647924B2|2009-04-13|2014-02-11|United Test And Assembly Center Ltd.|Semiconductor package and method of packaging semiconductor devices| JP2010267653A|2009-05-12|2010-11-25|Disco Abrasive Syst Ltd|Method of processing wafer| JP5356914B2|2009-05-28|2013-12-04|株式会社ディスコ|Wafer processing method| US8176607B1|2009-10-08|2012-05-15|Hrl Laboratories, Llc|Method of fabricating quartz resonators| JP5523922B2|2010-04-27|2014-06-18|東京応化工業株式会社|Peeling method and peeling device| JP5595790B2|2010-05-27|2014-09-24|株式会社ディスコ|Wafer processing method| US8912711B1|2010-06-22|2014-12-16|Hrl Laboratories, Llc|Thermal stress resistant resonator, and a method for fabricating same| JP5934621B2|2012-09-19|2016-06-15|スタンレー電気株式会社|Manufacturing method of optical deflector| US9250074B1|2013-04-12|2016-02-02|Hrl Laboratories, Llc|Resonator assembly comprising a silicon resonator and a quartz resonator| US9599470B1|2013-09-11|2017-03-21|Hrl Laboratories, Llc|Dielectric high Q MEMS shell gyroscope structure| US9693469B2|2013-12-19|2017-06-27|The Charles Stark Draper Laboratory, Inc.|Electronic module subassemblies| US9977097B1|2014-02-21|2018-05-22|Hrl Laboratories, Llc|Micro-scale piezoelectric resonating magnetometer| US10031191B1|2015-01-16|2018-07-24|Hrl Laboratories, Llc|Piezoelectric magnetometer capable of sensing a magnetic field in multiple vectors| US9991863B1|2014-04-08|2018-06-05|Hrl Laboratories, Llc|Rounded and curved integrated tethers for quartz resonators| US10147630B2|2014-06-11|2018-12-04|John Cleaon Moore|Sectional porous carrier forming a temporary impervious support| US10308505B1|2014-08-11|2019-06-04|Hrl Laboratories, Llc|Method and apparatus for the monolithic encapsulation of a micro-scale inertial navigation sensor suite| JP2016146429A|2015-02-09|2016-08-12|トヨタ自動車株式会社|Semiconductor device manufacturing method| US10110198B1|2015-12-17|2018-10-23|Hrl Laboratories, Llc|Integrated quartz MEMS tuning fork resonator/oscillator| US10175307B1|2016-01-15|2019-01-08|Hrl Laboratories, Llc|FM demodulation system for quartz MEMS magnetometer| CN106711049B|2016-12-22|2020-09-29|武汉华星光电技术有限公司|Porous substrate and manufacturing method thereof, and manufacturing method of thin film transistor| US10319830B2|2017-01-24|2019-06-11|Qualcomm Incorporated|Heterojunction bipolar transistor power amplifier with backside thermal heatsink|
法律状态:
2002-08-15| AS| Assignment|Owner name: HITACHI, LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKANISHI, ASAKI;SORIMACHI, SUSUMU;YAMASHITA, KIICHI;AND OTHERS;REEL/FRAME:013196/0575;SIGNING DATES FROM 20001120 TO 20001124 Owner name: HITACHI TOHBU SEMICONDUCTOR, LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKANISHI, ASAKI;SORIMACHI, SUSUMU;YAMASHITA, KIICHI;AND OTHERS;REEL/FRAME:013196/0575;SIGNING DATES FROM 20001120 TO 20001124 | 2006-06-01| FPAY| Fee payment|Year of fee payment: 4 | 2010-07-19| REMI| Maintenance fee reminder mailed| 2010-12-10| LAPS| Lapse for failure to pay maintenance fees| 2011-01-10| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 | 2011-02-01| FP| Expired due to failure to pay maintenance fee|Effective date: 20101210 |
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