• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a dielectric filling for electrical wiring planes of an integrated circuit. The electrical wiring of the integrated circuit comprises a base body on which track and passivation planes can already be disposed; a conductive layer which is disposed on the base body and is patterned in such a manner that it exhibits a first conductor track, a second conductor track and a trench between the first conductor track and the second conductor track; at least one dielectric layer is disposed on the conductive layer and at least partially fills the trench, the preferred material of the dielectric layer being the polymer material polybenzoxazole.
    公开号:US20010004539A1
    申请号:US09/741,308
    申请日:2000-12-18
    公开日:2001-06-21
    发明作者:Markus Kirchhoff；Michael Rogalli；Stephan Wege
    申请人:Infineon Technologies AG；
    IPC主号:H01L23-5329
    专利说明:
    [0001] The present invention relates to the dielectric filling of electrical wiring planes in an integrated circuit. [0001]
    [0002] Integrated circuits consist of a multiplicity of individual patterns which are in most cases arranged in layers on a substrate. Electronic components such as resistors, capacitors, diodes, transistors etc. are usually manufactured in one substrate. The individual components are then electrically interconnected in one or more wiring planes (so-called metalization planes) located thereabove. [0002]
    [0003] A process which is used for the electrical wiring provides for the deposition of a conductive layer on a substrate. The conductive layer is then photolithographically patterned so that conductor tracks with an intermediate trench are produced. The trench is usually filled with a dielectric of silicon oxide. For this purpose, for example, doped silicon oxides such as borosilicate glass, phosphorosilicate glass or arsenosilicate glass or mixtures of these materials are used. The doped silicate glasses have the property of becoming fluid at high temperatures. This makes it possible to fill the trench with an insulating dielectric. [0003]
    [0004] However, the doped silicate glasses have the disadvantage that they exhibit a high dielectric constant of approx. 4. The high dielectric constant has a disadvantageous effect on the speed of signal propagation on the electrical connecting lines which have a high capacitance due to their high dielectric constant. The large capacitance leads to long RC times. The problem of long RC times will become worse in future since, due to the general trend toward ever smaller components, the distances between the individual conductor tracks are continuing to decrease which leads to larger capacitances. [0004]
    [0005] Another problem which accompanies the continuous reduction in size of the electrical circuits is the limited flowability of the doped silicate glasses. As the trenches between the conductor tracks continue to become smaller, this results in voids which are no longer penetrated by the doped silicate glass. The voids have the objectionable characteristic of collecting moisture. During an elevated temperature exposure which the integrated circuit experiences, e.g. when it is soldered on, the integrated circuit explodes due to the vaporization of the collected moisture and, as a result, becomes unusable. [0005]
    [0006] A further disadvantage is the high reflectivity of the doped silicate glass layers which leads to wrong exposures and faulty processing during the subsequent lithographic steps. [0006] SUMMARY OF THE INVENTION
    [0007] It is accordingly an object of the invention to provide a method of producing dielectric filling of electrical wiring planes and dielectric filled electrical wiring planes, and a dielectric layer for an electrical wiring plane of an integrated circuit, that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, and exhibits good filling and reflowing characteristics, a low dielectric constant and reflection-suppressing characteristics in photolithographic steps. [0007]
    [0008] With the foregoing and other objects in view there is provided, in accordance with the invention, an electrically wired integrated circuit, comprising: [0008]
    [0009] a base body; [0009]
    [0010] a conductive layer disposed on the base body and patterned such that it exhibits a first conductor track, a second conductor track, and a trench between the first conductor track and the second conductor track, and [0010]
    [0011] at least one dielectric layer disposed on the conductive layer and at least partially filling the trench, wherein at least one dielectric layer comprises one or more of the polymer materials polybenzoxazole, polynorbornene, polytetrafluoroethylene and their derivatives. [0011]
    [0012] In addition to or alternatively to polybenzoxazole, other materials are also suitable, which can also be applied to a wafer by spin-on methods. These include inorganic materials such as hydrogen silsesquioxane and organic materials such as polybenzoxazole, polyimide, perylene polymers, polynorbornene and polytetrafluoroethylene and their derivatives and especially their fluorinated derivatives. [0012]
    [0013] With the foregoing and other objects in view there is also provided, in accordance with the invention, a process for producing electrical wiring of an integrated circuit comprising the steps of [0013]
    [0014] forming a conductive layer on a base body; [0014]
    [0015] patterning the conductive layer so that a first conductor track, a second conductor track and a trench between the first conductor track and the second conductor track are formed; and [0015]
    [0016] spin-coating at least one dielectric layer of a polymer onto the conductive layer so that the trench is at least partially filled. The polymer comprises polybenzoxazole and/or polynorbornene and/or one of their derivatives. [0016]
    [0017] The preferred polymer material polybenzoxazole (PBO) is distinguished by the fact that it can be applied by spin coating and thus fills the smallest gaps without voids. This prevents cavities which can collect moisture in a HAST (humidity acceleration stress test) test and explode during subsequent elevated temperature steps (popcorn effect). Apart from these excellent planarization characteristics, polybenzoxazole, after having been cured, is distinguished by high temperature stability up to above 400° Celsius and low moisture absorption. Moreover, the dielectric constant of polybenzoxazole in its cured state is less than 2.9. The low dielectric constant makes possible faster signals on the integrated circuit due to the lower parasitic capacitances. Furthermore, polybenzoxazole, due to its absorption characteristics, prevents reflections during subsequent photolithographic exposure steps. As a result, a greatly improved resolution is achieved during subsequent photolithographic steps. [0017]
    [0018] In an advantageous development of the integrated circuit according to the invention, a silicon nitride layer is disposed above at least one dielectric layer. The silicon nitride layer has the advantage that it can be used as passivation layer with excellent blocking effect against water vapor, alkali ions and other substances acting corrosively. [0018]
    [0019] In a further advantageous embodiment of the invention, a silicon oxide layer is disposed between at least one dielectric layer and the silicon nitride layer. [0019]
    [0020] In a further advantageous development of the invention, a second dielectric layer of polybenzoxazole or a photosensitive polyamide is disposed above the first dielectric layer. [0020]
    [0021] Other features which are considered as characteristic for the invention are set forth in the appended claims. [0021]
    [0022] Although the invention is illustrated and described herein as embodied in a dielectric filling of electrical wiring planes, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. [0022]
    [0023] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. [0023] BRIEF DESCRIPTION OF THE DRAWINGS
    [0024] FIG. 1 is a partial sectional view of a layer structure for the electrical wiring according to the prior art; [0024]
    [0025] FIG. 2 is a similar view of a layer structure according to the invention; and [0025]
    [0026] FIG. 3 is a similar view of another layer structure according to the invention. [0026]
    [0027] In the figures, identical reference symbols designate identical elements or those having the same function. [0027] DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0028] Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is seen a prior art layer structure of an electrical wiring. On a base body [0028] 1, which can already comprise electronic components such as resistors, capacitors, diodes, transistors, passivation layers etc., a conductive layer 2 is precipitated. The conductive layer 2 is usually formed of a metal such as aluminum or copper. The conductive layer 2 is patterned in such a manner that a first conductor track 3 and a second conductor track 4 with an intermediate trench 5 are produced. After that, a doped silicate glass is usually precipitated and caused to flow by a heating step in such a manner that it fills the trench 5 and forms a silicon oxide layer 7. On the silicon oxide layer 7, a silicon nitride layer 8 is then formed which is used as passivation layer with excellent blocking effect. After that, a second dielectric layer 9 is formed on the silicon nitride layer 8. The second dielectric layer 9 is used as photosensitive layer (photoresist) and consists, for example, of a polyimide, a photosensitive polyimide, a polyimide derivative, a polybenzoxazole, a photosensitive polybenzoxazole or of a polybenzoxazole derivative.
    [0029] Referring to FIG. 2, the inventive difference with respect to FIG. 1 concerns a first dielectric layer [0029] 6 used for filling the trench 5 and for covering the conductive layer 2 and thus for covering the first conductor track 3 and the second conductor track 4. The first dielectric layer 6 is, for example, the polymer material polybenzoxazole. The inventive advantage of the first dielectric layer 6 of polybenzoxazole consists in its excellent filling characteristic, its low dielectric constant which is less than 2.9, and the reduction of reflections during subsequent lithographic steps.
    [0030] Referring to FIG. 3, the silicon nitride layer [0030] 8 is formed on the dielectric layer 6. In contrast, a silicon oxide layer 7 is first formed on the dielectric layer 6 and the silicon nitride layer 8 is only formed above that in the exemplary embodiment shown in FIG. 2.
    [0031] Further advantages are provided by the dielectric layer [0031] 6 acting as stress reduction layer with respect to the silicon nitride layer 8 which is frequently mechanically stressed, as a result of which integration problems caused by the mechanical stress of the silicon nitride layer are reduced or, respectively, eliminated. Furthermore, the thickness of the dielectric layer 6 in FIG. 3 can be made smaller than the thickness of the silicon oxide layer 7 of FIG. 1, as a result of which subsequent dry etching steps for opening the passivation layer become shorter and are thus performed more economically.
    权利要求:
    Claims (10)
    [1" id="US-20010004539-A1-CLM-00001] 1. An electrical wiring of an integrated circuit, comprising:
    a base body;
    a conductive layer disposed on said base body and patterned into a first conductor track, a second conductor track, and a trench between said first conductor track and said second conductor track; and
    a dielectric layer disposed on said conductive layer and at least partially filling said trench, said dielectric layer comprising at least one polymer material selected from the group consisting of polybenzoxazole, polynorbornene, and their derivatives.
    [2" id="US-20010004539-A1-CLM-00002] 2. The electrical wiring according to
    claim 1 , which comprises a silicon nitride layer disposed on said dielectric layer.
    [3" id="US-20010004539-A1-CLM-00003] 3. The electrical wiring according to
    claim 2 , which comprises a silicon oxide layer disposed between said dielectric layer and said silicon nitride layer.
    [4" id="US-20010004539-A1-CLM-00004] 4. The electrical wiring according to
    claim 1 , wherein said dielectric layer is a first dielectric layer, and a second dielectric layer of a same material as said first dielectric layer is disposed above said first dielectric layer.
    [5" id="US-20010004539-A1-CLM-00005] 5. The electrical wiring according to
    claim 1 , wherein a material of said first dielectric layer has a dielectric constant of less than 3.5.
    [6" id="US-20010004539-A1-CLM-00006] 6. An electrical wiring of an integrated circuit, comprising:
    a base body;
    a conductive layer disposed on said base body and patterned into a first conductor track, a second conductor track, and a trench between said first conductor track and said second conductor track; and
    a dielectric layer disposed on said conductive layer and at least partially filling said trench, said dielectric layer comprising at least one polymer material selected from the group consisting of fluorinated derivatives of polybenzoxazole, polynorbornene, polyimide, and perylene polymer.
    [7" id="US-20010004539-A1-CLM-00007] 7. A process for producing an electrical wiring of an integrated circuit, which comprises the steps of:
    forming a conductive layer on a base body;
    patterning the conductive layer to form a first conductor track, a second conductor track, and a trench between the first conductor track and the second conductor track; and
    selecting a polymer from the group consisting of polybenzoxazole, polynorbornene, and their derivatives, and spin-coating at least one dielectric layer of the polymer onto the conductive layer so that the trench is at least partially filled.
    [8" id="US-20010004539-A1-CLM-00008] 8. The process according to
    claim 7 , which comprises forming a silicon nitride layer above the dielectric layer.
    [9" id="US-20010004539-A1-CLM-00009] 9. The process according to
    claim 8 , which comprises forming a silicon oxide layer between the dielectric layer and the silicon nitride layer.
    [10" id="US-20010004539-A1-CLM-00010] 10. The process according to
    claim 7 , which comprises forming a second dielectric layer of the same material as the first above-mentioned dielectric layer above the first dielectric layer.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6509623B2|2003-01-21|Microelectronic air-gap structures and methods of forming the same
    US7094689B2|2006-08-22|Air gap interconnect structure and method thereof
    US8901733B2|2014-12-02|Reliable metal bumps on top of I/O pads after removal of test probe marks
    US7012022B2|2006-03-14|Self-patterning of photo-active dielectric materials for interconnect isolation
    KR100265771B1|2000-10-02|Method for metallization by dual damascene process using photosensitive polymer
    US7071554B2|2006-07-04|Stress mitigation layer to reduce under bump stress concentration
    US6380076B2|2002-04-30|Dielectric filling of electrical wiring planes
    KR20040010267A|2004-01-31|Semiconductor integrated circuit device having multilevel interconnection
    KR100388830B1|2003-06-25|Hybrid dielectric structure for improving the stiffness of back end of the line structures
    KR100436674B1|2004-07-02|Semiconductor device and manufacturing method thereof
    US6265307B1|2001-07-24|Fabrication method for a dual damascene structure
    US6831363B2|2004-12-14|Structure and method for reducing thermo-mechanical stress in stacked vias
    US6821896B1|2004-11-23|Method to eliminate via poison effect
    US6730571B1|2004-05-04|Method to form a cross network of air gaps within IMD layer
    US20040004054A1|2004-01-08|Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits
    KR100281031B1|2001-03-02|Integrated Circuit with Photosensitive Soft Passivation Layer
    US7648870B2|2010-01-19|Method of forming fuse region in semiconductor damascene process
    WO2007041504A1|2007-04-12|High density, high q capacitor on top of protective layer
    US6399471B1|2002-06-04|Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
    KR100358570B1|2002-10-25|A method for forming a metal line of a semiconductor device
    US7494928B2|2009-02-24|Method for patterning and etching a passivation layer
    KR100671561B1|2007-01-19|Method of forming interconnection line for semiconductor device
    CN113658930A|2021-11-16|Preparation method and application method of semiconductor structure
    KR19990046867A|1999-07-05|Metal wiring formation method of semiconductor device
    KR20010027376A|2001-04-06|Method for forming an interconnection line of a semiconductor device
    同族专利:
    公开号 | 公开日
    KR20010062477A|2001-07-07|
    US6380076B2|2002-04-30|
    EP1109220A2|2001-06-20|
    TW492110B|2002-06-21|
    JP2001230505A|2001-08-24|
    DE19961103A1|2001-07-05|
    EP1109220A3|2003-12-17|
    DE19961103C2|2002-03-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    WO2003063244A1|2002-01-25|2003-07-31|Mergeoptics Gmbh|Integrated circuit arrangement|
    US20040253837A1|2003-06-10|2004-12-16|Yu-Hao Yang|Method for forming a dielectric layer of a semiconductor|
    EP1760774A1|2004-05-21|2007-03-07|JSR Corporation|Laminated body and semiconductor device|
    US20180190603A1|2016-12-29|2018-07-05|United Microelectronics Corp.|Contact hole structure and fabricating method of contact hole and fuse hole|JPS512125A|1974-06-22|1976-01-09|Jidosha Kiki Co|DORYOKUKAJITORISOCHINO SEIGYOBENSOCHI|
    GB1590723A|1976-08-03|1981-06-10|Raychem Ltd|Hv insulation materials|
    EP0177845A1|1984-09-28|1986-04-16|Siemens Aktiengesellschaft|Integrated circuit with multilayer wiring and method for manufacturing it|
    DE3802403A1|1988-01-28|1989-08-10|Licentia Gmbh|SEMICONDUCTOR ARRANGEMENT WITH POLYIMIDE PASSIVATION|
    JP3006218B2|1991-10-08|2000-02-07|日立化成工業株式会社|Semiconductor device and composition for interlayer insulating film and / or surface protective film for semiconductor multilayer wiring|
    JPH08139194A|1994-04-28|1996-05-31|Texas Instr Inc <Ti>|Manufacture of electrical connection onto semiconductor device and semiconductor device with electrical connection manufactured by said method|
    US5512514A|1994-11-08|1996-04-30|Spider Systems, Inc.|Self-aligned via and contact interconnect manufacturing method|
    JP3789545B2|1995-10-09|2006-06-28|ソニー株式会社|Formation method of insulating film|
    TW322680B|1996-02-29|1997-12-11|Tokyo Ohka Kogyo Co Ltd||
    KR100205318B1|1996-10-11|1999-07-01|구본준|Manufacture of low dielectric isolation film of low|
    US5763016A|1996-12-19|1998-06-09|Anon, Incorporated|Method of forming patterns in organic coatings films and layers|
    US6117763A|1997-09-29|2000-09-12|Advanced Micro Devices, Inc.|Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water|
    JPH11181094A|1997-12-24|1999-07-06|Sumitomo Bakelite Co Ltd|Production of fluorine-containing polybenzoxazole and its use|
    KR100635685B1|1998-05-25|2006-10-17|가부시키가이샤 히타치세이사쿠쇼|Semiconductor equipment and fabrication method thereof|
    SG104255A1|1998-09-29|2004-06-21|Sumitomo Bakelite Co|Polybenzoxazole resin and precursor thereof|
    US6235628B1|1999-01-05|2001-05-22|Advanced Micro Devices, Inc.|Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer|
    US6187668B1|1999-07-06|2001-02-13|United Microelectronics Corp.|Method of forming self-aligned unlanded via holes|US6677209B2|2000-02-14|2004-01-13|Micron Technology, Inc.|Low dielectric constant STI with SOI devices|
    US6413827B2|2000-02-14|2002-07-02|Paul A. Farrar|Low dielectric constant shallow trench isolation|
    US6890847B1|2000-02-22|2005-05-10|Micron Technology, Inc.|Polynorbornene foam insulation for integrated circuits|
    DE10155802B4|2001-11-14|2006-03-02|Infineon Technologies Ag|Semiconductor chip with FIB protection|
    KR100598991B1|2005-06-29|2006-07-12|주식회사 하이닉스반도체|Composition for forming interlayer dielectric and forming process of interlayer dielectric using thereof|
    US7696627B2|2005-07-07|2010-04-13|Panasonic Corporation|Multilayered interconnect structure and method for fabricating the same|
    US7927948B2|2005-07-20|2011-04-19|Micron Technology, Inc.|Devices with nanocrystals and methods of formation|
    JP6248392B2|2013-01-17|2017-12-20|富士電機株式会社|Semiconductor device|
    法律状态:
    2002-03-12| AS| Assignment|Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIRCHHOFF, MARKUS;ROGALLI, MICHAEL;WEGE, STEPHAN;REEL/FRAME:012708/0719;SIGNING DATES FROM 20010105 TO 20010115 |
    2002-04-12| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2005-10-25| FPAY| Fee payment|Year of fee payment: 4 |
    2009-10-23| FPAY| Fee payment|Year of fee payment: 8 |
    2010-01-13| AS| Assignment|Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023828/0001 Effective date: 20060425 |
    2013-10-24| FPAY| Fee payment|Year of fee payment: 12 |
    2015-05-08| AS| Assignment|Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
    2015-08-19| AS| Assignment|Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036396/0646 Effective date: 20150708 |
    优先权:
    申请号 | 申请日 | 专利标题
    DE19961103.3||1999-12-17||
    DE19961103A|DE19961103C2|1999-12-17|1999-12-17|Dielectric filling of electrical wiring levels and method for producing electrical wiring|
    DE19961103||1999-12-17||
    [返回顶部]