• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    本發明揭示一種製造半導體裝置之方法，其包含提供一半導基板。該方法亦包含定義在該半導基板之至少一個區中之該半導基板之一表面處的一重摻雜區域，其中該重摻雜區域包含具有大於該半導基板之一摻雜濃度之一摻雜濃度之一重摻雜層。該方法亦包含在該半導基板上形成半導體材料之一額外層，該額外層包括一實質上未摻雜之層。該方法進一步包含對該半導基板應用一第一移除程序，以定義一未蝕刻部分及一蝕刻部分，其中該未蝕刻部分定義一鰭式結構，且該蝕刻部分通過該額外層延伸，且接著將該鰭式結構從其他結構隔離。
    公开号:TW201314750A
    申请号:TW101128322
    申请日:2012-08-06
    公开日:2013-04-01
    发明作者:Thomas Hoffmann；Scott E Thompson
    申请人:Suvolta Inc；
    IPC主号:H01L21-00
    专利说明:
    具鰭式結構之半導體裝置及其製造方法
    本揭示內容一般係關於半導體裝置，且更特定地關於包含鰭式結構之半導體裝置以及一整合方案以在與基於鰭之電晶體相同之基板上併入平面電晶體。
    本申請案主張2011年8月5日申請且題為「Multigate Transistors」之美國臨時專利申請案第61/515,452號之優先權，其之全文內容以引用之方式併入本文中。
    隨著半導體工業將目光投向22 nm技術節點且超過22 nm技術節點，一些製作者正在考慮從平面CMOS電晶體轉變為三維(3D)FinFET裝置架構。對比於一平面電晶體中位於通道上方之閘極，一FinFET之閘極環繞該通道，提供從多個側的靜電控制。相對於平面電晶體，此等FinFET給予改良之通道控制及因此減小短通道效應。由於FinFET之固有的優越靜電控制，FinFET之裝置靜電隨著裝置(鰭)之寬度積極縮放(通常對於次22 nm之節點應用係約10 nm至15 nm)而改良。此係所謂「雙閘極」場效應之一結果，且隨著鰭寬度(Wfin)減小，可藉由以小閘極長度(Lg)之顯著DIBL縮減而量化。
    為在塊體矽上特殊整合FinFET(塊體FinFET)，已研究恰好在Si鰭下方使用一「接地平面」。提供此接地平面以防止源極與汲極之間之低摻雜且不在閘極之直接控制下之任何區域中之一潛在的洩漏路徑。在習知塊體FinFET中，該接地平面經由以充分高以造成摻雜物穿隧通過基板之垂直長度且在井區中形成接地平面之一能量植入一摻雜層而形成。該接地平面形成步驟在形成隔離特徵部之後所做。然而，由於多個因素(例如，所植入之摻雜物分佈之有限梯度、WPE及來自植入至隔離氧化物層中之背向散射)，可非刻意地摻雜Si鰭。該非刻意摻雜可使電效能劣化，表現於匹配問題(由於隨機摻雜物波動)或驅動電流變動(由於來自雜質散射之遷移率損失)。
    此外，在鰭形成之後執行此接地平面植入之情況中，實際鰭高度之任何變動將轉化為摻雜物位置相對於鰭之頂部之一變化。因此，該裝置之有效(或電)鰭高度亦變動。最壞的是，可能無法適當形成接地平面。鰭高度之變動不僅係由於程序條件之變動，而且由於負載效應及其他圖案相依性。此等變動將直接衝擊與裝置有效寬度直接成比例之裝置之關鍵效益指數(閘極電容及驅動電流)。由於此等限制，製作者亦考慮利用SOI-FinFET裝置架構，其藉由僅在一絕緣體之頂部上提供Si鰭而消除對於重摻雜接地平面之需要。
    然而，SOI-FinFET裝置並非沒有問題。例如，一個顯著問題是無法提供一足夠背側基板接觸，以固定該等裝置之一本體電壓。此可引起奇怪的裝置特性，諸如電流之突然增加，或可隨時間改變臨限電壓(Vt)之一歷史效應。另一顯著問題在於相較於塊體矽，一SOI基板之成本係禁止的。
    為更完整理解實施例及其等之優點，現與隨附圖式結合而參考以下描述。
    實施例參考附圖而描述，其中相似參考數字貫穿該等圖而用於指明類似或等效元件。該等圖並非按比例繪製，且其等僅提供於繪示實施例。下文參考實例應用而描述實施例之若干態樣以用於繪示。應理解，闡明許多特定細節、關係及方法。一般技術者將容易地認識到本發明可在沒有一個或多個該等特定細節之下實踐，或用其他方法實踐。在其他例子中，熟知結構或操作並不詳細展示，以避免模糊實施例。本發明不受繪示之動作或事件之順序限制，因為一些動作可以不同順序出現，及/或與其他動作或事件併發地出現。此外，並非需要所有繪示之動作或事件以實施根據本發明之一方法。
    各種實施例提供一塊體FinFET裝置架構，其限制或消除不期望之鰭摻雜量及有效鰭高度變動兩者，以致使鰭實質上不摻雜，藉此減小發生自鰭中之隨機摻雜物波動之臨限電壓之變動程度。特定言之，各種實施例提供一整合方案，其由以下組成：在隔離及鰭形成模組之前，(1)經由植入或其他摻雜技術在一基板之一表面中形成井及重摻雜層；(2)在形成該重摻雜區域之後在該基板上生長一未摻雜之磊晶層(epi層)；及(3)圖案化該磊晶層，以定義鰭。其後，該等鰭接著用於形成FinFET裝置。
    上文描述之整合方案提供SOI-FinFET之若干優點(但是在一塊體FinFET結構中)。首先，可在一高摻雜層上形成一真正未摻雜之鰭，因為在形成該磊晶層之後未執行通道植入。結果，電特性之改良(諸如改良之匹配特性及來自較少雜質散射的更高遷移率)係可能的。
    第二，此整合方案使得塊體FinFET之匹配係數到達約1.0至1.2 mV/um，密切地匹配對於未摻雜的SOI-FinFET裝置所報告之係數。此外，電效能之整體均勻度通過從蝕刻及植入程序之變動將有效(或電)鰭高度去耦合而改良。相反，鰭高度主要取而代之由磊晶膜厚度設定，為此，可達成0.1%或更好的均勻度。例如，對於30 nm至40 nm之一矽磊晶層，該磊晶層厚度晶圓均勻度可在+/-1 nm(1均方偏差)內，其比經由蝕刻程序及植入程序之習知組合對於實體鰭高度可達成之均勻度更緊密。
    其他可能益處包含增強之臨限電壓(Vth)調諧敏感度，其藉由接地平面集中度變化，及增強之本體係數。此外，因為不需要暈植入，且井/接地井植入在STI之前執行，該整合方案亦期望減小井近接效應。
    現轉向圖1，展示根據一特定實施例之在形成閘極之前之一例示性半導體裝置10之一截面圖。半導體裝置10包含藉由平版印刷及蝕刻程序之一組合而形成於一半導基板12上之一鰭式結構14。在所繪示之實施例中，半導體裝置10包含藉助於上覆一重摻雜區域18及視需要的一井區域19之一實質上未摻雜之半導體層而形成於鰭式結構14中之一通道區域60。鄰近於鰭式結構14在任一側上的是隔離氧化物16。半導體裝置10可於較高速度及/或以減小的功率消耗操作。如本文中所使用，術語「半導基板」指其上安置一層或多層半導體材料之任何類型之基板或支撐層。此等可包含絕緣體上矽基板、塊體矽基板或磊晶矽基板，等等。
    如由圖1所繪示，鰭式結構14形成於半導基板12上。在此實施例中之基板結構12表示具有其內形成之一重摻雜層18之半導體材料之一基板。重摻雜層18表示一層重濃度摻雜之半導體材料(5×1018至1020原子/cm3)。如圖1中所展示，此層可被組態為一抗衝穿層(APT)。
    鰭式結構14表示由半導基板12之頂部上之半導體材料形成之一結構，其從半導基板12向外及/或向上延伸。在圖1之特定組態中，該鰭式結構14至少通過該通道區域且較佳地通過該重摻雜層18而延伸。在一些組態中，該鰭式結構14可進一步通過該井層19而延伸。如上文所注意，該鰭式結構14較佳地藉由沈積實質上未摻雜之(<1017原子/cm3)一磊晶層且隨後圖案化以形成該鰭式結構14而形成。在特定實施例中，鰭式結構之寬度可介於5 nm與50 nm之間，諸如10 nm。
    如上文所注意，通道區域60亦表示鰭式結構14之一區域。特定言之，藉由定義鰭式結構14之一部分而由在鰭式結構14中之半導體材料形成通道區域60，在該部分中不添加任何類型之雜質。結果，通道區域60定義實質上未摻雜之一通道區域。
    因為通道區域60形成為從半導基板12及重摻雜層18延伸之鰭式結構14之一部分，所以形成閘極(未展示)以沿著通道區域60之多個邊界、面、側及/或部分而鄰接通道區域60。藉由在此等邊界處首先沈積或生長一層氧化物而形成閘極。接著，較佳地，形成一堆疊之金屬以提供一閘極電極。然而，各種實施例並不在這方面限制，且亦可使用其他類型之閘極電極材料。
    如上文所注意，在形成隔離區域之前形成該重摻雜層18(及井區域19)。此外，該重摻雜層18可以多種方式形成。在特定實施例中，藉由植入適當物種而形成該重摻雜層18，以形成一個或多個重摻雜區域。類似地，藉由植入適當物種而形成井區域19，以形成一個或多個井區域。此程序示意地繪示於圖2中。在一個例示性程序中，該半導基板12係一p型導電率基板。接著，可提供p型摻雜材料，諸如硼(B)、鎵(Ga)、銦(In)或任何其他適宜p型摻雜物。在一個例示性程序中，提供一硼井植入及額外硼植入。該等植入可經組態以在表面處導致介於5×1018至1×1020原子/cm3之間之一p型摻雜濃度。取決於程序條件，亦可提供額外植入以限制在隨後步驟期間允許擴散至該磊晶層中之B(或其他p型摻雜物)的量。例如，可利用一Ge非晶化植入及一C+植入，以提供取代C之一表面層，以在隨後處理步驟期間減小或消除B擴散。對於另一FinFFT，可提供n型摻雜材料，諸如銻、砷、磷或任何其他適當n型摻雜物。例如，可提供一磷井植入及一砷植入。該等植入可分層以提供相異摻雜物濃度之區域，以達成期望之電特性。再次，該等植入可經選擇以在表面處提供介於5×1018至1×1020原子/cm3之間之一n型摻雜濃度。
    緊接形成重摻雜層18及井區域19後，可形成未摻雜之通道。圖3繪示在已在重摻雜層18之頂部上形成未摻雜之半導體材料之一磊晶層13之後之半導基板12。在一特定實施例中，該磊晶層13可為一層30 nm至40 nm之矽。磊晶層13將隨後被用於形成鰭式結構14。該磊晶層13使用任何適當磊晶生長技術沈積該磊晶層13而形成於重摻雜層18之頂部上。在一些實施例中，該半導基板12係一包括矽之基板，且該磊晶層13係一層矽。在此等實施例中，可使用各種化學氣相沈積技術以形成該磊晶層13。此等包含超高真空CVD、低壓CVD及遠端電漿CVD，等等。然而，各種實施例並不在這方面限制，且可等同地應用任何其他技術以形成矽磊晶層。
    本揭示內容亦預期磊晶層13可使用與矽基板相容之其他材料形成。例如，磊晶層可為一層之矽鍺合金、矽鍺碳合金、矽碳合金或鍺碳合金。此外，本揭示內容亦預期該半導基板12及該磊晶層13之組合物並不限制於第IV行元素。相反，本文中描述之方法及來自其之裝置可沒有限制地基於任何其他類型之半導體材料。
    現參考圖4，此繪示一鰭圖案化程序，其在特定實施例中在已在重摻雜層18之頂部上形成磊晶層13之後執行。一硬掩膜40施覆至半導基板12之適當部分，以劃定鰭式結構14。掩膜40可包括氧化矽、氮氧化矽、氮化矽層、此等材料之一組合，及/或用於保護直接在掩膜40下方之磊晶層13之部分免受蝕刻的任何其他適當材料。在已施覆掩膜40之後，一層光阻劑施覆於掩膜40之頂部上，且接著蝕刻半導基板12以形成鰭式結構14。各種程序(諸如光學微影術、浸潤式微影術、壓印微影術、直接寫入電子束微影術、x射線微影術或極端紫外線微影術)可用於在光阻劑中定義此圖案。接著使用一蝕刻程序，諸如電漿蝕刻以結束圖案化程序，以形成鰭式結構14。在各種實施例中亦可使用任何其他蝕刻程序。接著可基於被利用之特定技術而適當地將掩膜40移除或保留於隨後步驟。
    如上文所注意，用於形成磊晶層13之一些程序可提供0.5%或更好之數量級之均勻度之變動。相應地，跨該半導基板12之該磊晶層13之厚度係熟知的。此外，亦可使用提供高位準之均勻度之選擇之蝕刻程序。例如，可用提供2 nm至5 nm精確度之乾式蝕刻程序、電漿蝕刻程序。相應地，此等兩個位準之均勻度之組合允許蝕刻程序精確地定目標為對於所得鰭實質上達成一期望厚度之磊晶層13之一蝕刻程序。
    在形成該鰭式結構14之蝕刻程序之後，在整個結構之上形成作為一毯覆層膜之一介電層42。在一特定實施例中，使用一化學氣相沈積方法以經選擇以避免來自重摻雜區域18之摻雜物移動上至通道60中之一溫度沈積氧化矽。其後，使用一蝕刻程序以移除介電層42之一部分下至一預選擇位準，以定義隔離介電體16。較佳地，該蝕刻程序經組態使得所得隔離介電體16之頂部表面在重摻雜區域18之頂部表面處或接近重摻雜區域18之頂部表面，如圖1中所繪示。
    在一些實施例中，在蝕刻介電層42之前，可執行一平坦化蝕刻或拋光程序作為一第一步驟，使得該介電層42可被移除至鰭式結構14之頂部表面之位準。適宜拋光程序之實例包含化學機械拋光或機械拋光。接著該蝕刻可通過該鰭式結構14之垂直長度進行，使得結果暴露該鰭式結構14之至少未摻雜之部分(通道60)，產生一暴露之鰭式結構15，且該鰭式結構14之剩餘部分被該隔離介電體16圍繞。在蝕刻介電體42之後，導致暴露通道60，可形成閘極結構(未展示)使得閘極材料(例如，閘極介電體及閘極電極)環繞鰭式結構14之暴露表面(即，繞暴露之鰭式結構15)。
    此程序之結果為暴露之鰭式結構15之電高度(即，通道60之高度，由Hfin_eff表示)及暴露之鰭式結構15之實際高度相同或實質上相同。由於上文描述之程序，該暴露之鰭式結構15與重摻雜層18相關聯之部分相對較小。結果，通道60之所有未摻雜之區域在隨後形成之閘極結構之直接控制下。此外，即使重摻雜層18之一些部分在隨後形成之閘極結構之控制下，其內之高摻雜將防止此部分鰭式結構14顯著地影響裝置10之操作。
    本揭示內容亦預期上文描述之方法可經利用以允許平面CMOS及FinFET裝置併發地在相同基板上形成。明確言之，上文描述之方法對於將深空乏通道(DDC)電晶體裝置與FinFET裝置整合可為有用的。DDC電晶體裝置順從上文描述之程序流程，因為其等亦對於形成於一個或多個高摻雜層之頂部上之通道使用一實質上未摻雜之層。
    例如藉由將摻雜物植入一基板中以形成一重摻雜網篩層(5×1018至1×1020原子/cm3)而藉由對於該等CMOS裝置形成一井而形成DDC電晶體。緊接此之後可為一未摻雜或輕微摻雜(統稱為「實質上未摻雜」)之毯覆層磊晶層(<5×1017)，其沈積在網篩層之上(跨多個晶粒及電晶體晶粒塊延伸)。應形成此一毯覆層磊晶層，以便減小井植入期間置入之散射摻雜物向上移動。在一些組態中，輕摻雜臨限電壓(Vth)調整層(介於5×1017與2×1019原子/cm3之間)亦可形成於網篩層中或鄰近於該網篩層，以允許調整臨限電壓之更精細及對抗不需要之洩漏電流的控制。較佳地，藉助於通道植入或暈植入之習知臨限電壓設定方法並不使用於DDC電晶體之製造中。然而，存在其他各種實施例。
    關於例示性DDC電晶體結構之細節更完整地描述於題為「ELECTRONIC DEVICES AND SYSTEMS,AND METHODS FOR MAKING AND USING THE SAME」且於2010年2月18日申請之美國專利申請案第12/708,497號、題為「LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF」且於2010年12月17日申請之美國專利申請案第12/971,884號、題為「TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF」且於2010年12月17日申請之美國專利申請案第12/971,955號、題為「ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES」且於2010年9月30日申請之美國專利申請案第12/895,785號(其等全文之揭示內容以引用之方式併入本文中)，及題為「ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION」且於2010年9月30日申請之美國專利申請案第12/895,813號中。
    現參考圖5A，程序可首先開始於在半導基板512之表面處形成一重摻雜層區域518。視需要，亦可形成一井區域(未展示)，如前文所描述。該重摻雜層區域518係用於將要形成之FinFET裝置，及用於將要形成之DDC裝置。儘管該重摻雜區域518中之摻雜濃度可出於對於一FinFET提供一足夠本體之目的經選擇，該摻雜濃度亦可對於一CMOS裝置(諸如一DDC裝置)而選擇。例如，在一DDC裝置之情況中，該重摻雜區域518可經組態以對於該DDC裝置提供一高摻雜之網篩層(圖5A至圖5D中之「網篩」)及Vth調整層(圖5A至圖5D中之「VT」)。對於每個裝置選擇重摻雜層區域518之摻雜物位準及材料，且其等可相同或可相異。若摻雜物位準及/或材料相異，則使用掩膜步驟以阻擋差別摻雜之區。
    可接著形成實質上未摻雜之磊晶層513，如圖5B中所展示。該磊晶層513可以與前文所描述實質上相同的方式形成。其後，可使用微影術及蝕刻步驟而圖案化該磊晶層513，以同時形成結構514及554，如圖5C中所展示。在圖5C中繪示之實施例中，結構514係一鰭式結構，而結構554係一裝置島狀物或一作用區結構或區域(用於在其上形成平面裝置)。在圖5C中，為便於繪示，不展示井植入。值得注意的是，亦可利用磊晶層513之蝕刻，以定義結構514與544之間之隔離特徵部。因此，該蝕刻程序可經組態以便蝕刻該磊晶層513之特定區域，重摻雜區域518之下面部分，及半導基板512之部分。
    其次，沈積一介電體542以覆蓋於所有蝕刻部分之上。此可較佳地使用化學氣相沈積而在低於最大溫度之一程序中執行，以避免摻雜物移動上至實質上未摻雜之磊晶層513中。接著，該介電體542蝕刻回至一期望深度，以工作為FinFET與平面裝置兩者之隔離，以產生隔離介電體516。由於介電體542之蝕刻，該介電隔離516將在定義一暴露之鰭式結構515之底部之一深度，以用於定義FinFET裝置，且將與作用區區域554之一上表面對準，以對於其上形成之平面裝置提供隔離。
    接著可執行額外處理，以形成平面及FinFET裝置，亦如圖5D中所展示。特定言之，閘極介電體530形成於暴露之鰭式結構515之暴露側上。一閘極介電體560亦形成於該等作用區區域554之上表面上。該等閘極介電體530及560可相同或不同，且可使用相同或不同程序形成。較佳地，閘極介電體530及560兩者在一熔爐中使用一熱氧化程序使用適宜於避免摻雜物移動上至實質上未摻雜之通道區中之一溫度而形成。接著較佳地使用一物理氣相沈積程序而從金屬形成每個裝置之閘極電極532及562。材料可包含TiN、Al合金、W及其他材料或其組合，以達成一期望之工作功能。對於平面裝置，可使用一閘極第一途徑或閘極最後途徑而形成閘極電極。額外地，對於平面裝置形成源極及汲極區域570。在一特定實施例中，此等區域可經由植入至該作用區區域554中形成。此一程序可包含對於源極/汲極延伸植入，在該作用區區域554中形成間隔物特徵部572。
    本揭示內容亦預期可對於平面CMOS裝置提供額外程序步驟。例如，該等平面CMOS裝置之通道區域可要求比該等FinFET裝置更高之一摻雜濃度，且因此將使用額外摻雜步驟。在還有另外實例中，可在形成閘極介電體560及閘極電極562之前執行選擇性蝕刻該作用區結構554，以減小用於該等平面CMOS裝置之磊晶層之厚度。
    本揭示內容亦預期緊接圖5C之結構之形成後，該程序流程可以一分歧之方式進行。即，可單獨執行不同裝置類型之許多或所有處理步驟。此可經由使用掩膜層而完成，以防止在某些裝置上執行程序步驟。例如，可利用掩膜層以允許用於閘極介電體、閘極電極及裝置植入之不同程序及材料，等等。然而，各種實施例並不在這方面限制，且亦可對於不同裝置將任何其他程序分歧。
    雖然已在上文描述各種實施例，但是應理解，其等僅藉助於實例且並非限制而展現。可在未脫離實施例之精神或範疇之下根據本文中之揭示內容對所揭示之實施例作出許多變化。因此，本發明之廣度及範疇不應由上文描述之實施例之任何者限制。相反，本發明之範疇應根據以下申請專利範圍及其等效物定義。
    儘管已相對於一個或多個實施繪示及描述實施例，然而熟習此項技術者在閱讀及理解本說明書及所附圖式時將出現等效改變及修改。再者，雖然一實施例之一特定特徵部可能已相對於若干實施之僅一者而揭示，但是當可能期望及有利於任何給定或特定應用時，此特徵部可與其他實施之一個或多個其他特徵部組合。
    本文中使用之專門名詞僅係出於描述特定實施例之目的，且並不意欲限制本發明。如本文中所使用，除非內文明確地另有指示，否則單數形式「一(「a」、「an」)」及「該」(「the」)意欲亦包含複數形式。此外，對術語「包含(「including」、「includes」)」、「具有(「having」、「has」、「with」)」或其等之變體使用於實施方式及/或申請專利範圍中之限度，此等術語意欲以類似於術語「包括」之一方式作為包含性的。
    除非另外定義，否則本文中使用之所有術語(包含技術及科學術語)具有與一般技術者普遍所理解之相同意義。將進一步理解，術語(諸如在普遍使用之辭典中定義之術語)應解譯為具有與其等在相關技術之內文中之意義一致之一意義，且將不以一理想化或過度正式之意思解譯，除非在本文中明確如此定義。
    10‧‧‧半導體裝置
    12‧‧‧半導基板
    13‧‧‧磊晶層
    14‧‧‧鰭式結構
    15‧‧‧鰭式結構
    16‧‧‧隔離介電體
    18‧‧‧重摻雜層
    19‧‧‧井區域
    40‧‧‧硬掩膜
    42‧‧‧介電層
    60‧‧‧通道區域
    512‧‧‧半導基板
    513‧‧‧磊晶層
    514‧‧‧結構
    515‧‧‧鰭式結構
    516‧‧‧隔離介電體
    518‧‧‧重摻雜區域/重摻雜層區域
    530‧‧‧閘極介電體
    532‧‧‧閘極電極
    542‧‧‧介電體
    554‧‧‧結構
    560‧‧‧閘極介電體
    562‧‧‧閘極電極
    570‧‧‧源極及汲極區域
    572‧‧‧間隔物特徵部
    圖1繪示根據一特定實施例之一半導體裝置之一截面圖；圖2至圖4繪示用於製造圖1之半導體裝置之一方法中之各種步驟；及圖5A至圖5D繪示根據一特定實施例之用於在一相同基板上形成FinFET及平面MOSFET裝置之各種步驟。
    10‧‧‧半導體裝置
    12‧‧‧半導基板
    14‧‧‧鰭式結構
    15‧‧‧鰭式結構
    16‧‧‧隔離介電體
    18‧‧‧重摻雜層
    19‧‧‧井區域
    60‧‧‧通道區域
    权利要求:
    Claims (18)
    [1] 一種製造半導體裝置之方法，其包括：提供一半導基板；定義在該半導基板之至少一個區中的該半導基板之一表面處的一重摻雜區域，該重摻雜區域包括至少一個重摻雜層，該至少一個重摻雜層具有大於該半導基板之一摻雜濃度之一摻雜濃度及具一第一導電率類型；在該半導基板上形成半導體材料之一額外層，該額外層包括一實質上未摻雜之層；對該半導基板應用一第一移除程序，以定義在該至少一個區中之至少一個未蝕刻部分及至少一個蝕刻部分，該至少一個未蝕刻部分定義至少一個鰭式結構，且該至少一個蝕刻部分通過至少該額外層之厚度而延伸；在該至少一個蝕刻部分中形成具有一厚度之一介電體，該厚度經選擇使得該至少一個鰭式結構中之該額外層保持暴露；及形成環繞該至少一個鰭式結構之該等暴露表面之一閘極。
    [2] 如請求項1之方法，其中該形成包括：在應用該第一移除程序之前，在該額外層上提供依對應於該至少一個鰭式結構之一圖案的一停止層；在應用該第一移除程序之後，在該半導基板上沈積一毯覆層介電膜；對該半導基板應用一平坦化程序，使得該毯覆層介電膜之一平坦化表面與該停止層實質上符合；及對該半導基板應用一第二移除程序，其相比於其他材料優先移除該毯覆層介電膜。
    [3] 如請求項1之方法，其中定義該重摻雜區域包括：植入至少一個物種，以將該第一導電率類型之摻雜物原子提供至約5×1018至1×1020原子/cm3之一濃度。
    [4] 如請求項1之方法，其中定義該重摻雜區域包括：在該半導基板之該表面處形成至少一個障壁層，以防止摻雜物擴散至該額外層中。
    [5] 如請求項1之方法，其中該半導基板包括一塊體矽基板、一磊晶基板或一絕緣體上矽基板之一者。
    [6] 如請求項1之方法，其中形成該額外層包括：沈積一層磊晶矽。
    [7] 一種製造半導體裝置之方法，其包括：提供一矽基板；定義在該矽基板之至少一區中之該矽基板之一表面處之一重摻雜區域，該重摻雜區域包括至少一個重摻雜層，該至少一個重摻雜層具有大於該半導基板之一摻雜濃度之一摻雜濃度及具一第一導電率類型；在該矽基板上形成半導體材料之一額外層，該額外層包括一實質上未摻雜之包括矽之磊晶層；對該矽基板應用一第一移除程序，以定義在該至少一個區中之至少一個未蝕刻部分及至少一個蝕刻部分，該至少一個未蝕刻部分定義至少一個鰭式結構，且該至少一個蝕刻部分通過該重摻雜區域之至少一部分而延伸；在該至少一個蝕刻部分中安置至少一個介電層，該至少一個介電層之厚度經選擇以使得該至少一個介電層之該上表面鄰接該重摻雜區域；及在該至少鰭式結構中形成一閘極，以提供至少一個FinFET裝置。
    [8] 如請求項7之方法，其中該安置包括：在應用該第一移除程序之前，在該額外層上提供依對應於該至少一個鰭式結構之一圖案的一停止層；在應用該第一移除程序之後，在該矽基板上沈積至少一個毯覆層介電膜；對該矽基板應用一平坦化程序，使得該至少一個毯覆層介電膜之一平坦化表面與該停止層實質上符合；及對該矽基板應用一第二移除程序，其相比於其他材料優先地移除該至少一個毯覆層介電膜之一部分，以產生該至少一個介電層。
    [9] 如請求項7之方法，其中定義該重摻雜區域包括：植入至少一個物種，以提供該第一導電率類型之摻雜物原子。
    [10] 如請求項7之方法，其中定義該重摻雜區域包括：在該矽基板之該表面處形成至少一個障壁層，以防止摻雜物擴散至該額外層中。
    [11] 如請求項7之方法，其中該矽基板包括一塊體矽基板、一磊晶基板或一絕緣體上矽基板之一者。
    [12] 如請求項7之方法，其中實質上未摻雜之包括矽之磊晶層包括一實質上未摻雜之矽磊晶層。
    [13] 一種製造半導體裝置之方法，其包括：提供一半導基板；定義在該半導基板之至少一個區中的該半導基板之一表面處的一重摻雜區域，該重摻雜區域包括至少一個重摻雜層，該至少一個重摻雜層具有大於該半導基板之一摻雜濃度之一摻雜濃度及具一第一導電率類型；在該半導基板上形成半導體材料之一額外層，該額外層包括一實質上未摻雜之層；對該半導基板應用一第一移除程序，以定義在該至少一個區中之至少一個第一未蝕刻部分、至少一個第二未蝕刻部分及至少一個蝕刻部分，該至少一個第一未蝕刻部分定義至少一個鰭式結構，該至少一個第二未蝕刻部分定義至少一個平面作用區，且該至少一個蝕刻部分至少通過該重摻雜層之一部分而延伸通過；在該至少一個蝕刻部分中形成至少一個介電層，使得該至少一個介電層之一上表面鄰接該至少一個鰭式結構中之該重摻雜區域，且鄰接該至少一個平面作用區中之該額外層之一上表面；及在該至少一個鰭式結構中形成一閘極，以提供至少一個FinFET裝置；及在該至少一個平面作用區域中形成一閘極，以提供至少一個平面MOSFET裝置。
    [14] 如請求項13之方法，其中該至少一個蝕刻部分通過該重摻雜區域而延伸。
    [15] 如請求項13之方法，其中該安置包括：在應用該第一移除程序之前，在該額外層上提供依對應於該至少一個鰭式結構及該至少一個平面作用區之一圖案的一停止層；在應用該第一移除程序之後，在該矽基板上沈積至少一個毯覆層介電膜；對該半導基板應用一平坦化程序，使得該至少一個毯覆層介電膜之一平坦化表面與該停止層實質上符合；在該至少一個平面作用區之上形成一掩膜層，且聯接該平坦化表面之部分；及對該半導基板應用一第二移除程序，其相比於其他材料優先地移除該至少一個毯覆層介電膜之一部分，以產生該至少一個介電層。
    [16] 如請求項13之方法，其中定義該重摻雜區域包括植入至少一個物種，以提供該第一導電率類型之摻雜物原子。
    [17] 如請求項13之方法，其中定義該重摻雜區域包括植入至少一個物種，以對於該至少一個平面MOSFET裝置提供至少一個臨限電壓調整層。
    [18] 如請求項13之方法，其中定義該重摻雜區域包括在該矽基板之該表面處形成至少一個障壁層，以防止摻雜物擴散至該額外層中。
    类似技术:
    公开号 | 公开日 | 专利标题
    TWI527095B|2016-03-21|具鰭式結構之半導體裝置及其製造方法
    US9263549B2|2016-02-16|Fin-FET transistor with punchthrough barrier and leakage protection regions
    TWI545761B|2016-08-11|半導體元件與其形成方法及ｐ型金氧半電晶體
    US8871584B2|2014-10-28|Replacement source/drain finFET fabrication
    CN101378080B|2010-12-08|半导体器件及其制造方法
    US10038075B2|2018-07-31|Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
    TWI383501B|2013-01-21|半導體裝置及其製造方法
    US10170475B2|2019-01-01|Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
    US10008501B2|2018-06-26|Sandwich EPI channel for device enhancement
    CN105322019A|2016-02-10|具有垂直沟道的半导体器件
    CN103985636A|2014-08-13|调整多阈值电压的FinFET/三栅极沟道掺杂
    US9184287B2|2015-11-10|Native PMOS device with low threshold voltage and high drive current and method of fabricating the same
    CN105336772B|2021-11-30|鳍式tfet及其制造方法
    US8999803B2|2015-04-07|Methods for fabricating integrated circuits with the implantation of fluorine
    US20150228649A1|2015-08-13|Transistor with well tap implant
    US10134902B2|2018-11-20|PMOS FinFET
    US20080265362A1|2008-10-30|Building fully-depleted and bulk transistors on same chip
    US9685528B2|2017-06-20|Fin semiconductor device and method of manufacture with source/drain regions having opposite conductivities
    KR20060077546A|2006-07-05|반도체 소자의 제조 방법
    CN104733308B|2018-08-10|半导体器件的形成方法
    CN105097535B|2018-03-13|FinFet器件的制造方法
    US8916430B2|2014-12-23|Methods for fabricating integrated circuits with the implantation of nitrogen
    US9070709B2|2015-06-30|Method for producing a field effect transistor with implantation through the spacers
    US8455319B2|2013-06-04|Vertical transistor for random-access memory and manufacturing method thereof
    同族专利:
    公开号 | 公开日
    TWI527095B|2016-03-21|
    WO2013022753A3|2013-05-10|
    KR20140050700A|2014-04-29|
    US9054219B1|2015-06-09|
    KR101891373B1|2018-08-24|
    WO2013022753A2|2013-02-14|
    TW201626446A|2016-07-16|
    TWI606498B|2017-11-21|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US9806154B2|2015-01-20|2017-10-31|Taiwan Semiconductor Manufacturing Company Ltd.|FinFET structure and method for manufacturing thereof|
    TWI622129B|2015-12-15|2018-04-21|台灣積體電路製造股份有限公司|半導體結構及其製造方法|US4021835A|1974-01-25|1977-05-03|Hitachi, Ltd.|Semiconductor device and a method for fabricating the same|
    US3958266A|1974-04-19|1976-05-18|Rca Corporation|Deep depletion insulated gate field effect transistors|
    US4000504A|1975-05-12|1976-12-28|Hewlett-Packard Company|Deep channel MOS transistor|
    US4276095A|1977-08-31|1981-06-30|International Business Machines Corporation|Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations|
    US4242691A|1978-09-18|1980-12-30|Mitsubishi Denki Kabushiki Kaisha|MOS Semiconductor device|
    DE3069973D1|1979-08-25|1985-02-28|Zaidan Hojin Handotai Kenkyu|Insulated-gate field-effect transistor|
    US4315781A|1980-04-23|1982-02-16|Hughes Aircraft Company|Method of controlling MOSFET threshold voltage with self-aligned channel stop|
    JPH0216020B2|1980-04-30|1990-04-13|Sanyo Electric Co||
    US4518926A|1982-12-20|1985-05-21|At&T Bell Laboratories|Gate-coupled field-effect transistor pair amplifier|
    JPS59193066A|1983-04-15|1984-11-01|Matsushita Electric Ind Co Ltd|Mos semiconductor device|
    US4559091A|1984-06-15|1985-12-17|Regents Of The University Of California|Method for producing hyperabrupt doping profiles in semiconductors|
    US5060234A|1984-11-19|1991-10-22|Max-Planck Gesellschaft Zur Forderung Der Wissenschaften|Injection laser with at least one pair of monoatomic layers of doping atoms|
    US4617066A|1984-11-26|1986-10-14|Hughes Aircraft Company|Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing|
    US4578128A|1984-12-03|1986-03-25|Ncr Corporation|Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants|
    US4662061A|1985-02-27|1987-05-05|Texas Instruments Incorporated|Method for fabricating a CMOS well structure|
    JPH0770606B2|1985-11-29|1995-07-31|株式会社日立製作所|半導体装置|
    JPH0426790B2|1985-11-29|1992-05-08|Hitachi Ltd||
    GB8606748D0|1986-03-19|1986-04-23|Secr Defence|Monitoring surface layer growth|
    US4780748A|1986-06-06|1988-10-25|American Telephone & Telegraph Company, At&T Bell Laboratories|Field-effect transistor having a delta-doped ohmic contact|
    AT58030T|1986-06-10|1990-11-15|Siemens Ag|Verfahren zum herstellen von hochintegrierten komplementaeren mosfeldeffekttransistorschaltungen.|
    US5156990A|1986-07-23|1992-10-20|Texas Instruments Incorporated|Floating-gate memory cell with tailored doping profile|
    DE3789894T2|1987-01-05|1994-09-08|Seiko Instr Inc|MOS-Feldeffekttransistor und dessen Herstellungsmethode.|
    GB2206010A|1987-06-08|1988-12-21|Philips Electronic Associated|Differential amplifier and current sensing circuit including such an amplifier|
    EP0312237A3|1987-10-13|1989-10-25|AT&T Corp.|Interface charge enhancement in delta-doped heterostructure|
    US5156989A|1988-11-08|1992-10-20|Siliconix, Incorporated|Complementary, isolated DMOS IC technology|
    US5034337A|1989-02-10|1991-07-23|Texas Instruments Incorporated|Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices|
    US4956311A|1989-06-27|1990-09-11|National Semiconductor Corporation|Double-diffused drain CMOS process using a counterdoping technique|
    US5208473A|1989-11-29|1993-05-04|Mitsubishi Denki Kabushiki Kaisha|Lightly doped MISFET with reduced latchup and punchthrough|
    JP2822547B2|1990-03-06|1998-11-11|富士通株式会社|高電子移動度トランジスタ|
    KR920008834A|1990-10-09|1992-05-28|아이자와 스스무|박막 반도체 장치|
    US5166765A|1991-08-26|1992-11-24|At&T Bell Laboratories|Insulated gate field-effect transistor with pulse-shaped doping|
    KR940006711B1|1991-09-12|1994-07-25|포항종합제철 주식회사|델타도핑 양자 우물전계 효과 트랜지스터의 제조방법|
    JP2851753B2|1991-10-22|1999-01-27|三菱電機株式会社|半導体装置およびその製造方法|
    JPH05315598A|1992-05-08|1993-11-26|Fujitsu Ltd|半導体装置|
    US5422508A|1992-09-21|1995-06-06|Siliconix Incorporated|BiCDMOS structure|
    JPH06151828A|1992-10-30|1994-05-31|Toshiba Corp|半導体装置及びその製造方法|
    US5298763A|1992-11-02|1994-03-29|Motorola, Inc.|Intrinsically doped semiconductor structure and method for making|
    US5444008A|1993-09-24|1995-08-22|Vlsi Technology, Inc.|High-performance punchthrough implant method for MOS/VLSI|
    US5625568A|1993-12-22|1997-04-29|Vlsi Technology, Inc.|Method and apparatus for compacting integrated circuits with standard cell architectures|
    DE69516767T2|1994-02-14|2000-11-23|Koninkl Philips Electronics Nv|Referenzschaltung mit kontrollierter temperaturabhängigkeit|
    KR0144959B1|1994-05-17|1998-07-01|김광호|반도체장치 및 제조방법|
    US5622880A|1994-08-18|1997-04-22|Sun Microsystems, Inc.|Method of making a low power, high performance junction transistor|
    US5889315A|1994-08-18|1999-03-30|National Semiconductor Corporation|Semiconductor structure having two levels of buried regions|
    US5818078A|1994-08-29|1998-10-06|Fujitsu Limited|Semiconductor device having a regrowth crystal region|
    US5559368A|1994-08-30|1996-09-24|The Regents Of The University Of California|Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation|
    EP0717435A1|1994-12-01|1996-06-19|AT&T Corp.|Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby|
    US6153920A|1994-12-01|2000-11-28|Lucent Technologies Inc.|Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby|
    JPH08250728A|1995-03-10|1996-09-27|Sony Corp|電界効果型半導体装置及びその製造方法|
    US5608253A|1995-03-22|1997-03-04|Advanced Micro Devices Inc.|Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits|
    US5552332A|1995-06-02|1996-09-03|Motorola, Inc.|Process for fabricating a MOSFET device having reduced reverse short channel effects|
    US5663583A|1995-06-06|1997-09-02|Hughes Aircraft Company|Low-noise and power ALGaPSb/GaInAs HEMTs and pseudomorpohic HEMTs on GaAs substrate|
    JP3462301B2|1995-06-16|2003-11-05|三菱電機株式会社|半導体装置及びその製造方法|
    US5624863A|1995-07-17|1997-04-29|Micron Technology, Inc.|Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate|
    US5754826A|1995-08-04|1998-05-19|Synopsys, Inc.|CAD and simulation system for targeting IC designs to multiple fabrication processes|
    KR0172793B1|1995-08-07|1999-02-01|김주용|반도체소자의 제조방법|
    JPH0973784A|1995-09-07|1997-03-18|Nec Corp|半導体装置及びその制御回路|
    US6127700A|1995-09-12|2000-10-03|National Semiconductor Corporation|Field-effect transistor having local threshold-adjust doping|
    US5712501A|1995-10-10|1998-01-27|Motorola, Inc.|Graded-channel semiconductor device|
    US5753555A|1995-11-22|1998-05-19|Nec Corporation|Method for forming semiconductor device|
    DE69609313T2|1995-12-15|2001-02-01|Koninkl Philips Electronics Nv|Halbleiterfeldeffektanordnung mit einer sige schicht|
    US5698884A|1996-02-07|1997-12-16|Thunderbird Technologies, Inc.|Short channel fermi-threshold field effect transistors including drain field termination region and methods of fabricating same|
    US6492232B1|1998-06-15|2002-12-10|Motorola, Inc.|Method of manufacturing vertical semiconductor device|
    JPH09270466A|1996-04-01|1997-10-14|Mitsubishi Electric Corp|半導体装置及びその製造方法|
    JPH1022462A|1996-06-28|1998-01-23|Sharp Corp|半導体装置及びその製造方法|
    US5847419A|1996-09-17|1998-12-08|Kabushiki Kaisha Toshiba|Si-SiGe semiconductor device and method of fabricating the same|
    US5736419A|1996-11-12|1998-04-07|National Semiconductor Corporation|Method of fabricating a raised source/drain MOSFET using self-aligned POCl3 for doping gate/source/drain regions|
    JPH10163342A|1996-12-04|1998-06-19|Sharp Corp|半導体装置|
    JPH10223853A|1997-02-04|1998-08-21|Mitsubishi Electric Corp|半導体装置|
    US5918129A|1997-02-25|1999-06-29|Advanced Micro Devices, Inc.|Method of channel doping using diffusion from implanted polysilicon|
    JPH10242153A|1997-02-26|1998-09-11|Hitachi Ltd|半導体ウエハ、半導体ウエハの製造方法、半導体装置および半導体装置の製造方法|
    US5936868A|1997-03-06|1999-08-10|Harris Corporation|Method for converting an integrated circuit design for an upgraded process|
    JPH10270687A|1997-03-27|1998-10-09|Mitsubishi Electric Corp|電界効果トランジスタおよびその製造方法|
    US5923067A|1997-04-04|1999-07-13|International Business Machines Corporation|3-D CMOS-on-SOI ESD structure and method|
    US6060345A|1997-04-21|2000-05-09|Advanced Micro Devices, Inc.|Method of making NMOS and PMOS devices with reduced masking steps|
    US6218895B1|1997-06-20|2001-04-17|Intel Corporation|Multiple well transistor circuits having forward body bias|
    US6218892B1|1997-06-20|2001-04-17|Intel Corporation|Differential circuits employing forward body bias|
    US6194259B1|1997-06-27|2001-02-27|Advanced Micro Devices, Inc.|Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants|
    US6723621B1|1997-06-30|2004-04-20|International Business Machines Corporation|Abrupt delta-like doping in Si and SiGe films by UHV-CVD|
    US5923987A|1997-06-30|1999-07-13|Sun Microsystems, Inc.|Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface|
    US5946214A|1997-07-11|1999-08-31|Advanced Micro Devices|Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns|
    US5989963A|1997-07-21|1999-11-23|Advanced Micro Devices, Inc.|Method for obtaining a steep retrograde channel profile|
    JP3544833B2|1997-09-18|2004-07-21|株式会社東芝|半導体装置及びその製造方法|
    FR2769132B1|1997-09-29|2003-07-11|Sgs Thomson Microelectronics|Amelioration de l'isolement entre alimentations d'un circuitanalogique-numerique|
    US5856003A|1997-11-17|1999-01-05|Taiwan Semiconductor Manufacturing Company, Ltd.|Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device|
    JPH11163458A|1997-11-26|1999-06-18|Mitsui Chem Inc|半導体レーザ装置|
    US6426260B1|1997-12-02|2002-07-30|Magepower Semiconductor Corp.|Switching speed improvement in DMO by implanting lightly doped region under gate|
    US6271070B2|1997-12-25|2001-08-07|Matsushita Electronics Corporation|Method of manufacturing semiconductor device|
    KR100339409B1|1998-01-14|2002-09-18|주식회사 하이닉스반도체|반도체소자및그의제조방법|
    US6088518A|1998-01-30|2000-07-11|Aspec Technology, Inc.|Method and system for porting an integrated circuit layout from a reference process to a target process|
    US6001695A|1998-03-02|1999-12-14|Texas Instruments - Acer Incorporated|Method to form ultra-short channel MOSFET with a gate-side airgap structure|
    US6096611A|1998-03-13|2000-08-01|Texas Instruments - Acer Incorporated|Method to fabricate dual threshold CMOS circuits|
    KR100265227B1|1998-06-05|2000-09-15|김영환|씨모스 트랜지스터의 제조 방법|
    US6072217A|1998-06-11|2000-06-06|Sun Microsystems, Inc.|Tunable threshold SOI device using isolated well structure for back gate|
    US6262461B1|1998-06-22|2001-07-17|Motorola, Inc.|Method and apparatus for creating a voltage threshold in a FET|
    US5985705A|1998-06-30|1999-11-16|Lsi Logic Corporation|Low threshold voltage MOS transistor and method of manufacture|
    KR100292818B1|1998-07-02|2001-11-05|윤종용|모오스트랜지스터제조방법|
    US6320222B1|1998-09-01|2001-11-20|Micron Technology, Inc.|Structure and method for reducing threshold voltage variations due to dopant fluctuations|
    US6066533A|1998-09-29|2000-05-23|Advanced Micro Devices, Inc.|MOS transistor with dual metal gate structure|
    US6143593A|1998-09-29|2000-11-07|Conexant Systems, Inc.|Elevated channel MOSFET|
    US20020008257A1|1998-09-30|2002-01-24|John P. Barnak|Mosfet gate electrodes having performance tuned work functions and methods of making same|
    US6221724B1|1998-11-06|2001-04-24|Advanced Micro Devices, Inc.|Method of fabricating an integrated circuit having punch-through suppression|
    US6084271A|1998-11-06|2000-07-04|Advanced Micro Devices, Inc.|Transistor with local insulator structure|
    US6380019B1|1998-11-06|2002-04-30|Advanced Micro Devices, Inc.|Method of manufacturing a transistor with local insulator structure|
    US6184112B1|1998-12-02|2001-02-06|Advanced Micro Devices, Inc.|Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile|
    US6214654B1|1999-01-27|2001-04-10|Advanced Micro Devices, Inc.|Method for forming super-steep retrograded channel for CMOS transistor using rapid laser annealing to reduce thermal budget|
    US6245618B1|1999-02-03|2001-06-12|Advanced Micro Devices, Inc.|Mosfet with localized amorphous region with retrograde implantation|
    JP2000243958A|1999-02-24|2000-09-08|Toshiba Corp|半導体装置およびその製造方法|
    US6060364A|1999-03-02|2000-05-09|Advanced Micro Devices, Inc.|Fast Mosfet with low-doped source/drain|
    US7145167B1|2000-03-11|2006-12-05|International Business Machines Corporation|High speed Ge channel heterostructures for field effect devices|
    US6928128B1|1999-05-03|2005-08-09|Rambus Inc.|Clock alignment circuit having a self regulating voltage supply|
    US6232164B1|1999-05-24|2001-05-15|Taiwan Semiconductor Manufacturing Company|Process of making CMOS device structure having an anti-SCE block implant|
    US6190979B1|1999-07-12|2001-02-20|International Business Machines Corporation|Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill|
    US6235597B1|1999-08-06|2001-05-22|International Business Machines Corporation|Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication|
    US6271547B1|1999-08-06|2001-08-07|Raytheon Company|Double recessed transistor with resistive layer|
    US6268640B1|1999-08-12|2001-07-31|International Business Machines Corporation|Forming steep lateral doping distribution at source/drain junctions|
    US6503801B1|1999-08-18|2003-01-07|Advanced Micro Devices, Inc.|Non-uniform channel profile via enhanced diffusion|
    US6426279B1|1999-08-18|2002-07-30|Advanced Micro Devices, Inc.|Epitaxial delta doping for retrograde channel profile|
    US6444550B1|1999-08-18|2002-09-03|Advanced Micro Devices, Inc.|Laser tailoring retrograde channel profile in surfaces|
    DE19940362A1|1999-08-25|2001-04-12|Infineon Technologies Ag|MOS-Transistor und Verfahren zu dessen Herstellung|
    US6162693A|1999-09-02|2000-12-19|Micron Technology, Inc.|Channel implant through gate polysilicon|
    US7091093B1|1999-09-17|2006-08-15|Matsushita Electric Industrial Co., Ltd.|Method for fabricating a semiconductor device having a pocket dopant diffused layer|
    US6506640B1|1999-09-24|2003-01-14|Advanced Micro Devices, Inc.|Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through|
    JP3371871B2|1999-11-16|2003-01-27|日本電気株式会社|半導体装置の製造方法|
    US6313489B1|1999-11-16|2001-11-06|Philips Electronics North America Corporation|Lateral thin-film silicon-on-insulator device having a lateral drift region with a retrograde doping profile, and method of making such a device|
    US6449749B1|1999-11-18|2002-09-10|Pdf Solutions, Inc.|System and method for product yield prediction|
    US6541829B2|1999-12-03|2003-04-01|Kabushiki Kaisha Toshiba|Semiconductor device and method of manufacturing the same|
    GB9929084D0|1999-12-08|2000-02-02|Regan Timothy J|Modification of integrated circuits|
    US7638380B2|2000-01-05|2009-12-29|Agere Systems Inc.|Method for manufacturing a laterally diffused metal oxide semiconductor device|
    US6633066B1|2000-01-07|2003-10-14|Samsung Electronics Co., Ltd.|CMOS integrated circuit devices and substrates having unstrained silicon active layers|
    US6297132B1|2000-02-07|2001-10-02|Chartered Semiconductor Manufacturing Ltd.|Process to control the lateral doping profile of an implanted channel region|
    US6797994B1|2000-02-14|2004-09-28|Raytheon Company|Double recessed transistor|
    US7015546B2|2000-02-23|2006-03-21|Semiconductor Research Corporation|Deterministically doped field-effect devices and methods of making same|
    US6326666B1|2000-03-23|2001-12-04|International Business Machines Corporation|DTCMOS circuit having improved speed|
    US6548842B1|2000-03-31|2003-04-15|National Semiconductor Corporation|Field-effect transistor for alleviating short-channel effects|
    US6319799B1|2000-05-09|2001-11-20|Board Of Regents, The University Of Texas System|High mobility heterojunction transistor and method|
    US6461928B2|2000-05-23|2002-10-08|Texas Instruments Incorporated|Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants|
    JP2001352057A|2000-06-09|2001-12-21|Mitsubishi Electric Corp|半導体装置、およびその製造方法|
    WO2002001641A1|2000-06-27|2002-01-03|Matsushita Electric Industrial Co., Ltd.|Dispositif semi-conducteur|
    DE10034942B4|2000-07-12|2004-08-05|Infineon Technologies Ag|Verfahren zur Erzeugung eines Halbleitersubstrats mit vergrabener Dotierung|
    US6624488B1|2000-08-07|2003-09-23|Advanced Micro Devices, Inc.|Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices|
    US6503783B1|2000-08-31|2003-01-07|Micron Technology, Inc.|SOI CMOS device with reduced DIBL|
    US6391752B1|2000-09-12|2002-05-21|Taiwan Semiconductor Manufacturing, Co., Ltd.|Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane|
    US7064399B2|2000-09-15|2006-06-20|Texas Instruments Incorporated|Advanced CMOS using super steep retrograde wells|
    US6891627B1|2000-09-20|2005-05-10|Kla-Tencor Technologies Corp.|Methods and systems for determining a critical dimension and overlay of a specimen|
    US6617217B2|2000-10-10|2003-09-09|Texas Instruments Incorpated|Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride|
    US6448590B1|2000-10-24|2002-09-10|International Business Machines Corporation|Multiple threshold voltage FET using multiple work-function gate materials|
    DE10061191A1|2000-12-08|2002-06-13|Ihp Gmbh|Schichten in Substratscheiben|
    US6300177B1|2001-01-25|2001-10-09|Chartered Semiconductor Manufacturing Inc.|Method to form transistors with multiple threshold voltages using a combination of different work function gate materials|
    US7652326B2|2003-05-20|2010-01-26|Fairchild Semiconductor Corporation|Power semiconductor devices and methods of manufacture|
    WO2002061842A1|2001-01-31|2002-08-08|Matsushita Electric Industrial Co., Ltd.|Film cristallin a semi-conducteurs|
    US6797602B1|2001-02-09|2004-09-28|Advanced Micro Devices, Inc.|Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts|
    US6551885B1|2001-02-09|2003-04-22|Advanced Micro Devices, Inc.|Low temperature process for a thin film transistor|
    US6787424B1|2001-02-09|2004-09-07|Advanced Micro Devices, Inc.|Fully depleted SOI transistor with elevated source and drain|
    EP1421607A2|2001-02-12|2004-05-26|ASM America, Inc.|Improved process for deposition of semiconductor films|
    US6821852B2|2001-02-13|2004-11-23|Micron Technology, Inc.|Dual doped gates|
    KR100393216B1|2001-02-19|2003-07-31|삼성전자주식회사|엘디디 구조를 갖는 모오스 트랜지스터의 제조방법|
    US6432754B1|2001-02-20|2002-08-13|International Business Machines Corporation|Double SOI device with recess etch and epitaxy|
    US6534373B1|2001-03-26|2003-03-18|Advanced Micro Devices, Inc.|MOS transistor with reduced floating body effect|
    JP3940565B2|2001-03-29|2007-07-04|株式会社東芝|半導体装置及びその製造方法|
    JP2002299454A|2001-04-02|2002-10-11|Toshiba Corp|論理回路設計方法、論理回路設計装置及び論理回路マッピング方法|
    US6576535B2|2001-04-11|2003-06-10|Texas Instruments Incorporated|Carbon doped epitaxial layer for high speed CB-CMOS|
    US6620671B1|2001-05-01|2003-09-16|Advanced Micro Devices, Inc.|Method of fabricating transistor having a single crystalline gate conductor|
    US6693333B1|2001-05-01|2004-02-17|Advanced Micro Devices, Inc.|Semiconductor-on-insulator circuit with multiple work functions|
    US6586817B1|2001-05-18|2003-07-01|Sun Microsystems, Inc.|Device including a resistive path to introduce an equivalent RC circuit|
    US6489224B1|2001-05-31|2002-12-03|Sun Microsystems, Inc.|Method for engineering the threshold voltage of a device using buried wells|
    US6822297B2|2001-06-07|2004-11-23|Texas Instruments Incorporated|Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness|
    US6500739B1|2001-06-14|2002-12-31|Taiwan Semiconductor Manufacturing Company|Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect|
    US6358806B1|2001-06-29|2002-03-19|Lsi Logic Corporation|Silicon carbide CMOS channel|
    JP4035354B2|2001-07-11|2008-01-23|富士通株式会社|電子回路設計方法及び装置、コンピュータプログラム及び記憶媒体|
    US6444551B1|2001-07-23|2002-09-03|Taiwan Semiconductor Manufacturing Company|N-type buried layer drive-in recipe to reduce pits over buried antimony layer|
    CN1265467C|2001-09-14|2006-07-19|松下电器产业株式会社|半导体装置|
    EP1428262A2|2001-09-21|2004-06-16|Amberwave Systems Corporation|Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same|
    AU2002341803A1|2001-09-24|2003-04-07|Amberwave Systems Corporation|Rf circuits including transistors having strained material layers|
    US6751519B1|2001-10-25|2004-06-15|Kla-Tencor Technologies Corporation|Methods and systems for predicting IC chip yield|
    US20050250289A1|2002-10-30|2005-11-10|Babcock Jeffrey A|Control of dopant diffusion from buried layers in bipolar integrated circuits|
    US6521470B1|2001-10-31|2003-02-18|United Microelectronics Corp.|Method of measuring thickness of epitaxial layer|
    US6770521B2|2001-11-30|2004-08-03|Texas Instruments Incorporated|Method of making multiple work function gates by implanting metals with metallic alloying additives|
    US6760900B2|2001-12-03|2004-07-06|Anadigics Inc.|Integrated circuits with scalable design|
    ITTO20011129A1|2001-12-04|2003-06-04|Infm Istituto Naz Per La Fisi|Metodo per la soppressione della diffusione anomala transiente di droganti in silicio.|
    US6849528B2|2001-12-12|2005-02-01|Texas Instruments Incorporated|Fabrication of ultra shallow junctions from a solid source with fluorine implantation|
    US7013359B1|2001-12-21|2006-03-14|Cypress Semiconductor Corporation|High speed memory interface system and method|
    US6662350B2|2002-01-28|2003-12-09|International Business Machines Corporation|FinFET layout generation|
    US20030141033A1|2002-01-31|2003-07-31|Tht Presses Inc.|Semi-solid molding method|
    US7919791B2|2002-03-25|2011-04-05|Cree, Inc.|Doped group III-V nitride materials, and microelectronic devices and device precursor structures comprising same|
    WO2003083951A1|2002-03-28|2003-10-09|Advanced Micro Devices, Inc.|Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same|
    DE10214066B4|2002-03-28|2007-02-01|Advanced Micro Devices, Inc., Sunnyvale|Halbleiterbauelement mit retrogradem Dotierprofil in einem Kanalgebiet und Verfahren zur Herstellung desselben|
    US6762469B2|2002-04-19|2004-07-13|International Business Machines Corporation|High performance CMOS device structure with mid-gap metal gate|
    US6957163B2|2002-04-24|2005-10-18|Yoshiyuki Ando|Integrated circuits having post-silicon adjustment control|
    KR100410574B1|2002-05-18|2003-12-18|주식회사 하이닉스반도체|데카보렌 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법|
    KR100414736B1|2002-05-20|2004-01-13|주식회사 하이닉스반도체|반도체소자의 트랜지스터 형성방법|
    US6893947B2|2002-06-25|2005-05-17|Freescale Semiconductor, Inc.|Advanced RF enhancement-mode FETs with improved gate properties|
    US7673273B2|2002-07-08|2010-03-02|Tier Logic, Inc.|MPGA products based on a prototype FPGA|
    US6849492B2|2002-07-08|2005-02-01|Micron Technology, Inc.|Method for forming standard voltage threshold and low voltage threshold MOSFET devices|
    US6743291B2|2002-07-09|2004-06-01|Chartered Semiconductor Manufacturing Ltd.|Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth|
    JP4463482B2|2002-07-11|2010-05-19|パナソニック株式会社|Ｍｉｓｆｅｔ及びその製造方法|
    US6869854B2|2002-07-18|2005-03-22|International Business Machines Corporation|Diffused extrinsic base and method for fabrication|
    JP4020730B2|2002-08-26|2007-12-12|シャープ株式会社|半導体装置およびその製造方法|
    KR100464935B1|2002-09-17|2005-01-05|주식회사 하이닉스반도체|불화붕소화합물 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법|
    JP2004119513A|2002-09-24|2004-04-15|Toshiba Corp|半導体装置及びその製造方法|
    US7226843B2|2002-09-30|2007-06-05|Intel Corporation|Indium-boron dual halo MOSFET|
    US6743684B2|2002-10-11|2004-06-01|Texas Instruments Incorporated|Method to produce localized halo for MOS transistor|
    US6864135B2|2002-10-31|2005-03-08|Freescale Semiconductor, Inc.|Semiconductor fabrication process using transistor spacers of differing widths|
    DE10251308B4|2002-11-04|2007-01-18|Advanced Micro Devices, Inc., Sunnyvale|Integrierte geschaltete Kondensatorschaltung und Verfahren|
    US6660605B1|2002-11-12|2003-12-09|Texas Instruments Incorporated|Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss|
    JP3769262B2|2002-12-20|2006-04-19|株式会社東芝|ウェーハ平坦度評価方法、その評価方法を実行するウェーハ平坦度評価装置、その評価方法を用いたウェーハの製造方法、その評価方法を用いたウェーハ品質保証方法、その評価方法を用いた半導体デバイスの製造方法、およびその評価方法によって評価されたウェーハを用いた半導体デバイスの製造方法|
    KR100486609B1|2002-12-30|2005-05-03|주식회사 하이닉스반도체|이중 도핑구조의 초박형 에피채널 피모스트랜지스터 및그의 제조 방법|
    EP1579352A2|2003-01-02|2005-09-28|PDF Solutions, Inc.|Yield improvement|
    US6963090B2|2003-01-09|2005-11-08|Freescale Semiconductor, Inc.|Enhancement mode metal-oxide-semiconductor field effect transistor|
    KR100499159B1|2003-02-28|2005-07-01|삼성전자주식회사|리세스 채널을 갖는 반도체장치 및 그 제조방법|
    US20040175893A1|2003-03-07|2004-09-09|Applied Materials, Inc.|Apparatuses and methods for forming a substantially facet-free epitaxial film|
    KR100989006B1|2003-03-13|2010-10-20|크로스텍 캐피탈, 엘엘씨|씨모스 이미지센서의 제조방법|
    WO2004084310A1|2003-03-19|2004-09-30|Siced Electronics Development Gmbh & Co. Kg|Halbleiteraufbau mit hoch dotiertem kanalleitungsgebiet und verfahren zur herstellung eines halbleiteraufbaus|
    SE0300924D0|2003-03-28|2003-03-28|Infineon Technologies Wireless|A method to provide a triple well in an epitaxially based CMOS or BiCMOS process|
    US7294877B2|2003-03-28|2007-11-13|Nantero, Inc.|Nanotube-on-gate FET structures and applications|
    KR20050119662A|2003-03-28|2005-12-21|코닌클리즈케 필립스 일렉트로닉스 엔.브이.|Ｎ-도핑된 규소 층의 에피택시얼 증착 방법|
    EP1612861B1|2003-04-10|2018-10-03|Fujitsu Semiconductor Limited|Semiconductor device and its manufacturing method|
    JP4469139B2|2003-04-28|2010-05-26|シャープ株式会社|化合物半導体ｆｅｔ|
    US7176137B2|2003-05-09|2007-02-13|Taiwan Semiconductor Manufacturing Co., Ltd.|Method for multiple spacer width control|
    US6794235B1|2003-06-05|2004-09-21|Texas Instruments Incorporated|Method of manufacturing a semiconductor device having a localized halo implant|
    JP4472633B2|2003-06-10|2010-06-02|富士通マイクロエレクトロニクス株式会社|半導体集積回路装置および半導体集積回路装置の製造方法|
    US6808994B1|2003-06-17|2004-10-26|Micron Technology, Inc.|Transistor structures and processes for forming same|
    KR100476940B1|2003-06-20|2005-03-16|삼성전자주식회사|기판으로부터 수직으로 연장된 게이트 채널을 갖는디램기억 셀 및 그 제조방법|
    US7260562B2|2003-06-30|2007-08-21|Intel Corporation|Solutions for constraint satisfaction problems requiring multiple constraints|
    US7036098B2|2003-06-30|2006-04-25|Sun Microsystems, Inc.|On-chip signal state duration measurement and adjustment|
    EP1647046A2|2003-07-23|2006-04-19|ASM America, Inc.|DEPOSITION OF SiGE ON SILICON-ON-INSULATOR STRUCTURES AND BULK SUBSTRATES|
    US7521323B2|2003-09-03|2009-04-21|Nxp B.V.|Method of fabricating a double gate field effect transistor device, and such a double gate field effect transistor device|
    US6930007B2|2003-09-15|2005-08-16|Texas Instruments Incorporated|Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance|
    EP1519421A1|2003-09-25|2005-03-30|Interuniversitair Microelektronica Centrum Vzw|Multiple gate semiconductor device and method for forming same|
    JP4186774B2|2003-09-25|2008-11-26|沖電気工業株式会社|情報抽出装置，情報抽出方法，およびプログラム|
    US7127687B1|2003-10-14|2006-10-24|Sun Microsystems, Inc.|Method and apparatus for determining transistor sizes|
    US7109099B2|2003-10-17|2006-09-19|Chartered Semiconductor Manufacturing Ltd.|End of range secondary defect engineering using substitutional carbon doping|
    US7274076B2|2003-10-20|2007-09-25|Micron Technology, Inc.|Threshold voltage adjustment for long channel transistors|
    US7141468B2|2003-10-27|2006-11-28|Texas Instruments Incorporated|Application of different isolation schemes for logic and embedded memory|
    US7057216B2|2003-10-31|2006-06-06|International Business Machines Corporation|High mobility heterojunction complementary field effect transistors and methods thereof|
    US7132323B2|2003-11-14|2006-11-07|International Business Machines Corporation|CMOS well structure and method of forming the same|
    US6927137B2|2003-12-01|2005-08-09|Texas Instruments Incorporated|Forming a retrograde well in a transistor to enhance performance of the transistor|
    US7279743B2|2003-12-02|2007-10-09|Vishay-Siliconix|Closed cell trench metal-oxide-semiconductor field effect transistor|
    CN100477092C|2003-12-18|2009-04-08|Nxp股份有限公司|利用固相外延再生长的具有降低的结泄漏的半导体衬底及其制作方法|
    US7045456B2|2003-12-22|2006-05-16|Texas Instruments Incorporated|MOS transistor gates with thin lower metal silicide and methods for making the same|
    US7111185B2|2003-12-23|2006-09-19|Micron Technology, Inc.|Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit|
    US7015741B2|2003-12-23|2006-03-21|Intel Corporation|Adaptive body bias for clock skew compensation|
    DE10360874B4|2003-12-23|2009-06-04|Infineon Technologies Ag|Feldeffekttransistor mit Heteroschichtstruktur sowie zugehöriges Herstellungsverfahren|
    US7005333B2|2003-12-30|2006-02-28|Infineon Technologies Ag|Transistor with silicon and carbon layer in the channel region|
    KR100597460B1|2003-12-31|2006-07-05|동부일렉트로닉스 주식회사|반도체 소자의 트랜지스터 및제조방법|
    US7205758B1|2004-02-02|2007-04-17|Transmeta Corporation|Systems and methods for adjusting threshold voltage|
    US6917237B1|2004-03-02|2005-07-12|Intel Corporation|Temperature dependent regulation of threshold voltage|
    US7089515B2|2004-03-09|2006-08-08|International Business Machines Corporation|Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power|
    US7176530B1|2004-03-17|2007-02-13|National Semiconductor Corporation|Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor|
    US7089513B2|2004-03-19|2006-08-08|International Business Machines Corporation|Integrated circuit design for signal integrity, avoiding well proximity effects|
    KR100626372B1|2004-04-09|2006-09-20|삼성전자주식회사|전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법|
    US7564105B2|2004-04-24|2009-07-21|Taiwan Semiconductor Manufacturing Co., Ltd.|Quasi-plannar and FinFET-like transistors on bulk silicon|
    US7402207B1|2004-05-05|2008-07-22|Advanced Micro Devices, Inc.|Method and apparatus for controlling the thickness of a selective epitaxial growth layer|
    JP4795653B2|2004-06-15|2011-10-19|ルネサスエレクトロニクス株式会社|半導体記憶装置|
    US7562233B1|2004-06-22|2009-07-14|Transmeta Corporation|Adaptive control of operating and body bias voltages|
    US7221021B2|2004-06-25|2007-05-22|Taiwan Semiconductor Manufacturing Co., Ltd.|Method of forming high voltage devices with retrograde well|
    US7491988B2|2004-06-28|2009-02-17|Intel Corporation|Transistors with increased mobility in the channel zone and method of fabrication|
    US7169675B2|2004-07-07|2007-01-30|Chartered Semiconductor Manufacturing, Ltd|Material architecture for the fabrication of low temperature transistor|
    US7462908B2|2004-07-14|2008-12-09|International Rectifier Corporation|Dynamic deep depletion field effect transistor|
    US7186622B2|2004-07-15|2007-03-06|Infineon Technologies Ag|Formation of active area using semiconductor growth process without STI integration|
    US7846822B2|2004-07-30|2010-12-07|The Board Of Trustees Of The University Of Illinois|Methods for controlling dopant concentration and activation in semiconductor structures|
    US7119381B2|2004-07-30|2006-10-10|Freescale Semiconductor, Inc.|Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices|
    US7002214B1|2004-07-30|2006-02-21|International Business Machines Corporation|Ultra-thin body super-steep retrograde well FET devices|
    US7071103B2|2004-07-30|2006-07-04|International Business Machines Corporation|Chemical treatment to retard diffusion in a semiconductor overlayer|
    DE102004037087A1|2004-07-30|2006-03-23|Advanced Micro Devices, Inc., Sunnyvale|Selbstvorspannende Transistorstruktur und SRAM-Zellen mit weniger als sechs Transistoren|
    JP4469677B2|2004-08-04|2010-05-26|パナソニック株式会社|半導体装置およびその製造方法|
    JP4664631B2|2004-08-05|2011-04-06|株式会社東芝|半導体装置及びその製造方法|
    US7189627B2|2004-08-19|2007-03-13|Texas Instruments Incorporated|Method to improve SRAM performance and stability|
    US8106481B2|2004-09-03|2012-01-31|Rao G R Mohan|Semiconductor devices with graded dopant regions|
    US20060049464A1|2004-09-03|2006-03-09|Rao G R Mohan|Semiconductor devices with graded dopant regions|
    JP5244390B2|2004-09-17|2013-07-24|カリフォルニアインスティテュートオブテクノロジー|Ｓｏｉウェーハで作ったバック照明式ｃｍｏｓ撮像素子（ｉｍａｇｅｒ）の製造方法|
    JP4540438B2|2004-09-27|2010-09-08|富士通セミコンダクター株式会社|半導体装置及びその製造方法|
    US7332439B2|2004-09-29|2008-02-19|Intel Corporation|Metal gate transistors with epitaxial source and drain regions|
    US7095094B2|2004-09-29|2006-08-22|Agere Systems Inc.|Multiple doping level bipolar junctions transistors and method for forming|
    US7268049B2|2004-09-30|2007-09-11|International Business Machines Corporation|Structure and method for manufacturing MOSFET with super-steep retrograded island|
    KR100652381B1|2004-10-28|2006-12-01|삼성전자주식회사|다수의 나노 와이어 채널을 구비한 멀티 브릿지 채널 전계효과 트랜지스터 및 그 제조방법|
    US7226833B2|2004-10-29|2007-06-05|Freescale Semiconductor, Inc.|Semiconductor device structure and method therefor|
    DE102004053761A1|2004-11-08|2006-05-18|Robert Bosch Gmbh|Halbleitereinrichtung und Verfahren für deren Herstellung|
    US7402872B2|2004-11-18|2008-07-22|Intel Corporation|Method for forming an integrated circuit|
    US20060113591A1|2004-11-30|2006-06-01|Chih-Hao Wan|High performance CMOS devices and methods for making same|
    US7105399B1|2004-12-07|2006-09-12|Advanced Micro Devices, Inc.|Selective epitaxial growth for tunable channel thickness|
    KR100642407B1|2004-12-29|2006-11-08|주식회사 하이닉스반도체|반도체 메모리 소자의 셀 트랜지스터 제조 방법|
    KR100613294B1|2004-12-30|2006-08-21|동부일렉트로닉스 주식회사|단채널 효과가 개선되는 모스 전계효과 트랜지스터 및 그제조 방법|
    US20060154428A1|2005-01-12|2006-07-13|International Business Machines Corporation|Increasing doping of well compensating dopant region according to increasing gate length|
    US7193279B2|2005-01-18|2007-03-20|Intel Corporation|Non-planar MOS structure with a strained channel region|
    US20060166417A1|2005-01-27|2006-07-27|International Business Machines Corporation|Transistor having high mobility channel and methods|
    US7531436B2|2005-02-14|2009-05-12|Texas Instruments Incorporated|Highly conductive shallow junction formation|
    US7404114B2|2005-02-15|2008-07-22|International Business Machines Corporation|System and method for balancing delay of signal communication paths through well voltage adjustment|
    US20060203581A1|2005-03-10|2006-09-14|Joshi Rajiv V|Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions|
    US7407850B2|2005-03-29|2008-08-05|Texas Instruments Incorporated|N+ poly on high-k dielectric for semiconductor devices|
    JP4493536B2|2005-03-30|2010-06-30|富士通マイクロエレクトロニクス株式会社|半導体装置及びその製造方法|
    US7338817B2|2005-03-31|2008-03-04|Intel Corporation|Body bias compensation for aged transistors|
    US7170120B2|2005-03-31|2007-01-30|Intel Corporation|Carbon nanotube energy well field effect transistor|
    US7271079B2|2005-04-06|2007-09-18|International Business Machines Corporation|Method of doping a gate electrode of a field effect transistor|
    US7605429B2|2005-04-15|2009-10-20|International Business Machines Corporation|Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement|
    JP4551811B2|2005-04-27|2010-09-29|株式会社東芝|半導体装置の製造方法|
    US7446380B2|2005-04-29|2008-11-04|International Business Machines Corporation|Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS|
    US7441211B1|2005-05-06|2008-10-21|Blaze Dfm, Inc.|Gate-length biasing for digital circuit optimization|
    US20060273379A1|2005-06-06|2006-12-07|Alpha & Omega Semiconductor, Ltd.|MOSFET using gate work function engineering for switching applications|
    US7354833B2|2005-06-10|2008-04-08|Taiwan Semiconductor Manufacturing Co., Ltd.|Method for improving threshold voltage stability of a MOS device|
    US20070040222A1|2005-06-15|2007-02-22|Benjamin Van Camp|Method and apparatus for improved ESD performance|
    US7190050B2|2005-07-01|2007-03-13|Synopsys, Inc.|Integrated circuit on corrugated substrate|
    JP4800700B2|2005-08-01|2011-10-26|ルネサスエレクトロニクス株式会社|半導体装置およびそれを用いた半導体集積回路|
    US7409651B2|2005-08-05|2008-08-05|International Business Machines Corporation|Automated migration of analog and mixed-signal VLSI design|
    US7314794B2|2005-08-08|2008-01-01|International Business Machines Corporation|Low-cost high-performance planar back-gate CMOS|
    US7307471B2|2005-08-26|2007-12-11|Texas Instruments Incorporated|Adaptive voltage control and body bias for performance and energy optimization|
    US7838369B2|2005-08-29|2010-11-23|National Semiconductor Corporation|Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications|
    JP2007073578A|2005-09-05|2007-03-22|Matsushita Electric Ind Co Ltd|半導体装置及びその製造方法|
    JP2007103863A|2005-10-07|2007-04-19|Nec Electronics Corp|半導体デバイス|
    US7569873B2|2005-10-28|2009-08-04|Dsm Solutions, Inc.|Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys|
    US7465642B2|2005-10-28|2008-12-16|International Business Machines Corporation|Methods for forming semiconductor structures with buried isolation collars|
    JP4256381B2|2005-11-09|2009-04-22|株式会社東芝|半導体装置|
    US8255843B2|2005-11-14|2012-08-28|Taiwan Semiconductor Manufacturing Company, Ltd.|Method of manufacturing strained-silicon semiconductor device|
    US7462538B2|2005-11-15|2008-12-09|Infineon Technologies Ag|Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials|
    US7759206B2|2005-11-29|2010-07-20|International Business Machines Corporation|Methods of forming semiconductor devices using embedded L-shape spacers|
    CN101313395B|2005-12-09|2013-03-27|山米奎普公司|通过植入碳团簇制造半导体装置的系统和方法|
    JP2009521801A|2005-12-22|2009-06-04|エーエスエムアメリカインコーポレイテッド|ドープされた半導体物質のエピタキシャル堆積|
    KR100657130B1|2005-12-27|2006-12-13|동부일렉트로닉스 주식회사|반도체 소자 및 그 제조 방법|
    US7633134B2|2005-12-29|2009-12-15|Jaroslav Hynecek|Stratified photodiode for high resolution CMOS image sensor implemented with STI technology|
    US7485536B2|2005-12-30|2009-02-03|Intel Corporation|Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers|
    JP5145691B2|2006-02-23|2013-02-20|セイコーエプソン株式会社|半導体装置|
    US20070212861A1|2006-03-07|2007-09-13|International Business Machines Corporation|Laser surface annealing of antimony doped amorphized semiconductor region|
    US7380225B2|2006-03-14|2008-05-27|International Business Machines Corporation|Method and computer program for efficient cell failure rate estimation in cell arrays|
    JP5283827B2|2006-03-30|2013-09-04|富士通セミコンダクター株式会社|半導体装置の製造方法|
    US7351637B2|2006-04-10|2008-04-01|General Electric Company|Semiconductor transistors having reduced channel widths and methods of fabricating same|
    US7681628B2|2006-04-12|2010-03-23|International Business Machines Corporation|Dynamic control of back gate bias in a FinFET SRAM cell|
    US7348629B2|2006-04-20|2008-03-25|International Business Machines Corporation|Metal gated ultra short MOSFET devices|
    US20070257315A1|2006-05-04|2007-11-08|International Business Machines Corporation|Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors|
    KR100703986B1|2006-05-22|2007-04-09|삼성전자주식회사|동작 특성과 플리커 노이즈 특성이 향상된 아날로그트랜지스터를 구비하는 반도체 소자 및 그 제조 방법|
    WO2007136102A1|2006-05-23|2007-11-29|Nec Corporation|半導体装置、集積回路、及び半導体装置の製造方法|
    US7384835B2|2006-05-25|2008-06-10|International Business Machines Corporation|Metal oxide field effect transistor with a sharp halo and a method of forming the transistor|
    US7941776B2|2006-05-26|2011-05-10|Open-Silicon Inc.|Method of IC design optimization via creation of design-specific cells from post-layout patterns|
    JP5073968B2|2006-05-31|2012-11-14|住友化学株式会社|化合物半導体エピタキシャル基板およびその製造方法|
    US7503020B2|2006-06-19|2009-03-10|International Business Machines Corporation|IC layout optimization to improve yield|
    US7469164B2|2006-06-26|2008-12-23|Nanometrics Incorporated|Method and apparatus for process control with in-die metrology|
    US7538412B2|2006-06-30|2009-05-26|Infineon Technologies Austria Ag|Semiconductor device with a field stop zone|
    JP4271210B2|2006-06-30|2009-06-03|株式会社東芝|電界効果トランジスタ、集積回路素子、及びそれらの製造方法|
    GB0613289D0|2006-07-04|2006-08-16|Imagination Tech Ltd|Synchronisation of execution threads on a multi-threaded processor|
    DE112007001814T5|2006-07-31|2009-06-04|Applied Materials, Inc., Santa Clara|Verfahren zum Bilden kohlenstoffhaltiger Siliziumepitaxieschichten|
    US7496862B2|2006-08-29|2009-02-24|Taiwan Semiconductor Manufacturing Co., Ltd.|Method for automatically modifying integrated circuit layout|
    US8063466B2|2006-09-07|2011-11-22|Sumco Corporation|Semiconductor substrate for solid-state image sensing device as well as solid-state image sensing device and method for producing the same|
    US20080067589A1|2006-09-20|2008-03-20|Akira Ito|Transistor having reduced channel dopant fluctuation|
    US7683442B1|2006-09-29|2010-03-23|Burr James B|Raised source/drain with super steep retrograde channel|
    JP2008085253A|2006-09-29|2008-04-10|Oki Electric Ind Co Ltd|半導体装置の製造方法|
    US7642150B2|2006-11-08|2010-01-05|Varian Semiconductor Equipment Associates, Inc.|Techniques for forming shallow junctions|
    US7750374B2|2006-11-14|2010-07-06|Freescale Semiconductor, Inc|Process for forming an electronic device including a transistor having a metal gate electrode|
    US7696000B2|2006-12-01|2010-04-13|International Business Machines Corporation|Low defect Si:C layer with retrograde carbon profile|
    US7741200B2|2006-12-01|2010-06-22|Applied Materials, Inc.|Formation and treatment of epitaxial layer containing silicon and carbon|
    US7821066B2|2006-12-08|2010-10-26|Michael Lebby|Multilayered BOX in FDSOI MOSFETS|
    US7897495B2|2006-12-12|2011-03-01|Applied Materials, Inc.|Formation of epitaxial layer containing silicon and carbon|
    US8217423B2|2007-01-04|2012-07-10|International Business Machines Corporation|Structure and method for mobility enhanced MOSFETs with unalloyed silicide|
    US7416605B2|2007-01-08|2008-08-26|Freescale Semiconductor, Inc.|Anneal of epitaxial layer in a semiconductor device|
    KR100819562B1|2007-01-15|2008-04-08|삼성전자주식회사|레트로그레이드 영역을 갖는 반도체소자 및 그 제조방법|
    US20080169516A1|2007-01-17|2008-07-17|Taiwan Semiconductor Manufacturing Co., Ltd.|Semiconductor devices for alleviating well proximity effects|
    KR100862113B1|2007-01-22|2008-10-09|삼성전자주식회사|공정 변화에 대한 정보를 이용하여 공급전압/공급주파수를제어할 수 있는 장치와 방법|
    US7644377B1|2007-01-31|2010-01-05|Hewlett-Packard Development Company, L.P.|Generating a configuration of a system that satisfies constraints contained in models|
    KR100836767B1|2007-02-05|2008-06-10|삼성전자주식회사|높은 전압을 제어하는 모스 트랜지스터를 포함하는 반도체소자 및 그 형성 방법|
    KR101312259B1|2007-02-09|2013-09-25|삼성전자주식회사|박막 트랜지스터 및 그 제조방법|
    US7781288B2|2007-02-21|2010-08-24|International Business Machines Corporation|Semiconductor structure including gate electrode having laterally variable work function|
    US7818702B2|2007-02-28|2010-10-19|International Business Machines Corporation|Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates|
    US7831873B1|2007-03-07|2010-11-09|Xilinx, Inc.|Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits|
    US7602017B2|2007-03-13|2009-10-13|Fairchild Semiconductor Corporation|Short channel LV, MV, and HV CMOS devices|
    US7598142B2|2007-03-15|2009-10-06|Pushkar Ranade|CMOS device with dual-epi channels and self-aligned contacts|
    JP2008235568A|2007-03-20|2008-10-02|Toshiba Corp|半導体装置およびその製造方法|
    US8394687B2|2007-03-30|2013-03-12|Intel Corporation|Ultra-abrupt semiconductor junction profile|
    US7496867B2|2007-04-02|2009-02-24|Lsi Corporation|Cell library management for power optimization|
    US7737472B2|2007-04-05|2010-06-15|Panasonic Corporation|Semiconductor integrated circuit device|
    CN101030602B|2007-04-06|2012-03-21|上海集成电路研发中心有限公司|一种可减小短沟道效应的mos晶体管及其制作方法|
    US7692220B2|2007-05-01|2010-04-06|Suvolta, Inc.|Semiconductor device storage cell structure, method of operation, and method of manufacture|
    US7586322B1|2007-05-02|2009-09-08|Altera Corporation|Test structure and method for measuring mismatch and well proximity effects|
    US20080272409A1|2007-05-03|2008-11-06|Dsm Solutions, Inc.;|JFET Having a Step Channel Doping Profile and Method of Fabrication|
    US20080315206A1|2007-06-19|2008-12-25|Herner S Brad|Highly Scalable Thin Film Transistor|
    US7759714B2|2007-06-26|2010-07-20|Hitachi, Ltd.|Semiconductor device|
    CN101720463B|2007-06-28|2012-09-26|萨格昂泰克以色列有限公司|基于设计规则和用户约束的半导体布图修正方法|
    US7651920B2|2007-06-29|2010-01-26|Infineon Technologies Ag|Noise reduction in semiconductor device using counter-doping|
    KR100934789B1|2007-08-29|2009-12-31|주식회사 동부하이텍|반도체 소자 및 그 제조 방법|
    US7895546B2|2007-09-04|2011-02-22|Lsi Corporation|Statistical design closure|
    JP2009064860A|2007-09-05|2009-03-26|Renesas Technology Corp|半導体装置|
    US7795677B2|2007-09-05|2010-09-14|International Business Machines Corporation|Nanowire field-effect transistors|
    JP5242103B2|2007-09-07|2013-07-24|ルネサスエレクトロニクス株式会社|半導体集積回路のレイアウト方法|
    US7675317B2|2007-09-14|2010-03-09|Altera Corporation|Integrated circuits with adjustable body bias and power supply circuitry|
    US7926018B2|2007-09-25|2011-04-12|Synopsys, Inc.|Method and apparatus for generating a layout for a transistor|
    US8053340B2|2007-09-27|2011-11-08|National University Of Singapore|Method for fabricating semiconductor devices with reduced junction diffusion|
    US7704844B2|2007-10-04|2010-04-27|International Business Machines Corporation|High performance MOSFET|
    US8329564B2|2007-10-26|2012-12-11|International Business Machines Corporation|Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method|
    US7948008B2|2007-10-26|2011-05-24|Micron Technology, Inc.|Floating body field-effect transistors, and methods of forming floating body field-effect transistors|
    DE102007052220B4|2007-10-31|2015-04-09|Globalfoundries Inc.|Verfahren zur Dotierstoffprofileinstellung für MOS-Bauelemente durch Anpassen einer Abstandshalterbreite vor der Implantation|
    JP5528667B2|2007-11-28|2014-06-25|ルネサスエレクトロニクス株式会社|半導体装置および半導体装置の制御方法|
    US7994573B2|2007-12-14|2011-08-09|Fairchild Semiconductor Corporation|Structure and method for forming power devices with carbon-containing region|
    US7745270B2|2007-12-28|2010-06-29|Intel Corporation|Tri-gate patterning using dual layer gate stack|
    US7622341B2|2008-01-16|2009-11-24|International Business Machines Corporation|Sige channel epitaxial development for high-k PFET manufacturability|
    DE102008006961A1|2008-01-31|2009-08-27|Advanced Micro Devices, Inc., Sunnyvale|Verfahren zum Erzeugen eines verformten Kanalgebiets in einem Transistor durch eine tiefe Implantation einer verformungsinduzierenden Sorte unter das Kanalgebiet|
    CN102007584B|2008-02-14|2013-01-16|马克斯半导体股份有限公司|半导体装置结构及其相关工艺|
    FR2928028B1|2008-02-27|2011-07-15|St Microelectronics Crolles 2|Procede de fabrication d'un dispositif semi-conducteur a grille enterree et circuit integre correspondant.|
    US7867835B2|2008-02-29|2011-01-11|Chartered Semiconductor Manufacturing Ltd.|Integrated circuit system for suppressing short channel effects|
    US7750682B2|2008-03-10|2010-07-06|International Business Machines Corporation|CMOS back-gated keeper technique|
    US7968440B2|2008-03-19|2011-06-28|The Board Of Trustees Of The University Of Illinois|Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering|
    KR101502033B1|2008-04-11|2015-03-12|삼성전자주식회사|Ａｄｃ의 전류 제어 회로 및 방법|
    EP2112686B1|2008-04-22|2011-10-12|Imec|Method for fabricating a dual workfunction semiconductor device made thereof|
    JP2009267159A|2008-04-25|2009-11-12|ＳｕｍｃｏＴｅｃｈｘｉｖ株式会社|半導体ウェーハの製造装置及び方法|
    JP5173582B2|2008-05-19|2013-04-03|株式会社東芝|半導体装置|
    US8225255B2|2008-05-21|2012-07-17|International Business Machines Corporation|Placement and optimization of process dummy cells|
    DE102008026213B3|2008-05-30|2009-09-24|Advanced Micro Devices, Inc., Sunnyvale|Verfahren zur Durchlassstromerhöhung in Transistoren durch asymmetrische Amorphisierungsimplantation|
    FR2932609B1|2008-06-11|2010-12-24|Commissariat Energie Atomique|Transistor soi avec plan de masse et grille auto-alignes et oxyde enterre d'epaisseur variable|
    US8471307B2|2008-06-13|2013-06-25|Texas Instruments Incorporated|In-situ carbon doped e-SiGeCB stack for MOS transistor|
    US8129797B2|2008-06-18|2012-03-06|International Business Machines Corporation|Work function engineering for eDRAM MOSFETs|
    US20100012988A1|2008-07-21|2010-01-21|Advanced Micro Devices, Inc.|Metal oxide semiconductor devices having implanted carbon diffusion retardation layers and methods for fabricating the same|
    US7951678B2|2008-08-12|2011-05-31|International Business Machines Corporation|Metal-gate high-k reference structure|
    DE102008045037B4|2008-08-29|2010-12-30|Advanced Micro Devices, Inc., Sunnyvale|Statischer RAM-Zellenaufbau und Mehrfachkontaktschema zum Anschluss von Doppelkanaltransistoren|
    US7927943B2|2008-09-12|2011-04-19|Taiwan Semiconductor Manufacturing Company, Ltd.|Method for tuning a work function of high-k metal gate devices|
    CN102165561A|2008-09-25|2011-08-24|应用材料股份有限公司|使用十八硼烷自我非晶体化注入物的无缺陷接点形成|
    US20100100856A1|2008-10-17|2010-04-22|Anurag Mittal|Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics|
    JP5519140B2|2008-10-28|2014-06-11|ルネサスエレクトロニクス株式会社|半導体装置及びその製造方法|
    US7824986B2|2008-11-05|2010-11-02|Micron Technology, Inc.|Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions|
    US8103983B2|2008-11-12|2012-01-24|International Business Machines Corporation|Electrically-driven optical proximity correction to compensate for non-optical effects|
    US8170857B2|2008-11-26|2012-05-01|International Business Machines Corporation|In-situ design method and system for improved memory yield|
    DE102008059501B4|2008-11-28|2012-09-20|Advanced Micro Devices, Inc.|Technik zur Verbesserung des Dotierstoffprofils und der Kanalleitfähigkeit durch Millisekunden-Ausheizprozesse|
    US20100148153A1|2008-12-16|2010-06-17|Hudait Mantu K|Group III-V devices with delta-doped layer under channel region|
    US7960238B2|2008-12-29|2011-06-14|Texas Instruments Incorporated|Multiple indium implant methods and devices and integrated circuits therefrom|
    DE102008063427B4|2008-12-31|2013-02-28|Advanced Micro Devices, Inc.|Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung|
    JP5350815B2|2009-01-22|2013-11-27|株式会社東芝|半導体装置|
    US7829402B2|2009-02-10|2010-11-09|General Electric Company|MOSFET devices and methods of making|
    US20100207182A1|2009-02-13|2010-08-19|International Business Machines Corporation|Implementing Variable Threshold Voltage Transistors|
    US8048791B2|2009-02-23|2011-11-01|Globalfoundries Inc.|Method of forming a semiconductor device|
    US8163619B2|2009-03-27|2012-04-24|National Semiconductor Corporation|Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone|
    US8178430B2|2009-04-08|2012-05-15|International Business Machines Corporation|N-type carrier enhancement in semiconductors|
    US8214190B2|2009-04-13|2012-07-03|International Business Machines Corporation|Methodology for correlated memory fail estimations|
    US7943457B2|2009-04-14|2011-05-17|International Business Machines Corporation|Dual metal and dual dielectric integration for metal high-k FETs|
    JP2010258264A|2009-04-27|2010-11-11|Toshiba Corp|半導体集積回路装置およびその設計方法|
    US8183107B2|2009-05-27|2012-05-22|Globalfoundries Inc.|Semiconductor devices with improved local matching and end resistance of RX based resistors|
    US8173499B2|2009-06-12|2012-05-08|Taiwan Semiconductor Manufacturing Co., Ltd.|Method of fabricating a gate stack integration of complementary MOS device|
    US8227307B2|2009-06-24|2012-07-24|International Business Machines Corporation|Method for removing threshold voltage adjusting layer with external acid diffusion process|
    US8236661B2|2009-09-28|2012-08-07|International Business Machines Corporation|Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage|
    WO2011062788A1|2009-11-17|2011-05-26|Suvolta, Inc.|Electronic devices and systems, and methods for making and using the same|
    US8273617B2|2009-09-30|2012-09-25|Suvolta, Inc.|Electronic devices and systems, and methods for making and using the same|
    US20110079861A1|2009-09-30|2011-04-07|Lucian Shifren|Advanced Transistors with Threshold Voltage Set Dopant Structures|
    CN102034865B|2009-09-30|2012-07-04|中国科学院微电子研究所|半导体器件及其制造方法|
    EP2309544B1|2009-10-06|2019-06-12|IMEC vzw|Tunnel field effect transistor with improved subthreshold swing|
    US8552795B2|2009-10-22|2013-10-08|Taiwan Semiconductor Manufacturing Company, Ltd.|Substrate bias control circuit for system on chip|
    US8114761B2|2009-11-30|2012-02-14|Applied Materials, Inc.|Method for doping non-planar transistors|
    US8598003B2|2009-12-21|2013-12-03|Intel Corporation|Semiconductor device having doped epitaxial region and its methods of fabrication|
    TWI404209B|2009-12-31|2013-08-01|Univ Nat Chiao Tung|高電子遷移率電晶體及其製作方法|
    US8343818B2|2010-01-14|2013-01-01|International Business Machines Corporation|Method for forming retrograded well for MOSFET|
    US8697521B2|2010-01-21|2014-04-15|International Business Machines Corporation|Structure and method for making low leakage and low mismatch NMOSFET|
    US8048810B2|2010-01-29|2011-11-01|Taiwan Semiconductor Manufacturing Company, Ltd.|Method for metal gate N/P patterning|
    US8288798B2|2010-02-10|2012-10-16|Taiwan Semiconductor Manufacturing Company, Ltd.|Step doping in extensions of III-V family semiconductor devices|
    US20110212590A1|2010-02-26|2011-09-01|Taiwan Semiconductor Manufacturing Company, Ltd.|High temperature implantation method for stressor formation|
    US8385147B2|2010-03-30|2013-02-26|Silicon Storage Technology, Inc.|Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features|
    US8530286B2|2010-04-12|2013-09-10|Suvolta, Inc.|Low power semiconductor transistor structure and method of fabrication thereof|
    US8176461B1|2010-05-10|2012-05-08|Xilinx, Inc.|Design-specific performance specification based on a yield for programmable integrated circuits|
    US8201122B2|2010-05-25|2012-06-12|International Business Machines Corporation|Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapes|
    JP5614877B2|2010-05-28|2014-10-29|ルネサスエレクトロニクス株式会社|半導体装置の製造方法|
    US8759872B2|2010-06-22|2014-06-24|Suvolta, Inc.|Transistor with threshold voltage set notch and method of fabrication thereof|
    US8373229B2|2010-08-30|2013-02-12|Taiwan Semiconductor Manufacturing Company, Ltd.|Gate controlled bipolar junction transistor on fin-like field effect transistor structure|
    US8361872B2|2010-09-07|2013-01-29|International Business Machines Corporation|High performance low power bulk FET device and method of manufacture|
    JP2012060016A|2010-09-10|2012-03-22|Renesas Electronics Corp|半導体装置の評価方法、評価装置、及びシミュレーション方法|
    US8450169B2|2010-11-29|2013-05-28|International Business Machines Corporation|Replacement metal gate structures providing independent control on work function and gate leakage current|
    US8466473B2|2010-12-06|2013-06-18|International Business Machines Corporation|Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs|
    US8656339B2|2010-12-22|2014-02-18|Advanced Micro Devices, Inc.|Method for analyzing sensitivity and failure probability of a circuit|
    US8299562B2|2011-03-28|2012-10-30|Nanya Technology Corporation|Isolation structure and device structure including the same|
    US8324059B2|2011-04-25|2012-12-04|United Microelectronics Corp.|Method of fabricating a semiconductor structure|
    US8455307B2|2011-05-19|2013-06-04|GlobalFoundries, Inc.|FINFET integrated circuits and methods for their fabrication|CN104282562A|2013-07-03|2015-01-14|中芯国际集成电路制造有限公司|鳍式场效应晶体管及其形成方法|
    US9881993B2|2014-06-27|2018-01-30|Taiwan Semiconductor Manufacturing Company Limited|Method of forming semiconductor structure with horizontal gate all around structure|
    CN106575671A|2014-09-19|2017-04-19|英特尔公司|创建掺杂的子结构以减少微电子晶体管中的泄露的装置和方法|
    US9953836B2|2015-01-28|2018-04-24|Taiwan Semiconductor Manufacturing Co., Ltd.|Barrier layer above anti-punch throughimplant region to improve mobility of channel region of fin field effect transistordevice structure|
    KR102352154B1|2015-03-03|2022-01-17|삼성전자주식회사|집적회로 소자|
    US9385218B1|2015-04-23|2016-07-05|International Business Machines Corporation|Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy|
    US9911806B2|2015-05-22|2018-03-06|Taiwan Semiconductor Manufacturing Company, Ltd.|Solvent-based oxidation on germanium and III-V compound semiconductor materials|
    CN107851664A|2015-09-25|2018-03-27|英特尔公司|用于控制晶体管子鳍状物漏电的技术|
    KR102323943B1|2015-10-21|2021-11-08|삼성전자주식회사|반도체 장치 제조 방법|
    US9960273B2|2015-11-16|2018-05-01|Taiwan Semiconductor Manufacturing Company, Ltd.|Integrated circuit structure with substrate isolation and un-doped channel|
    US9735275B2|2015-12-18|2017-08-15|International Business Machines Corporation|Channel replacement and bimodal doping scheme for bulk finFET threshold voltage modulation with reduced performance penalty|
    US10147651B1|2017-05-12|2018-12-04|International Business Machines Corporation|Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels|
    CN109712934B|2017-10-26|2021-06-22|联华电子股份有限公司|一种制作半导体元件的方法|
    KR101948481B1|2018-04-04|2019-02-14|한국과학기술원|단일 사건 현상과 누적 이온화 현상에 강인한 내방사선 입체 단위 모스펫|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US201161515452P| true| 2011-08-05|2011-08-05||
    [返回顶部]