• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to telecommunications. The purpose of the invention is to improve the accuracy of compensation at a predetermined value of the phase control step. The echo signals caused by the digital transmission signals of the transmitting branch of the differential system (DS) 4, in the receiving branch of DS 4, together with the received digital 4 receive signals, form a mixture of signals. From it, the compensation signals generated by the echo canceller 12 are subtracted from the digital transmission signals at equidistant read moments. These moments are set by 2-Invention relates to telecommunications and can be used in systems of duplex transmission of digital signals. The purpose of the invention is to improve the accuracy of compensation at a given step of phase control. In FIG. 1 shows the structured electrical circuit of the device for performing by means of clock read pulses, the phase position of which is adjusted depending on the magnitude of the distortions of the phase correction (FC) signals. To improve the accuracy of the compensation, the signals of the FC are accumulated to exceed the specified upper threshold or, respectively, lower than the specified lower threshold by summing the accumulated signals of the FC. At the same time, a correction-compensation signal is generated corresponding to the total signal of the FC, which is added to the compensation signal. When the specified upper threshold is exceeded or, respectively, lower than the specified lower threshold, the phase position of the read clock pulses is shifted by one step and the total signal of the PC is erased at the same time. To implement the method, a device is used that contains a transmitting unit 1 consisting of an encoder 2 and a low-pass filter 3, DS 4, readout unit 5, subtraction unit 6, receiving unit 7, driver 8 clock pulses, consisting of clock generator 9, accumulator 10 of the FC signal and counter 11 steps of the FC signal. echo canceller 12, correction-compensation block 13 and adder 14. 2 s. and 4 fn, fla, 3 or more, a method of compensating for echoes; in fig. 2 is a diagram of the correction-compensation unit; in fig. 3 - timing diagrams explaining the features of the device operation. The essence of the way to compensate for echo signals in the case of full-duplex transmission of digital signals is that the echoes.Allows4i ^ (> & CA)
    公开号:SU1713450A3
    申请号:SU843759432
    申请日:1984-07-10
    公开日:1992-02-15
    发明作者:Шольмайер Геро；Зайлер Хайнрих
    申请人:Сименс Аг (Фирма)；
    IPC主号:
    专利说明:

    caused by the digital transmission signals of the transmitting branch of the differential system, in the receiving branch of the differential system, together with the digital signals received from the differential system, they generate a mixture of signals from which the compensation signals generated by the echo canceller from the digital transmission signals at equidistant reading points that are set with using read clock pulses, the phase position of which is adjusted depending on the magnitude of the distortion of the phase correction signals and, where the phase correction signals are accumulated to exceed a predetermined upper threshold or, respectively, decrease below a predetermined lower threshold by summing up the accumulated phase correction signals, simultaneously generate a compensation signal corresponding to the total phase correction signal, which is summed with the compensation signal, and when the upper one is exceeded the threshold or, respectively, lowering below a predetermined lower threshold, shift the phase position of the read clock pulses to one step and dnovremenno erase the total signal phase correction.
    The device for echo cancellation contains a transmitting unit 1, which includes an encoder 2 and a low-pass filter 3. differential system 4, reading unit 5, subtraction unit b, receiving unit 7, driver 8 clock pulses, which include clock generator 9, accumulator 10 of phase correction signal and counter 11 steps of phase correction signal, echo-equalizer 12, correction-compensation block 13 and adder 14, and the information-signal accumulator 15 is included in the compensation correction block 13, constant accumulator The first set of 16 instantaneous values of the slope of the echo signal for the individual steps of the phase correction signal, the first multiplier 17, the accumulator 18, the second 19 and the third 20 multiplication blocks, the register 21 and the constant register 22, and the accumulator 18 includes the adder 23 and the register 24 .
    A device for implementing the method of echo cancellation works as follows.
    The digital transmission signals are transmitted from the communication line to the input of the transmitting unit 1, and the digital receiving signals are output from the receiving unit 7; This device, which may be
    subscriber terminal device or telephone station device, through differential system 4 is connected to a two-wire line, which can
    represent a subscriber line for duplex transmission of digital signals by the method of simultaneous transmission of signals over one channel, to the other end of which another device is connected, identical to
    0 this device.
    Digital signals received from the communication line are input to the encoder 2 of the transmitting unit 1, which, for example, converts binary signals to pseudo-termination signals. For this conversion from the driver, the clock pulses receive transmission clock pulses at the clock input of the encoder. : Converted digital signals with
    The 0 outputs of the encoder 2 are fed to a low-pass filter 3, where signals are generated for transmission over a two-wire line through Differential System 4.
    Differential system 4 with one
    5, on the two-wire line, the signals generated by the transmitting unit 1 are generated for transmission, and on the other hand, they receive signals from the other device through the two-wire line in the form of discrete digital signals, which are then transmitted to the receiving unit 7. In addition to these received signals, the differential system 4 outputs to the receiving unit 7 also spurious signals
    5 - echoes that occur when transmitting transmitted signals or directly in the differential system 4 due to incomplete isolation of the transmission channels or in places where the two-wire line is reflected. Thus, at the output of the differential system 4, not only the transmitted signals appear, but also a mixture of signals formed from them and the echo signals.
    This mixture of signals goes to block 5
    5 readings, from the output of which, at a predetermined reading time, a frequency limited mixture of signals is extracted. The moments of reading information can be selected in such a way that
    0, each bit of a digital signal transmitted to a two-wire line is read once or repeatedly. For this purpose, the read clock pulses are supplied to the readout unit 5 from the clock pulse generator 8. The read values of a frequency-limited mixture of signals from the output of read block 5 are fed to the first inputs of subtraction block 6, since the other inputs simultaneously for each read value of the signal mix, represented as a group of bits, also feed the corresponding echo component groups of bits, so that the output of block 6 subtraction is allocated a group of bits that corresponds only to the received signals.
    These received signals through the receiving unit 7 come in line svzi. Moreover, to the clock input of the receiving unit 7, the read clock pulses are supplied from the clock generator 8, where their phase adjustment is carried out. The generated phase correction signal from the output of the receiving unit 7 is fed to the corresponding input of the driver 8 clock pulses, which is output when a position shift is required. The phase correction signal consists of a control pulse and a binary signal indicating the direction of the required phase position offset.
    The formation of groups of bits supplied to the subtraction unit b to eliminate the echo components is performed in the echo canceller 12, which, depending on the digital transmission signals from the communication line, provides the instantaneous value of the compensating signals in the form of coded groups of bits. These instantaneous values can be stored in the memory cells of the permanent storage of the echo canceller 4. These memory cells are controlled to provide groups of bits depending on the transmitted signals arriving at the input of the echo compensation, torus 12;
    From the output of the echo-equalizer 12, a group of bits goes to the first inputs of the adder 14, to the other inputs of which, from the output of the correction-compensation unit 13, in the form of coded groups of bits, the correction signals are received, compensating the signals when the position of the information is read.
    Moreover, digital transmission signals from the communication line arrive at the input of the compensation compensation block 13. The total compensating signal thus generated from the output of the adder 14 is fed to the subtraction unit 6.
    The clock pulse generator 8 includes a clock generator 9, which generates transmission clock and read clock pulses. These clock pulses, depending on the size of the controlled signal, can be adjusted in phase in the predetermined signal of the phase correction signal, the range. The signal for phase control is issued by a reversing counter operating as a phase 10 signal accumulator 10, to the counting input of which a phase correction signal is fed from the corresponding output of the receiving unit 7.
    In this case, the binary signal, which is part of the phase correction signal, indicating the direction of the required phase shift, sets the counting direction of the reversible counter, and the control pulses serve as counting pulses. Only when the preset upper reading of the reversing counter is exceeded (upper limit) or when the preset lower state of the reversing counter falls below the lower limit of the scientific research institute, a corresponding signal is generated, which is fed to the control input of the clock generator 9 and causes a shift in the phase position of the clock pulses transmitting and reading a predetermined step of the phase correction signal in one or another direction.
    In addition, this signal controls the counter 11 steps of the phase correction signal, made in the form of a reversible counter. When this signal is output, the reversible counter, operating as accumulator 10, simultaneously returns to its original state.
    Output signals corresponding to
    0 defined states of reversible meters operating as accumulator 10 and counter 11 steps. They are provided to the inputs of the correction-compensation unit 13 to determine the correction signals, depending on the phase position of the clock pulses. In addition, the transmission clock pulses from the driver 8 are supplied to the correction compensation unit 13.
    At the same time, digital transmission signals (signal bits) that appear for a specified number of m transmission clock pulses, i.e., are recorded into the storage 15 of the information signal of the correction-compensation block 13. it can be memorized.
    5 there are no digital signals that appear from the time tm-i to the time t. As the accumulator 15 can be applied, for example, the shift register.
    0 In addition, in the correction-compensation unit 13, a permanent storage device 16 is provided with a large number of memory cells, which are stored in the form of a group of bits of the instantaneous value of the signal
    5 slopes of a typical echo. The number of memory cells in this case is chosen such
    that for each phase-correction phase position signal set by clock signals, the instantaneous values of the echo slope for m consecutive clock pulses can be memorized. To control the memory cells, a permanent drive 16 with its address inputs is connected to the counter outputs of 11 steps of a phase correction signal. Moreover, the signals at the outputs of the counter 11 indicate the number of steps that the phase of the clock pulses is shifted from the initial position; under each of these addresses, the instantaneous values of the increase in the reflected signal for m consecutive clock pulses corresponding to the corresponding phase positions are recorded. These instantaneous values associated with the individual clock pulses are read one after the other and multiplied in the first multiplication unit 17 with the digital signals recorded for the corresponding clock pulse in the accumulator 15.
    The multiplication of signals in the first multiplication unit 17 reduces to the fact that for a digital signal a logical 1 outputs an instantaneous value as a group of bits, while for a digital signal a logical O produces an instantaneous value of zero, i.e. when transmitting digital signals, only logical 1 signals contribute to the echo signals.
    At the output of the first multiplication unit 17, the accumulator 18 is turned on, which accumulates the instantaneous values emitted by this block for a period of time equal to m clock pulses and outputs to the outputs a corresponding signal in the form of a group of bits. The drive 18 contains an adder 23 and a register 24 connected to it, the outputs of which are also connected to the first inputs of the second multiplication unit 19, to the other inputs of which a temporal signal is transmitted in an encoded form, reduced in proportion to the ratio of the signal from the reversible counter operating as drive 10, to the upper or lower limit. The total value of this time signal corresponds to the step of the phase correction signal of the clock signals. From this reduced time signal and the sum signal outputted by the register 24, the second multiplication unit 19 generates a correction signal and outputs it to the adder 14. In order to form the reduced time signal, a register 21 is provided in the correction-compensation unit 13, to which the output of the reversible counter is supplied operating as accumulator 10, and a constant register 22, in which a constant is written that indicates the total step size of the signal
    reaction, divided by the signal value corresponding to the upper or lower limit. From the signals from the outputs of the register 21 and the register 22 of constants, the third multiplication unit 20 generates a reduced, time signal.
    The essence of the method for compensating echoes is illustrated in the pulse diagram shown in FIG. 3
    0 In the diagram of FIG. The two echoes 3Ci and ESa, which are displaced relative to each other, are shown for the maximum, the maximum values of which are denoted, respectively, Mi and М2. Maksisum MI should be in this.
    5, for example, using the rising edge of the receive clock (FIG. 36) is read in the receive branch. This may be the initial phase position of the clock read pulses of the imaging unit 8, with
    In this phase position, the echo signal received together with the digital signal is fully compensated by the compensating signal emitted by the echo equalizer 12 at this time. If the loss of the phase position between the transmit and read clock pulses is changed, then the echo would require a phase shift of these clock
    0 pulses.
    FIG. As an example, it is shown that the maximum of the echo signal now appears with a time delay ({Ma echo signal ES2).
    5 Completely compensating for this signal by the compensating signal provided by the echo canceller 12 can now be made by shifting the phase position of the receiving clock.
    0 gear by a certain amount. This is represented in FIG. By means of the stroke of the receiving pulses shown by the dashed line of the curve. Phase position offset could lie
    5 within the pitch of the phase raster correction signal (PFC), by which the clock pulses in the imaging unit 8 can be shifted (Fig. 3g).
    Instead of instantly shifting the phase position according to the crioco6y proposed, phase correction signals generated due to the changed phase position in the receiving unit 7 are accumulated in a reversible counter operating as a stack of accumulator 10, while maintaining the newly set position.
    FIG. The signals of the phase correction are formed at the output of the receiving unit 7 during phase fluctuations within the phase correction signal step.
    (PFC). in this case, as an example, when the phase position is shifted by one step of the phase correction signal, the receiving unit 7 outputs to the reversible counter, operating as accumulator 10, a specified number of phase correction signals, which is determined for the reversible counter, which acts as accumulator 10 , an upper or lower limit, upon reaching which a control signal is output to the clock generator 9 for shifting the phase position by one step of the phase correction signal (PFC). A comparison of the echo signals (Fig. 3a) shows that the echo signal ES2, due to the appearance with a time delay by the time of reading the information set using the receive clock (Fig. 36), is active only with the amplitude value A. But echo the compensator 12 also provides a compensating signal corresponding to the echo signal 3Ct and too large in magnitude compared with the amplitude value A of the echo signal ECG. The resulting uncompensated echo component is now compensated for by the correction signal generated by the correction-compensation unit 15. In order to form this correction signal (Fig. A) in a reversible counter operating as accumulator 10, four control signals of phase correction are accumulated. Using this signal, which is rewritten to register 21, and the constants recorded in register 22 of constants of the correction-compensation block 13, a reduced time signal is set in the third multiplication unit 20.
    Since, with the example selected here, the position of the phases of the clock pulses relative to the initial position of the phases should change only within the step of the phase raster of the FS, which serves as a measure for phase displacement, due to the output signal of the reversible counter operating as accumulator 10, the upper and lower limits are not exceeded. As a result, the control signal for controlling them is not fed to the clock generator 9, the nickname of the 11-step counter. As a result, the 11-step counter is still in its initial position, with its output signal corresponding to this initial position, the fixed accumulator 16 is controlled, producing instantaneous values of the steepness of the echo signal in accordance with this initial phase position. From these instantaneous values, taking into account the reduced time signal, a correction signal is set, which is necessary for the initial phase position to compensate for the echoes.
    In the timing diagrams of FIG. 3 was considered only the case when there is only a slight change in the phase position of the clock pulses that lies within the phase correction step. When the phase position changes out of the bounds of the phase correction step due to the phase correction signal accumulated in the reversible counter operating as the accumulator 10 exceed depending on the direction of change
    5 phase position upper or lower limit. As a consequence, the reversible counter, operating as accumulator 10, outputs a signal to the control input of the clock generator 9 in the driver 8. Thereafter, the reversible counter, operating as accumulator 10, returns to its initial state. Minor changes in the phase position inside the phase signal considered now
    5, corrections are then processed as described above.
    In addition, the instantaneous values of the slope of the echo signal for a certain moment of reading information can be
    0 are obtained from the instantaneous values of the steepness of the digital signal generated by this moment by the transmitting unit 1. In order to memorize these instantaneous values, it is necessary in this case to replace the permanent drive 16 with the write and read drive.
    The correction-compensation unit 13 (FIG. 2) for determining the correction signals can be made in the form of a microprocessor.
    权利要求:
    Claims (6)
    [1]
    1. A method of compensating for echo signals in full duplex transmission of digital signals, which means that the echo signals caused by digital transmission signals generated by the transmitting unit of the transmitting branch of the differential system are received in the receiving unit of the receiving branch of the differential system along with the received ones through the differential system
    0 digital signals receive a mixture of signals, from which they subtract the compensation signals generated by the echo-equalizer from the digital transmission signals at equidistant reading moments, which are set using clock pulses, the phase position of which is regulated in steps depending on the phase correction signals, And in order to increase the accuracy of compensation at a given value of the phase control step, the phase correction signals are accumulated to exceed the specified upper threshold. whether, respectively, lowering below a predetermined lower threshold by summing the accumulated phase correction signals simultaneously generate a correction-to signal (sensation corresponding to the total phase correction signal, which is summed with the compensation signal, and when the specified upper threshold is exceeded or lowered below the specified lower threshold, they shift the phase position of the clock read pulses is one step and at the same time erases the total phase correction signal.
    [2]
    2. A method according to claim 1, in which, in order to generate a correction-compensation signal by a certain reading moment, a predetermined number of consecutive digital transmission signals are multiplied with the instantaneous value of the echo slope signal the signal corresponding to the digital transmission signal at the appropriate moment of reading, the resulting signals after multiplying are summed and multiplied with the time signal, the full value of which corresponds to the step size of the phase position of the clock pulses with readout, and the time signal is reduced to a predetermined upper threshold or, respectively, a predetermined lower threshold, compared to the total phase correction signal.
    [3]
    3. Device for compensating echo signals for duplex transmission of digital signals, containing a transmitting unit in the transmitting branch of the differential system, the signal input of which is connected to the input of the echo compensator, and in the receiving branch of the differential system - serially connected reading unit, subtraction unit and receiving unit The output of the phase correction signal of which is connected to the input of the clock pulse generator, the output of the reading clock pulses of which are connected to the clock input of the reader, which distinguishes that the series-connected correction-compensation block and the adder are inputted, and the clock pulse generator comprises a clock generator with a control signal input, a phase correction signal accumulator, and a phase correction signal step counter, the first clock generator output being the clock pulse output of clock body shapes pulses, the output of the clock transmission pulses of which is the second output of the clock generator, and the input of the clock pulse generator is the input of the accumulator Phase Correction Solids, Overflow Signal Output
    which is connected to the input of the control signal of the clock generator, to the input of the counter of the steps of the phase correction signal and to the input of the initial installation of the accumulator of the phase correction signal, the output of the sum signal
    which is connected to the first input of the correction-compensation block, to the second input of which the output of the counter of the steps of the phase correction signal is connected, the output of the echo-compensator is connected to another input
    an adder, the output of which is connected to another input of the subtraction unit, the signal input of the transmitting unit is connected to the corresponding input of the correction-compensation unit, the output of the clock transmission pulses of the clock generator, with the corresponding inputs of the transmitting unit of the echo-equalizer and the correction-compensation unit, and the output of the clock read pulses - with the corresponding input of the receiving unit.
    [4]
    4. The device according to claim 3, in which the correction-compensation block contains an information signal accumulator and a permanent accumulator of instantaneous values of the steepness of the echo signal for individual steps of the phase-correction signal, whose outputs are connected to the corresponding inputs of the first multiplication unit, the output of which is connected to the input of the accumulator, the output of which is connected to the first input of the second multiplication unit, to the second input of which the output of the third multiplication unit is connected, to the inputs of which the outputs of the register and the reg a source of constants, wherein the signal and clock inputs of the information signal accumulator are respectively the signal and input clock of the transmission pulses of the correction-compensation unit, the output of which
    is the output of the second multiplication unit, and the first and second inputs of the compensation compensation block are respectively the inputs of the register and the constant storage of the instantaneous values of the steepness of the echo signal
    for the individual steps of the phase correction signal,
    [5]
    5. Device on PP. Zi 4, characterized in that the drive is made in
    View of a series-connected adder and register, the outputs of which are connected to the second inputs of the adder and which are the outputs of the accumulator, whose inputs are the first inputs of the adder.
    [6]
    6. The device according to claim 3, which is based on the fact that the signal accumulator is phase
    Howled
    8g.
    15
    0 / 7fSffB
    (Rig.1
    13 correction is made in the form of a reversible counter.
    From 5p
    sixteen
    BLU
    2i
    Itf
    T
    ig
    22
    (rig, 2
    24
    23
    WITH
    H5L.14
    nineteen
    Mi HZ
    but
     3Cl
    In i.
    U j
    fie. J
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US4074086A|1976-09-07|1978-02-14|Bell Telephone Laboratories, Incorporated|Joint adaptive echo canceller and equalizer for two-wire full-duplex data transmission|
    US4072830A|1976-10-04|1978-02-07|Bell Telephone Laboratories, Incorporated|Variable phase shifter for adaptive echo cancellers|
    DE2920575C2|1979-05-21|1981-09-17|Siemens AG, 1000 Berlin und 8000 München|Digital telecommunications system with at least one four-wire line section|
    FR2479617B1|1980-03-26|1983-10-21|Trt Telecom Radio Electr|
    DE3120639C2|1981-05-23|1986-10-23|ANT Nachrichtentechnik GmbH, 7150 Backnang|Arrangement for adaptive cancellation of speaker echoes|
    DE3121545C2|1981-05-29|1986-12-04|Siemens AG, 1000 Berlin und 8000 München|Crosstalk and / or Echo cancellation circuit|
    FR2509552B1|1981-07-09|1983-12-02|Telecommunications Sa|
    SE426764B|1981-11-02|1983-02-07|Ellemtel Utvecklings Ab|PROCEDURE TO ACCEPT ADAPTIVE ECO-ELIMINATION BY TRANSFER OF DIGITAL INFORMATION IN DUPLEX EQUIPMENT FOR CARRYING OUT THE PROCEDURE|
    GB2111354B|1981-11-19|1985-06-19|Standard Telephones Cables Ltd|Echo canceller|NZ214905A|1985-01-29|1988-09-29|British Telecomm|Noise cancellation by adaptive filter compensates for timing variations|
    JPH0773240B2|1985-12-13|1995-08-02|日本電気株式会社|Automatic retraining method|
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    DE3874997T2|1987-07-20|1993-03-25|Nec Corp|Echo compensator.|
    ES2035186T3|1987-07-29|1993-04-16|Siemens Aktiengesellschaft|ECOS COMPENSATOR.|
    JPH0752859B2|1987-11-06|1995-06-05|日本電気株式会社|Echo remover|
    JP2810052B2|1987-11-18|1998-10-15|株式会社日立製作所|Transmission equipment|
    DE4334289A1|1993-10-08|1995-04-13|Kommunikations Elektronik|Circuit arrangement for digital data transmission|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DE19833327467|DE3327467A1|1983-07-29|1983-07-29|METHOD AND CIRCUIT ARRANGEMENT FOR COMPENSATING ECHO SIGNALS|
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