Pulse-code modulation translator

专利摘要:
The present Pulse Code Modulation (PCM) translators include a first translator (COLI) for translating a PCM input word coded according to the A or mu-iaw into a linear PCM output word and a second translator (LIC0) for translating a linear PCM input word into a PCM output word coded according to the A or mu-iaw. The choice of the A-law or mu-law is done by selecting the binary value of a single control bit (A).
公开号:SU1702879A3
申请号:SU843793654
申请日:1984-09-17
公开日:1991-12-30
发明作者:Герман Лутгардис Корнелиус Рабай Дирк；Рене Хаспеслаф Дидье
申请人:Алкатель Н.В. (Фирма)；
IPC主号:

专利说明:

The invention relates to pulse-code modulation translators for converting an input pulse-modulated word to a companded pulse-modulated word containing a 3-bit segment code and a 4-bit stage code.
The purpose of the invention is to extend the functionality by selectively transforming according to the A-law or jU-law and simplifying the structure. FIG. Figure 1 shows a pulse code modulator translator for translating a compressed input word into a linear output word; in fig. 2 - pulse code modulation translator for translating a linear input word into a compressed output word; in fig. 3 shows synchronizing pulses for controlling the translator as shown in FIG. one; in fig. 4 shows sync pulses for controlling the translator shown in FIG. 2
Pulse-coded modulation translator for translating a compressed input word into a linear output (Fig. 1) contains an input register 1, a matching unit 2, the first is the fourth block of triggers 3, 4, 5 and b, a segment decoder 7, an arithmetic unit 8 , block 9 keys, the multiplier 10, the output block 11, the adder 12 and the block 13 synchronization, the Multiplier 10 contains the first and second registers 14 and 15 of the shift.
A pulse code modulator translator for translating a linear input word into a compressed output word (FIG. 2) contains a matching unit 16, an input register 17, an adder 18, a first shift register 19, a segment decoder 20, an arithmetic unit 21, the first third blocks the trigger 22-24, the encoder 25, the output unit 26, the first and second blocks 27 and 28 keys, the inverter unit 29, the synchronization unit 30 and the second shift register 31.
The translator of FIG. 1 is made with the possibility of determining the function
T (L + a-24+ c) -5K1 + s
where if is the input word; L - step code;
a, b, c are variables. K1 refers to the segment code and depends. together with the variables a, c, and c of the control bit (A), indicating that this output word is encoded according to the A-law or, m-law.
From this function, it follows that the operations that are performed for the A-law and the r-law are very similar, which makes it possible to use the same translator structure for both laws. The segment decoder 7 is designed to decode the 3-bit code of the segment into 1-of-8 code 87, S6, ..., S11, S10. The arithmetic unit produces variables.
and S1 0 + A;
in S1 0 (GGP + A); SO S10-A;
S1 S1J0- A + S11,
moreover, the code word S 7, ..., S1, S0 forms a modified code of a segment having a decimal value K1.
Block 6 of triggers is intended for half-students of the modified step code.
L + a-24+.
A multiplier 10 is needed to multiply the obtained modified step code by 2K to obtain a product of 0 + a-24 +) -2k.
Code-to-Pulse Code Modulation Translator for converting a com- plexed pulse-code-modulated input word containing a 3-bit Segment code and a 4-bit stage code to a linear pulse-code-modulated output word (Fig. 2 ) The modem defines the functions;
K og2 (f + c) -2-4J;
L (fT + c) -2K-d, where K is the code of the segment;
Stage L-code;
c and d are variables.
It refers to the code of the segment and depends in the same way as the variables c d, on the control bit (A), indicating that the input word is encoded according to A-law or according to -law.
The translator (Fig. 2) contains an adder, controlled by the control bit A to sum the variable with the input word to obtain the modified input word + c and store it in the shift register 19, the decoder 20 connected to the shift register 19 for decoding the 8 most significant bits of the modified input word 7 + c in the code 1-of-8, the encoder 25, issuing variables:
50 S10-A;
51 S1p-A + S11,
moreover, the code word has a decimal value K1, an arithmetic unit 21, a key block 28, and a shift register 31 for multiplying the modified input word Ј / + c by and summing the variable -de with the obtained product to obtain the code of the level L.
 The multiplier 10 is needed to multiply the binary word stored in the first shift register 14 by 2x, where x 0, ..., K, shift this word through the x steps of this shift register.
The code-pulsed-modulated signal is encoded according to a segmented logarithmic A-law or i-law, each of which contains 8 segments for each of the values of the sign S encoded by bit b1. Three bits B2-B4 define one segment K among 8 possible segments KB, ..., K7, and bits B5-B8 define one level L among 16 possible equal steps in the segment. According to the r-law, the relative sizes of the steps in the K0, ..., K7 segments are 2 °, ..., 27, respectively, whereas, according to the A-law, they are equal to 2.2.2,.,., 2, respectively. This means that the step size in the K0 segment according to the law A is twice the size of the step in the U segment according to the law / 4. A compensated code-pulse modulated signal, for example, is received and transmitted in a form where all bits, except the sign one, are inverted (a-law) or where only even bits are inverted (A-law) ....
It can be shown that the corresponding algorithm for 8-bit transcoding
five
10 15
0
compand code-pulse-modulated word containing bits b1-b8 with the sign bit S b1, segment code K b2 bv4 and stage code L b5, wb, b7, b8 into a 13-bit linear code-pulse-modulated word by formula
ЈT 2K (L + a-24 + b-2 1) + s or
,
where c is 0 dl a-law and c -16 dl, “is zzkona;
K1 0 - 7 for segments K0 - K7, with the exception of the segment Kf according to the A-law, the value of which is equal to 1, not 0;
and in 1 for the segments K2 - K7 for both laws and for K1 according to // - the law, therefore
(L + 24 + 21);
-a 1 and 0 for the segment K $ (and -law) and K1 (A-law), therefore
 + 24);
-a to 0, and K1 1 for the K0 segment (A-law), therefore
The translator of FIG. 1 can calculate this algorithm as follows
The compiled code-pulse-modulated signal applied to the input of block 2, the most significant bit goes first and transformed in matching block 2, and the 8-bit receive signal containing bits b1 through b8 (Fig / 1 ) and determining S, K and L, are successively entered into register 1 in two consecutive packets of four bits B1-B4 and B5-B8.
The four bits b1 through b4 are locked in block 3 of the flip-flops under the control of the first synchronization pulse TP2 (Fig. 3). The sign bit S b1 is fed to output block 11, while the 3-bit segment code K b2-B3 b4 is fed to a segment decoder, where it is decoded into 1-of-8-segment code formed by the bits:
S7, -S6, / S5, S4.S3, S2.S1.S0
at the same outputs of the decoder 7, This code defines the Kj3 segments by K7 as follows:
76 54 3 2 1 About the Partial, meaningful. j K
K (E0 .000;: 0И0 1 #
K10CH 0bI0I1 DV V
K71.00 .. 0ra # 0i 7
Thus, each of the outputs S1j0, S11. ..., S7 decoder 7 is activated for the corresponding one of the segments K0, K1, K2, ,,., K7 and for these segments the decimal values K1 0, 2, .... G, 7 are allocated. However, according to the above algorithm : Mu is wrong for the Kj3 segment according to the A law, since the value of K must be equal to Ta and $.
Under the control of the timing pulse, the bit B1 and the output code S10, S11,.,., S7 of the decoder 7 are locked in block 3 of the flip-flops so that bit b1 and S2-S7 are fed to the block 6 of the flip-flops, then kgk bits S 0 and S1 are fed an arithmetic unit 8, which is used to calculate the values of a and b and to calculate the correct value of K for the K0 segment according to the law A. At its own outputs a, b, S0 and S1, block 8 creates the same-name signals:: l /. ,
  - .. /
 a S10 - (- A;,. / - l:.
V v.:. . ...,.,
B S10 (S11 + A): - ... . ..
S0-S10; A; . v.
S1 SVA + S4.
It follows from these relations that, as the above-mentioned algorithm requires: a in 1 for the K2-K7 segments according to both laws A and / and, characterized in that A 0 and A 1, respectively. :
a 1 and c. - O for the K0 segment (w -law) and K1 (A is the law); and in 0 for the K0 segment (A-law), therefore, the above segment codes change, and give the following modified segment codes:
 S7S6S5S4S352S1S0
К0Чи) - у # уasл 1:
K0 (A) pK1 t Poison. E-IS1ff
 K7. 1ST & V-V & I. :
.- Thus, the decimal value of K1 1 is assigned to K0 by the A-law, which is required,
The second packet of bits B5 WB B7 B8 determining the code of the stage L is entered into register 1. These bits are locked in block 3 under the control of the second synchronization pulse TP2 and then locked in
block 4 with a TP4 synchronizing pulse. Because of this, these bits B5-B8 are fed to the information inputs of multiplier 10 ..
Under the influence of the subsequent synchronization pulse TP5, the bits in {, 0, 31, S2-S7, as well as a, v at the outputs of block 3 and block 8 are locked in block 6 of flip-flops, with the result that bit b1 is fed to block 11,
S-bits are fed to a block of 9 keys and bits
and served on information inputs
multiplier 10. Modified step code,
formed by bits a, b5, wb, b7, b8 and c,
is now entered into register 14 under the control of a TPC clock pulse, inverted in this circuit and fed to the outputs of the cells of this register. Thus, on (zykhodah register 14 is present,
B5, WB, B7, B8 and c.
So, the modified step code
L + a
.24 +
p1
inverted bits are stored in PCT cells on PC6 register 14, which are given values from 24 respectively. As follows from the algorithm, this value should now be multiplied by 2K in order to obtain a value of 5g.
By means of a negatively directed TRb synchronizing pulse, also bits S0, S1 and S2-SJ are fed to the control inputs of the corresponding cells PC11 by PC18 register .15. In this way, a connection is established between the output of register 14 and the second output of the PC11 register 15 through a number of cells equal to the value of K1.
Running six synchronism
TP7 pulses applied to the control input of register 14, and TP1 clock pulses applied to the control input, register input 15, bits in, b8, b7, wb, b5 and a are shifted along sequential cells of registers 14 and 15 and in the first cell used in register 15 is inverted. Thus, the value stored in register 14 is inverted and multiplied by
a factor of 2, so a binary number appears at the output of register 15,
According to the specified algorithm for
get the desired value of ЈG to the value you need to add the value of 0dl
A-law, or the value of the C -16 Act. This is accomplished by adder 12, which is controlled by the same control input A as block 8. Thereafter, the result and the bit of the sign q are combined in output block 11 and;
Ranges are formed before feeding to the outlet.
FIG. Figure 2 shows a translator configured to transcode a 13-bit linear 5 code-pulse modulated word into an 8-bit companded code-pulse modulated word.
The corresponding algorithm for transcoding a 13-bit linear code-10 pulse-modulated word containing bits from B1 to B13, where the sign bit is s B1, and the value of 1G is determined by bits from B2 to B13, into an 8-bit compand code-pulse modulated a word with a sign / bit S, a K segment and a step is specified by
K log2 (s) -2 4 L (tT + c) -2 K-d,
s
where c 0 for a-law;
from 16 dl // -law;
and at K from 0 to 7 and d 16 segments from U to 25 K7, except for the Q segment for the A-law, for which this value is 1. and not (5, and for which also d 0. For K, the lower limit.
The translator (Fig. 2) can calculate 30 this algorithm as follows.
The linear code-pulse-modulated word is fed to the input of block 16, the low-order bit being fed first and transformed in the matching block 16, 35 and the resulting 13-bit linear pulse-modulated word containing bits from B1 to B13 with the sign bit S B1 and a value of 5 B2, ..., B13 is stored in register 17. The sign bit B1 is supplied to the output block 26, and the broken B2 through B13, defining the value 3, are sequentially entered into the register 19 under the influence of the TP8 clock pulses and t c ez adder 18, in which to 45 the value of U p The discount is from 0 or 16, depending on the conversion according to A-law or JLI-law (which is given by control input A). Thus, the word stored in register 19 is 50 a modified input word + c. Since bit b13 is the low-order bit and has a weight function of 2, eight bits b2 through b9 determine the value of (+ c)% 2. Of which is now used to determine 55
15
20
K log2 (7 + c).
. This is done by determining only the highest degree for 2. in expression (17+ s). The highest degree determines the lower limit of the segment.
To this end, inputs b2 through b9 of cells SC1 through SC8 of register 19 are connected to segment decoder 20, which transforms the following 8-bit binary input codes:
ten
15
where X has an arbitrary value, in the following 1-IZ-8 segment codes appearing on the same outputs of the decoder 20:
The decoder 20, for example, contains a plurality of clocked AND gates defining a Boolean function B2; v2.vz; B2B3, B4; ... in 2vSv4v5v6v7v8. The output of each of these valves is connected to the corresponding one of the outputs S7, .... S directly and through the block 29 inertors with the others.
These last output terminals S 0, S11, .... S7 of decoder 20 are associated with corresponding segments K (f, K1, ... K7, which are given the decimal values
The decoder 20 actually detects the first 1. in a sequence of bits b2 to b9, with the exception of K0, and ignores subsequent binary values in this sequence. This means that it defines the highest levels for 2 and does not take into account lower degrees. Therefore, each of the segments is determined by its lower limit. Q.0 is determined if all bits b2 through b8 are 0, regardless of b9, since there is confidence that it is a segment 0.
Said outputs S 0, S 1, ..., S7 are fed into the n-a block of 22 flip-flops and from there to the encoder 25, which translates 1-of-8 segment codes into 3-bit segment codes, which are fed through the block 24 flip-flops to output block 26.
During the described operation, the value of Y + c shifted in register 19 by one step to the right, therefore, at the outputs of its corresponding cells SCI no SC12 there are bits from B2 to B13.
The magnitude of the step L (5 + s) -2 - d is determined. The decimal value of K can be used for the K0 (/.I -law) and K2-K7 segments (both laws), but not for the K0 by the A-law, since in this case the step size is equal to the size of the K1 segment. In order to take this into account, the output signals S10 and 311 of the decoder 20 are fed to block 21, which outputs on its outputs S0 and S1 signals
50 S10-A ;.
51 S0-A + S11. ,
 These output signals from 0 to 7 together with S $ no S7 are fed to the control inputs of the block 28 keys Sft) 0 no Soft, respectively. As a result, and depending on the decimal value K1, equal to 0, 1, .. ,, 7,
the outputs of the cells SC12, SC11,, .., C5 register 19 respectively, signals are given to the inputs of register 31, Shifting the contents of the left cells you can get the value (5 + s) -2 .., ..
However, only four bits are shifted.
in four cells of register 19, so there
The following binary values are remembered: for K0 (and-law) B10
dl, k0 (a-law) and
K1 (both laws9

for K7 (both laws), VZ v4 v5 wb
Thus, the preceding bits that have are ignored each time. state 0, except for the latter, which has state 1 for the K0 (and -law) and K1-K7 segments (both laws) and state 0 for the K0 segment (A-law), i.e. bits в9 (К0, 4 -law) and в8 (К1, both laws) according to ВЗ (К7, both laws) have state 1, whereas в8 О (К $, А-law). If you do not take into account these bits; 1.2 or 0.2 is actually subtracted from the value stored in register 31. Thus, this value is actually a 4-bit stage code.
-to
1 .- (U + s)
or
L (54c) -2
-TO
The contents of register 31 are locked in block 23 and then fed to output block 26.

权利要求:
Claims (3)
[1]
1. A pulse code modulator translator for translating a compressed input word into a linear output word containing an input register, a segment decoder,
a key block, an output block, and a synchronization block, the first and second outputs of which are connected respectively to the synchronization inputs of the output block and the key block, characterized in that
 extending the functionality by selectively transforming according to the A-law and simplifying the structure, a matching block is entered into it, the first is the fourth trigger block, the arithmetic block, multiplier and adder, the control input of which is combined with the control input of the arithmetic block and is the translator input, the output of the matching unit
connected to the input of the input register, the outputs of which are connected to the corresponding information inputs of the first block of flip-flops, the outputs of which are connected to the corresponding information
the inputs of the second block of triggers, the outputs of which are connected to the first information inputs, the multiplier, the output of which is connected to the information input of the summator whose output is connected to the first information input of the output block, the inputs of the segment decoder are connected to the corresponding outputs of the first trigger block, the first output of which is connected with the first information entry
the third block of triggers, the second information inputs and the first and second outputs of which are connected respectively to the outputs of the segment decoder, the first information inputs of the fourth block
triggers and information inputs of the arithmetic unit, the outputs of which are connected to the second information inputs of the fourth block of triggers, the first,
The second and third outputs of which are connected respectively to the second information input of the output block, the information inputs of the key block and the second information inputs of the multiplier, the third information inputs of which are connected to the corresponding outputs of the key block, the input of the matching block and the output of the output block , the first synchronization input of the multipliers is connected to the first output of the block
synchronization, the second synchronization input of the multiplier is combined with the synchronization input of the third trigger block and connected to the third output of the synchronization unit, the fourth to the seventh outputs of which are connected respectively to the synchronization inputs of the first, second and fourth trigger blocks and the third synchronization input of the multiplier.
[2]
2. The translator according to claim 1, expressing the fact that the multiplier contains the first and second shift registers, the information inputs of the bits of the first shift register, except for the first and last, are connected respectively to the first information inputs of the multiplier, information the inputs of the first and last bits of the first shift register are connected respectively to the second information inputs of the multiplexer, the output, the output of the last digit of the first shift register is connected to the control inputs of the bits of the second shift register, the information inputs to The second bits of the second shift register are output of the multiplier, the clock inputs of the bits of the second shift register and the first and second clock inputs of the bits of the first shift register are combined and are respectively the first, second and third sync multiplier inputs.
[3]
3. Pulse-code modulation translator for translating a linear input word into a compressed output word containing the first shift register, the first and second outputs of which are connected respectively to the first and second inputs of the segment decoder, the outputs of which are connected respectively to the first information the output inputs of the first block of triggers, the first outputs of which are connected to the corresponding inputs of the encoder, the first block of keys, the outputs of which are connected to the first information outlets of the output block, the output of which is ode of the device, the synchronization unit, the first output of which is connected to the clock input of the first shift register, characterized in that, in order to extend the functionality by selectively transforming according to A or fi law and simplifying the structure, an inverter unit is inserted into it, a matching unit , input register, adder, second key block, arithmetic block, second shift register, second and third trigger blocks, input of matching block is a device input, output is connected to information input of input regis tra, the output of which is connected to the information input of the adder, the output of which is connected to the information input of the first shift register, the second and third outputs of which are connected respectively. The information inputs to the second key block, the outputs of which are combined and connected to the information input of the second shift register, the outputs of which are connected to the information inputs of the second trigger block, the outputs of which are connected to the information inputs of the first key block, synchronization inputs of the second shift register of the input register are combined and connected to the first output of the synchronization unit, the control inputs of the adder and the arithmetic unit are combined and are the control input of the device, the information The ion inputs and outputs of the arithmetic unit are connected respectively to the corresponding outputs of the segment decoder and the second information inputs of the first trigger block, the inputs of the inverter block are combined with the first control inputs of the second key block and connected to the corresponding outputs of the first trigger block, the outputs of the inverter block are connected respectively to the second control inputs of the second key block, the encoder's outputs are connected to the information inputs of the third trigger block, whose outputs are connected to the second th information inputs of the output block, the third information and clock inputs of which are connected respectively to the output of the first bit of the input register and the second output of the synchronization unit, the third, fourth and fifth outputs of which are connected. respectively to the clock inputs of the first and second block of triggers, clock inputs of the first key block and the third block of triggers.
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US5991278A|1996-08-13|1999-11-23|Telogy Networks, Inc.|Asymmetric modem communications system and method|

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US6549569B1|1999-04-09|2003-04-15|Siemens Information & Communication Networks, Inc.|System and method for improving conversion between A-law and U-law coding|

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KR101418711B1|2012-12-27|2014-08-06|주식회사 선익시스템|Substrate align module and apparatus for deposition having the same|

法律状态:

优先权:

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申请号 | 申请日 | 专利标题

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BE2/60209A|BE897773A|1983-09-19|1983-09-19|PULSE CODE MODULATION CONVERTER|

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