• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In a high power MOSFET having a plurality of closely packed polygonal sources 123 spaced from one another on one surface of a semiconductor body 121, and an elongated gate electrode 141 exposed in the spacing between the polygonal sources and cooperating with two channels, 161, 162 one for each adjacent source electrode, to control conduction from the source electrode through the channel and then to drain electrode 151 on the opposite surface of the semiconductor body, the conductive region adjacent the channel and between adjacent sources is relatively highly conductive in the section 128 of the channel adjacent to the surface containing the sources. The polygonal shaped source members are preferably hexagonal. Each polygonal region has a relatively deep central portion 122, 123 and a shallow outer shelf portion 124, 125. The shelf portion generally underlies an annular source region 126, 127. The deep central portion underlies an aluminium conductive electrode 150 and is sufficiently deep that it will not be fully penetrated by aluminium spiking. <IMAGE>
    公开号:SU1621817A3
    申请号:SU792835965
    申请日:1979-10-11
    公开日:1991-01-15
    发明作者:Лидов Александер；Герман Томас；Руменник Владимир
    申请人:Интернэшнл Ректифиер Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    one
    (21) 2835965/25
    (22) 11.10.79
    (31) 951310; 38662
    (32) 13.10Л8; 01.05.79
    (33) US
    (46) 01.15.91. Bgap 9 2
    (71) International Rectifier Corporation (US)
    (72) Alexander Lndov, Thomas Herman and Vladimir Rumennik (US)
    (53) 621.382 (088.8)
    (56) U.S. Patent No. 4,115,793, cl. H 01 L 29/78, 1978.
    U.S. Patent No. 4,072,975, cl. H 01 L 29/78, 1978.
    (54) POWERFUL FIELD TRANSISTOR WITH ISOLATED SHUTTER
    (57) The invention relates to high-power MOSFET transistors, in particular, to the structure of a MOSFET transistor, which allows its use in high-power devices with relatively high reverse
    The invention relates to a high-power MOSFET device, in particular, to a structure for a MOSFET device, which allows its use in high-power devices with relatively high reverse voltage and low on-state impedance.
    voltage and low on state impedance. The aim of the invention is to increase the power of the field effect transistor. In a powerful POLER-transistor with an insulated gate, containing in the high-impedance plate base areas, in each of which the source areas of the opposite conduction type are formed, the gate formed between the base areas, and the drain area on the opposite side, the plate area between the base areas is made with a conductivity of not less than 2 times the higher conductivity of the high-resistance plate, which reduces the on-state resistance per unit area of the device more than doubled. The source areas have the shape of a polygon, in particular the shape of a hexagon, to obtain a constant gap along the main source lengths, which ensures a high transmission capacity of large currents. 2 hp f-ly, 2 ill.
    The aim of the invention is to increase the power of the field effect transistor.
    FIG. 1 shows a chip of a field MDP transistor, a plan view; in fig. 2 is a section A-A in FIG. one.
    A powerful field-effect transistor has two electrodes 1 and 2 of the source, which are separated by a metallized electrode 3 of the gate, separated from
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    the surface of the semiconductor wafer when using layer 4 of silicon dioxide. The serpentine trajectory 5, following the silicon dioxide of the gate, has a length of 50 cm and 667 irregularities, which are depicted in FIG. Other channel widths can also be used. The source electrodes 1 and 2 can be extended in the lateral direction to serve as pale yellow boards to facilitate the propagation of the depletion area created during the application of the reverse voltage. Each of the electrodes 1 .. and 2 sources supplies current to a common drain electrode 6, which is mounted on the bottom of chip 7. A silicon chip 7 is formed on an nf substrate 8, which may be about 14 miles thick (0.356 mm). The epitaxial naked layer 9 on the substrate 8 is a cohom n-type conductivity and has a thickness and resistivity depending on the desired reverse voltage. All transitions are formed on this epitaxial layer, which may have relatively high resistivity. In the proposed transistor, the epitaxial layer 9 has a thickness of about 35 microns and a specific resistance of about 20 ohms / cm. A preferred extended serpentine p-area under each of the source electrodes 1 and 2, which thus passes around the serpentine path shown in FIG. 1. These p-regions 10 and 11, shown in FIG. 2, The maximum depth, which is greatly increased in order to form a large radius of curvature. This allows the device to withstand higher reverse voltages. The depth of regions 10 and 11 is preferably 4 microns at the location indicated in FIG. 2 by the index X and 3 μm in the place indicated by the index Y.
    Using D-MOS technology two
    The p-regions 12 and 13 are formed under the source electrodes 1 and 2, respectively, and in the area with p-regions 10 and 11, the areas of the n-type channels are defined - regions 14 and 15, respectively. The regions 14 and 15 of the channels are located under the layer 4 of silicon dioxide of the gate 3 and can be inverted by appropriately applying the signal

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    to gate 3 in order to provide conduction from source 1 and source 2 through the inversion layers to the central region located under gate 3 and then to the drain electrode 6. Areas 14 and 15 channels can have each length in the order of 1 micron. A large part of this central area is made highly conductive and contains a n-area 16, located directly below the gate silicon dioxide layer 4, while the n-area has a depth of about 4 microns (the depth change limit is 3-6 microns). While its exact conductivity unknown n varies in depth, it is high relative to the n-area below it. In particular, region 16 has a high conductivity, which would be determined by the total dose of injected ions in the order of 1x10 - 1x1 phosphorus atoms per cm2 at 50 kV following the initiation of diffusion at temperatures from 1150 ° to 1250 ° C for 30 - 240 minutes. By forming a region 16 of a relatively highly conductive n material using a diffusion or other operation, the characteristics of the device are greatly improved and the direct resistance of the switched on state of the device is halved.
    The presence of the high conductivity region 16 does not affect the reverse voltage characteristics of the device. Cause the area under the gate oxide layer 4 and between the regions 14 and 15 of the channels more highly conductive, the direct resistance of the switched on state of the high-power switching device is significantly reduced.
    It is assumed that the conductive channels of regions 14 and 15 are made of p-material and are inverted into n-type conductivity to ensure that the conduction channel on the main carriers from sources 1 and 2 is received in the central region 16 when the corresponding gate voltage is applied. However, all these types of conduction can be reversed, therefore, the device will work as a p-channel device, not as an n-channel device.
    Two sources are placed on the same semiconductor surface.
    516
    chip and are separated in the transverse direction relative to each other. A gate electrode deposited on a conventional gate oxide is located between the sources. The two p-type conduction channels are located along the gates and are separated from one another by the main region of the n-type conductivity. The current from each source can flow through its respective channel (after creating the inversion layer defining the channel). Thus, the conductivity of the main carrier can flow through the main region through the chip to the drain electrode. The drain electrode may be located on the opposite side of the chip or on a region spaced sideways from the source electrodes. Such a configuration is made using the necessary technology to manufacture a MOS type D device, which allows precise alignment of various electrodes and channels and the use of extremely small channel lengths.
    The molded device is formed in an n-substrate, which has a relatively high resistivity, which is necessary to obtain the required reverse voltage capability of the device. For example, for a four-volt device, the n-region will have a resistivity of about 20 ohms / cm. However, the same necessary resistivity characteristic is due to the relatively high switching resistance value of the MOSFET device when used as a power switch.
    At the top of the central base-; From the material with a relatively low resistivity, a central region can be formed immediately under the gate's silicon oxide, for example, by diffusing n + into the region of this channel without adversely affecting on the characteristics of the reverse voltage device.
    This common channel will have an upper part under the gate silica and even lower below the main part, passing in the direction of the drain electrode. This lower part has the high resistivity required for 76
    The ability to withstand high reverse voltage, and the depth dependent on the required reverse voltage for a given device. Thus, for a 400-volt device, the lower p-region can have a depth of about 35 microns, while for a 90-volt device it has a depth of about 8 microns. Other depths are selected depending on the desired return voltage of the device to provide the required thicker depletion area required to prevent breakdown during the supply voltage state. The upper part of the common channel is made relatively high-conducting p4-area to a depth of the order of 3 to 6 µm. This does not affect the ability of the device to withstand the reverse voltage, however it reduces the on-state resistance per unit area of the device more than doubled.
    Each of the individually spaced areas of the source is multi-, coal-shaped, preferably hexagonal, to ensure a constant gap along the main source lengths located on the surface of the body. An extremely large number of small hexagonal source elements can be formed on the same semiconductor surface for a given device. For example, in a chip having dimensions of the order of 100x140 mils, 6600 hexagonal source areas can be formed to obtain an effective channel width in the order of 22000 mils (558.8mm), so the device gets a very high transmission capacity of large currents.
    The gap between adjacent sources may contain a poly-silicone gate structure or any other gate structure, where the gate structure contacts the device surface with the help of elongated gate contact fingers that ensure good contact over the entire surface of the device.
    Each of the polygonal areas of the source r has a contact with a uniform conductive layer that interacts with individual polygonal sources through the holes in the insulating layer covering
    source areas, these openings can be formed using a standard photolithographic technique for manufacturing a MOS device of type D. Then, the area of contact of the source cushion for the source conductor and the connection area of the cushion pad for the extended fingers of the gate is obtained. The drain connection area is fabricated on the reverse surface of the semiconductor device.
    Many such devices can be formed on a single semiconductor panel and the individual elements can be separated from each other by scratching or by any other suitable method.
    The region of the p-type conductivity, which defines the channel under the gate's silicon oxide, has a relatively deep diffusion part under the source. Thus, the p-type diffusion region will have a large radius of curvature in the epitaxial, forming the device body. This deeper diffusion or deeper transition improves the voltage gradient at the edges of the device and allows the use of devices with higher reverse voltages.
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    权利要求:
    Claims (3)
    [1]
    1. Powerful field-effect transistor with an insulated gate, formed in a semiconductor high-resistance plate containing on the main surface at least one pair of base regions of the first conductivity type, separated from one another, in each of which are high-alloyed regions of the source of the second conductivity type, gate above the main surface between the base areas and the drain area, which includes a high-alloy layer of the second type of conductivity with an electrode, formed on a different surface This high-resistance semiconductor wafer, characterized in that, in order to increase the power, the wafer area limited to the base areas and the main surface is made with a conductivity no less than twice the conductivity of the high-resistance plate and a depth of 3-6 microns.
    [2]
    2. A transistor according to claim 1, characterized in that the source areas have the shape of a polygon.
    [3]
    3. Transistor on PP. 1 and 2, which is characterized by the fact that the source areas have the shape of a hexagon.
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    同族专利:
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    FR2438917A1|1980-05-09|
    NL175358B|1984-05-16|
    SE8503615L|1985-07-26|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US4015278A|1974-11-26|1977-03-29|Fujitsu Ltd.|Field effect semiconductor device|
    JPS52106688A|1976-03-05|1977-09-07|Nec Corp|Field-effect transistor|
    JPS6145396B2|1976-04-29|1986-10-07|Sony Corp|
    US4055884A|1976-12-13|1977-11-01|International Business Machines Corporation|Fabrication of power field effect transistors and the resulting structures|
    JPS5374385A|1976-12-15|1978-07-01|Hitachi Ltd|Manufacture of field effect semiconductor device|
    US4148047A|1978-01-16|1979-04-03|Honeywell Inc.|Semiconductor apparatus|
    JPH05185381A|1992-01-10|1993-07-27|Yuum Kogyo:Kk|Handle for edge-replaceable saw|US4593302B1|1980-08-18|1998-02-03|Int Rectifier Corp|Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide|
    DE3040775C2|1980-10-29|1987-01-15|Siemens Ag, 1000 Berlin Und 8000 Muenchen, De|
    US4412242A|1980-11-17|1983-10-25|International Rectifier Corporation|Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions|
    GB2111745B|1981-12-07|1985-06-19|Philips Electronic Associated|Insulated-gate field-effect transistors|
    CA1188821A|1982-09-03|1985-06-11|Patrick W. Clarke|Power mosfet integrated circuit|
    US4532534A|1982-09-07|1985-07-30|Rca Corporation|MOSFET with perimeter channel|
    DE3346286A1|1982-12-21|1984-06-28|International Rectifier Corp., Los Angeles, Calif.|High-power metal-oxide field-effect transistor semiconductor component|
    JPS59167066A|1983-03-14|1984-09-20|Nissan Motor Co Ltd|Vertical type metal oxide semiconductor field effect transistor|
    JPS6010677A|1983-06-30|1985-01-19|Nissan Motor Co Ltd|Vertical mos transistor|
    JPH0247874A|1988-08-10|1990-02-16|Fuji Electric Co Ltd|Manufacture of mos semiconductor device|
    IT1247293B|1990-05-09|1994-12-12|Int Rectifier Corp|POWER TRANSISTOR DEVICE PRESENTING AN ULTRA-DEEP REGION, AT A GREATER CONCENTRATION|
    US5404040A|1990-12-21|1995-04-04|Siliconix Incorporated|Structure and fabrication of power MOSFETs, including termination structures|
    US5304831A|1990-12-21|1994-04-19|Siliconix Incorporated|Low on-resistance power MOS technology|
    IT1250233B|1991-11-29|1995-04-03|St Microelectronics Srl|PROCEDURE FOR THE MANUFACTURE OF INTEGRATED CIRCUITS IN MOS TECHNOLOGY.|
    DE59208987D1|1992-08-10|1997-11-27|Siemens Ag|Power MOSFET with improved avalanche strength|
    JPH06268227A|1993-03-10|1994-09-22|Hitachi Ltd|Insulated gate bipolar transistor|
    EP0660396B1|1993-12-24|1998-11-04|Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno|Power MOS device chip and package assembly|
    US5798287A|1993-12-24|1998-08-25|Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno|Method for forming a power MOS device chip|
    DE69321966T2|1993-12-24|1999-06-02|Cons Ric Microelettronica|Power semiconductor device|
    EP0665597A1|1994-01-27|1995-08-02|Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe|IGBT and manufacturing process therefore|
    US5817546A|1994-06-23|1998-10-06|Stmicroelectronics S.R.L.|Process of making a MOS-technology power device|
    EP0689238B1|1994-06-23|2002-02-20|STMicroelectronics S.r.l.|MOS-technology power device manufacturing process|
    DE69418037T2|1994-08-02|1999-08-26|St Microelectronics Srl|Power semiconductor device made of MOS technology chips and housing structure|
    US5798554A|1995-02-24|1998-08-25|Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno|MOS-technology power device integrated structure and manufacturing process thereof|
    DE69533134T2|1995-10-30|2005-07-07|Stmicroelectronics S.R.L., Agrate Brianza|Power component of high density in MOS technology|
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    US6228719B1|1995-11-06|2001-05-08|Stmicroelectronics S.R.L.|MOS technology power device with low output resistance and low capacitance, and related manufacturing process|
    DE69518653T2|1995-12-28|2001-04-19|St Microelectronics Srl|MOS technology power arrangement in an integrated structure|
    US5766966A|1996-02-09|1998-06-16|International Rectifier Corporation|Power transistor device having ultra deep increased concentration region|
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    JP4122113B2|1999-06-24|2008-07-23|新電元工業株式会社|High breakdown strength field effect transistor|
    US6344379B1|1999-10-22|2002-02-05|Semiconductor Components Industries Llc|Semiconductor device with an undulating base region and method therefor|
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    JP2006295134A|2005-03-17|2006-10-26|Sanyo Electric Co Ltd|Semiconductor device and method for manufacture|
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    JP5907097B2|2013-03-18|2016-04-20|三菱電機株式会社|Semiconductor device|
    US9508596B2|2014-06-20|2016-11-29|Vishay-Siliconix|Processes used in fabricating a metal-insulator-semiconductor field effect transistor|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US95131078A| true| 1978-10-13|1978-10-13|
    US3866279A| true| 1979-05-14|1979-05-14|
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