• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A POWER SUPPLY UNIT FOR DOMAINED MEMORY, containing two stabilized DC sources and a reference voltage source, characterized in that, in order to increase the reliability of the power supply, it contains a comparison element, two delay elements. And element, NOT element and key element, the inputs of the comparison element are connected respectively to the output of the first stabilized DC source, which is the first code of the power supply unit, and to the output of the reference voltage source, the output of the comparison element is connected to the inputs of the delay elements and the first input element And, the output of the first delay element through the element is NOT connected to the control input of the key element connected to the output of the second stabilized i DC source, which is The second output terminal of the power supply unit and the zero potential bus, the output of the second delay element are connected to the second input of the AND element, the output of which is the control output of the power supply unit.
    公开号:SU1175367A3
    申请号:SU802968562
    申请日:1980-07-18
    公开日:1985-08-23
    发明作者:Имазеки Риодзи；Хаттори Мазавоки
    申请人:Фудзицу Фанук Лимитед (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to computing and can be used in the development of apomical devices on cylindrical magnetic domains (CMD). The purpose of the invention is to increase the reliability of the power supply unit for the domain memory. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a timing diagram for increasing and decreasing output signals. The power supply unit for the domain memory contains two stabilized DC power supplies 1 and 2 and a reference voltage source 3, a reference element 4, the inputs of which are connected to sources 1 and 3, and the output through the first delay element 5 is connected to the input of the HE element 6 and the input enable power supply source 2, as well as through the second delay element 8 to one input element And 9. The output element NOT 6 is connected to the control input of the key element 10, performed on the thyristor. The inputs of the stabilized sources 1-3 through the switch 11 are connected to the primary power source 12. The power supply unit for the domain memory generates three output signals at its outputs: the memory address enable signal Me, which is fed to the domain memory control unit, the first DC voltage signal Е, the inputs to the domain mic assembly and the unit control of the domain memory, and the second voltage signal of the current EJ, which arrives at the excitation roll of the rotating magnetic field. In order to ensure reliable operation of the domain memory during emergency shutdown of the primary power source, these output signals must increase (when the primary power source is turned on) and kill (when it is turned off) in certain sequences (Fig. 2). 1,672 The proposed power supply operates as follows. When the switch 11 is turned on, the AC voltage is applied to the inputs of sources 1 - 3. A signal E is generated at the output of source 1. Since the signal at input 7 of source 2 is zero, the output signal EJ is not present at this time. After the output signal EJ becomes greater than the reference voltage V, the signal at the output of the comparison element 4 takes on the value of logic 1, and after some time t determined by the delay element 5 is fed to the enable input 7 of source 2 and through the HE 6 element on the control input of the thyristor 10, lock it. The voltage Ej at the output of source 2 increases some time tj to its nominal value Vj. Finally, at the output of the And 9 element, the signal takes the value of logical 1 during the time interval tj defined by the delay element 8. Thus, the output signals E (,, E j and Me) are generated in the required sequence. When the primary power source 12 is disconnected in an emergency, the signals E and Ej begin to gradually decrease. As soon as the signal E becomes less than the reference voltage V, the And 9 element the signal closes and the signal Me takes on the value of a logical O. Then, through the time interval t, the signal at the enable input 7 of source 2 is turned off and the thyristor 10 is turned on, after which the signal E (quickly decreases to zero). The output signal E continues to decrease gradually and after a certain time interval t ((t (0) stanovit-;. with an equal lower allowable value V, thus turning off sequence provided correct output signals.
    权利要求:
    Claims (1)
    [1]
    POWER SUPPLY FOR A DOMAIN MEMORY, containing two stabilized DC sources and a reference voltage source, characterized in that, with a circuit to increase the reliability of the power supply, it contains a comparison element, two delay elements, an AND element, a NOT element and a key element, inputs of the comparison element respectively connected to the output of the first stabilized DC source, which is the first output of the power supply, and to the output of the reference voltage source, the output of the comparison element is connected to the input the delay elements and the first input of the AND element, the output of the first delay element through the element is NOT connected to the control input of the key element connected to the output of the second stabilized DC source, which is the second output of the power supply, and the zero potential bus, the output of the second delay element is connected to the second input of the element And, the output of which is the control output of the power supply.
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    同族专利:
    公开号 | 公开日
    EP0023124B1|1986-01-22|
    JPS5855591B2|1983-12-10|
    US4327422A|1982-04-27|
    EP0023124A3|1981-03-25|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    GB1032081A|1961-09-13|1966-06-08|English Electric Co Ltd|Electric supply and control means for an electric digital computer|
    US3560861A|1969-01-16|1971-02-02|Motorola Inc|Electronic sensing system for selectively energizing and de-energizing apparatus|
    US3980935A|1974-12-16|1976-09-14|Worst Bernard I|Volatile memory support system|JPS6031036B2|1980-07-14|1985-07-19|Fanuc Ltd|
    JPS6242418B2|1981-06-18|1987-09-08|Fujitsu Ltd|
    JPH0235328B2|1981-07-03|1990-08-09|Fujitsu Ltd|
    JPS5974434U|1982-11-05|1984-05-21|
    FR2548381B1|1983-06-17|1985-11-15|Telemecanique Electrique|METHOD FOR MEASURING THE AUTONOMY OF A CUT-OUT POWER SUPPLY AND DEVICE FOR IMPLEMENTING SAME|
    JPS61198489A|1985-02-28|1986-09-02|Fujitsu Ltd|Bubble cassette device|
    JP2000215112A|1998-11-20|2000-08-04|Sony Computer Entertainment Inc|Electronic equipment and low-voltage detecting method|
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    US8421479B2|2009-06-30|2013-04-16|Navisense|Pulsed echo propagation device and method for measuring a parameter|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP54091998A|JPS5855591B2|1979-07-19|1979-07-19|
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