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    • 专利摘要:

    公开号:SE533962C2
    申请号:SE0900780
    申请日:2009-06-09
    公开日:2011-03-15
    发明作者:Yuuichi Takeuchi；Rajesh Kumar Malhan
    申请人:Denso Corp；
    IPC主号:
    专利说明:

    53 30 963 962 In the structure shown in Japanese Patent Application Laid-Open No. 2004-79576 breakthrough of a transistor portion can be avoided because the Iavingen breakthrough can be caused to occur in the outermost p-type base region or the p-type diffusion region in the outer region. However, if L-load energy is further increased or a chip size is increased, a path of conduction of current surge energy in a conduction form is concentrated on the outer region and the outermost region of the cell region. Therefore, a problem arises when the parasitic bipolar transistor is turned on or an element breakthrough is caused by heat due to power concentration. Therefore, it is preferable that avalanche breakdown occurs throughout the cell area and that the parasitic bipolar transistor is not turned on.
    The structure shown in published Japanese patent application no. H11-330091 can improve an L-load resistance compared to a structure that does not have a deep p-type layer.
    However, since a breakthrough occurs in the outermost cell region, the L-load resistance is insufficient. Therefore, the problem of breakthrough occurring in the outermost cell region, when the current rushing energy is increased, can not be solved. Furthermore, a shape of the deep p-type layer depends on a shape of a pre-formed ditch. Since the trench is formed by etching, one in the form of a sharp corner of the trench is transferred to the deep p-type layer. Therefore, a problem arises with an electric field concentration occurring in the sharp portion and a reduction of a strength against breakthrough of electric fields.
    In view of the above, it is an object to provide a SiC semiconductor device having an L load surge resistance and an electric field breakdown strength and also to provide a method of manufacturing the same.
    According to a first consideration of the present invention, a semiconductor device of silicon carbide comprises a silicon carbide substrate, a drift layer of silicon carbide, a semiconductor element, a breakdown-resistant region and a deep layer. The substrate has a first or second type of conductivity. The operating layer is formed on a surface of the substrate and has a first type of conductivity. The semiconductor element is formed in a cell area of the substrate and has a vertical structure to allow flow of an electric current between a front electrode formed on a front side of the substrate and a back side electrode formed on a back side of the substrate. The penetrating region surrounds the periphery of the cell area. The deep layer has a second type of conductivity and reaches the operating layer. The deep layer is formed in each of a central region of the cell region and a junction region surrounding the central region for interconnection of the central region and the permeation resistant region.
    The deep layer causes a breakdown voltage of the center region to be lower than a breakdown voltage of the junction region. The breakthrough voltage layer of the junction area is less than a breakdown voltage of the breakthrough resistant area. According to another consideration of the present invention, a method of manufacturing a semiconductor device of silicon carbide comprises arranging, preparing or providing a silicon carbide substrate having a first or second type of conductivity. The method further comprises forming an operating layer having a first type of conductivity on a surface of substrate. The method further comprises forming a semiconductor element in a cell region of the substrate. The semiconductor element has a vertical structure to allow flow of an electric current between a front electrode formed on a front side of the substrate and a back side electrode formed on a back side of the substrate. The method further comprises forming a breakthrough resistant area for surrounding the periphery of the cell area.
    The method further comprises forming a trench in each of a central region and a connecting region of the cell region to reach a predetermined depth of the operating layer.
    The connection area surrounds and the breakthrough resistant area. The step of forming the ditch involves producing the width of a ditch formed in the center area larger than the width of a ditch formed in the connecting area.
    The method further comprises forming a deep layer in each of the ditches in the central region and the connecting area by epitaxial growth of a first layer having a first type of central region for connecting the central region of conductivity or a second type of conductivity in the ditches and by epitaxial growth of a second layer on the first layer in the ditches. The first layer has an impurity concentration that is less than an impurity concentration of the second layer.
    The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic top plan view of a trench gate MOSFET according to a first embodiment of the present invention; ; Fig. 2 is a schematic cross-sectional view taken along the line A-A in Fig. 1; Figs. 3A-3D are schematic cross-sectional views of manufacturing processes for said trench gate MOSFET shown in Fig. 1; Fig. 4 is a diagram showing the result of an experiment in which a ratio between a width of a ditch and a growth fraction of an impurity layer was measured by changing the width; Fig. 5A is a schematic cross-sectional view of a portion near the ditch having a small width when epitaxial growth is performed for a predetermined period of time, and Fig. 5B is a schematic cross-sectional view of the portion near the ditch having a large width when epitaxial growth is performed during the predetermined growth period; Fig. 6 is a schematic cross-sectional view of a planar MOSFET according to a second embodiment of the present invention; Figs. 7A-7D are schematic cross-sectional views of manufacturing processes for the planar MOSFET shown in Fig. 6; Fig. 8 is a schematic cross-sectional view of a JBS according to a third embodiment of the present invention; Figs. 9A-9D are schematic cross-sectional views of manufacturing processes for the JBS shown in Fig. 8; Fig. 10 is a schematic cross-sectional view of a trench gate MOSFET according to a fourth embodiment of the present invention; and Fig. 1 1A - 11 D are schematic cross-sectional views of manufacturing processes for the trench gate MOSFET shown in Fig. 10.
    Embodiments of the invention are described below with reference to the drawings. Throughout the embodiments, like symbols are used for like or corresponding parts throughout the drawings.
    (First Embodiment) A first embodiment of the present invention is described. Here, a trench gate MOSFET is described as an element formed or fabricated in a SiC semiconductor device. Figs. T and 2 are schematic views showing a trench gate MOSFET according to the present embodiment. Fig. 1 is a schematic layout view from above of the trench gate MOSFET and Fig. 2 is a schematic cross-sectional view along the line A-A in Fig. 1.
    As shown in Fig. 1, in the MOSFET of the present embodiment, an inner region of a chip is defined as a cell region R1, and an outer region of the chip is defined as a breakthrough resistant region R2. The cell region R1 comprises a central region R1a located in the center of the chip and a connecting region R1b located between the central region R1a and the breakthrough resistant region R2 to act as a connecting region to the breakthrough resistant region R2. Cells are formed in the cell region R1. A cell formed in the central region R1a has a structure different from a structure of a cell formed in the junction region R1b.
    As specifically shown in Fig. 2, the MOSFET is prepared using a SiC substrate 1 type. The n-type substrate 1 has, for example, a thickness of about 300 μm and is doped with an n-type impurity, such as nitrogen with a high concentration of about 1, ox 10 ° / cm 3.
    An nlt type SiC operating layer 2 is formed on a surface of the nï type substrate 1. The nltype operating layer 2 has, for example, a thickness of from about 10 [mu] m to about 15 [mu] m and is doped with an n-type impurity, such as nitrogen, having a concentration of from about 3, Ox10 is lower than the concentration of the n-type substrate 1. At a surface portion of the n 'type operating layer 2, an element structure of the MOSFET is formed in the cell region R1, and an outer breakthrough structure is formed in the breakthrough region R2.
    That is, in the cell region R1, at the surface portion of the n 'type operating layer 2, a p-type base region 3 is formed doped with a p-type impurity, such as boron or aluminum. Furthermore, an n ° type emitter region 4 is doped with an n-type impurity, such as nitrogen with a high concentration formed on the p-type base region 3.
    For example, the p-type base region 3 has a p-type impurity concentration of from about 5.0x10 16 / cm 3 to about 2.0x10 19 / cm 3 and has a thickness of about 2.0 μm.
    The n-type emitter region 4 has, for example, an n-type impurity concentration (surface concentration) of about 1.0x10 2 ° / cm 3 at its surface portion and has a thickness of about 0.5 μm. 53 15 962 A ditch 5 is formed to reach the n '-type operating layer 2 by penetrating the p-type base region 3 and the nï-type emitter region 4. A deep layer 6 of p-type is formed in the ditch 5.
    The ditch 5 is formed for each cell in each of the center region R1a and the connection region R1b. The depth of the ditch 5 is the same between in the central area R1a and in the connecting area R1 b. For example, the depth of the ditch 5 is 4.5 μm or more. The width of the trench 5 is different between in the central area R1a and in the connecting area R1b. The width of the trench 5a formed in the central area R1a is greater than the width of the trench 5b formed in the connecting area R1b. for example, the ditch 5a has a width of from about 1.0 μm to about 1.5 μm and the ditch 5b has a width of from about 0.5 μm to about 1.0 μm.
    The p-type deep layer 6 is formed to fill each ditch 5. The p-type deep layer 6 comprises a first layer 6a formed mainly on a bottom of the ditch 5 and a second layer 6b formed on the first layer 6a. Deviating from a corner of a bottom of the first layer 6a, a surface shape of the first layer 6a is rounded. A bottom of the second layer 6b of the first layer 6a is rounded.
    The first and second layers 6a, 6b have different p-type impurity concentrations, and the first layer 6a has a concentration lower than that of the second layer 6b. For example, the first layer 6a has an impurity concentration of 1x10 7 ° / cm 3 or less, and the second layer 6b has an impurity concentration of from 5.0x10 7 ° / cm 3 to 5.0x10 2 ° / cm 3. Therefore, the second layer 6b, which has a higher concentration, serves as a deep layer for drawing or conducting a breakthrough current.
    The thickness of the first layer 6a from the bottom of the ditch 5 differs between in the middle area R1a and in the connecting area R1b. The thickness of the first layer 6a formed in the trench 5a in the central region R1a is greater than the thickness of the first layer 6a formed in the trench 5b of the connecting region R1b. For example, the first layer 6a formed in the trench 5a has a thickness of from about 0.4 μm to 0.5 μm, and the first layer 6a formed in the trench 5b has a thickness of from about 0.5 μm to about 0.6 μm.
    Furthermore, a ditch 7 is formed to reach the operating layer 2 n 'type by penetrating the base region 3 of p-tyo and the emitter region 4 of n type. For example, the ditch 7 has a width of from about 1.4 microns to about 2.0 microns and a depth of about 3.0 microns or more (eg, 3.5 microns).
    The p-type base region 3 and the n 'type emitter region 4 are located to be in contact with a side surface of the ditch 7. An inner surface of the ditch 7 is covered with a gate oxide film 8. The ditch 7 10 15 20 25 30 533 962 is filled with a gate electrode 9 formed on a surface of the gate oxide film 8. The gate electrode 9 is made of doped polysilicon. The gate oxide film 8 is formed by thermal oxidation of the inner surface of the trench 7. The gate oxide film 8 has a uniform thickness of about 100 nm. In this way, a trench gate structure is formed. In the present embodiment, the gate oxide film 8 is used as a gate insulating film. Alternatively, another insulating film, such as a silicon oxide / silicon nitride / silicon oxide (ONO) film, may be used as a gate insulating film.
    An emitter electrode 11 and a gate wire or wire (not shown) are formed on surfaces of the n-type emitter region 4, the p-type deep layer 6 and the gate electrode 9.
    The emitter electrode 11 and the gate wire are made of several metal materials (eg Ni / Al).
    The emitter electrode 11 and the gate wire may be in ohmic contact with an n-type SiC (especially the n "type emitter region 4 and the n-doped gate electrode 9).
    The emitter electrode 11 and the gate wire may be in barrier-free contact with a p-type SiC (especially the p-type deep layer 6 and the p-type gate electrode 9).
    The emitter electrode 11 and the gate wire are formed on an interlayer insulating film 12 for electrical insulation. The emitter electrode 11 is in electrical contact with the emitter region 4 of the n * type and the deep layer 6 of the p-type through a contact hole formed in the interlayer insulating film 12. The gate wire is in electrical contact with the gate electrode 9 via the contact hole.
    A drain electrode 13 is formed on a back side of the nite-type substrate 1 and in electrical contact with the nite-type substrate 1. In this way, an element structure of the MOSFET is formed.
    A ditch 20 is formed in the breakthrough resistant area R2. The ditch 20 reaches the n-type drift layer 2 by penetrating the p-type base region 3 and the n ° type emitter region 4 formed in the cell region R1. A RESURF (reduced surface field) layer 21 is in contact with the p-type base area 3 at a side surface of the ditch 20 and extends towards a bottom of the ditch 20. Ie. The p-type RESURF layer 21 extends toward the outside of the cell region R1. A n-type contact area 22 is further formed at the bottom of the ditch 20 and located further away from the cell area R1 than the p-type RESURF layer 21 in a direction toward the outside cell area R1. The p-type RESURF layer 21 and the nite-type contact area 22 surround the entire periphery of the cell area R1. The p-type RESURF layer 21 is in electrical contact with an outer electrode 23 via the contact hole formed in the interlayer insulating film 12. The nf-type contact area 22 is in electrical contact with an equipotential ring electrode (Equi-Potential Ring (EQR) 10 15 20 25 30 35 533 962 electrode) 24 via the contact hole. In this way, the breakthrough resistant region R2 of the MOSFET is formed.
    In the trench gate MOSFET, the depth of the second layer 6b of the p-type deep layer 6 is greater in the center region R1a than in the junction region R1b. Therefore, the following relationship exists between a drain breakdown voltage BV (R1a) of the center region R1a, a drain breakdown voltage BV (R1b) of R1b and a connection region drain breakthrough voltage BV (R2) of the breakthrough resistant region R2: BV (R1a) <BV ( R1b) <.
    BV (R2).
    As described above, the drain breakdown voltage BV (R1a) of the center region R1a, which is not in contact with the breakthrough resistant region R2, is less than that of any other region. Therefore, a breakthrough occurs in a planar form over the entire central area R1a, not in line form, so that a breakthrough current can flow in a planar form over a wide area.
    Consequently, the surface density of the breakthrough current becomes small, so that an inductive load resistance can be improved.
    When in the layout shown in Fig. 1 the surface of the central area R1a is larger than that of the connecting area R1b, the breakthrough current can flow over a much wider surface. With such an approach, the surface density of the breakthrough current becomes much smaller, so that the inductive load resistance can be improved. Furthermore, in the present embodiment, the width of the deep layer 6 p-type is larger in the central region R1a than in the connecting region R1b. In such an approach, a resistance of the deep layer 6 of the p-type is reduced to a smaller value, so that the breakthrough current can be effectively conducted (drawn).
    Furthermore, the second layer 6b of the p-type deep layer 6 serves in practice as a deep layer. Since the bottom of the second layer 6b is rounded, it is possible to prevent an electric field concentration caused when the bottom of the second layer 6b is sharp or pointed. Accordingly, it is possible to prevent a reduction of a breakthrough voltage due to the electric field concentration. Furthermore, since the first layer 6a has a lower concentration than the second layer 6b, the first layer 6a serves as an electric field-relieving layer, so that an ideal breakthrough-resistant structure can be achieved. The following describes a method of manufacturing the french gate MOSFET shown in Figs. 1 and 2. Figs. 3A-3D show schematic cross-sectional views of manufacturing processes for the trench gate MOSFET shown in Figs. Fig.1. The procedure is described below with reference to 3A-3D.
    (Process shown in Fig. 3A) First, the n-type substrate 1 is provided or prepared with a thickness of, for example, about 300 μm and doped with an n-type impurity, such as nitrogen having a concentration of, for example, about 1, Ox101 ° / cm 3. Thereafter, on the surface of the n-type substrate 1 by epitaxial growth, the n-type SiC drift layer 2, the p-type base region 3 and the n-type emitter region 4 are formed. For example, the n 'type operating layer 2 has a thickness of from about 10 microns to about 15 microns and is doped with an n-type impurity, such as nitrogen, having a concentration of from about about 10 .mu.m to about 70 .mu.m. . For example, the p-type base region 3 has a thickness of about 2.0 microns and is doped with a p-type impurity, such as boron or aluminum, having a concentration of from about 5.0x10 15 / cm 3 to about 2.0x10 19 / cm 3. For example, the emitter region 4 of the n * type has a thickness of about 0.5 μm and is doped with an n-type impurity, such as nitrogen with a concentration (surface concentration) of about 1.0x102 ° / cm 3. (Process shown in FIG. 3B) After an etching mask, which is not shown in the drawings, has been formed on the emitter region 4 of n-type, an opening in the etching mask is formed at a position where the ditch 5 is to be formed. Thereafter, an anisotropic etching is performed by using the etching mask to form the trench 5 to a depth of about 4.5 microns or more. If necessary, the following can be performed on the anisotropic etching an isotropic etching and a sacrificial oxidation. In this way, the ditch 5a having a width of from about 1.0 μm to about 1.5 μm is formed in the central region R 1a, and the ditch 5b having a width of from about 0.5 μm to about 1.0 μm is formed in the connecting region R1b. Then the etching mask is removed.
    (Process shown in FIG. 3C) For example, material gas is supplied to fill each ditch at a temperature of 1600 ° C or more, so that a p-type impurity layer can epitaxially grow at a growth rate of 2.5 μm / h or less. In this way, the deep layer 6 of p-type is formed.
    In particular, the second layer 6b grows having an impurity concentration of about e.g. from 5, 10x10 of about e.g. 1.0x101 ° / cm3 or less, grows epitaxially over a predetermined period of time.
    In this way, the thickness of the first layer 6a formed in the trench Sa in the central region R1a becomes larger than the thickness of the first layer 6a formed in the trench 5b in the connecting region R1b.
    The reason for this is described with reference to Figs. 4, 5A and 5B.
    Fig. 4 is a diagram showing the result of an experiment in which a ratio between a width L of a ditch 100 and a growth portion G of an impurity layer 101 was measured by changing the width L. Fig. 5A is a schematic cross-sectional view of a portion near the ditch 100 having a narrow or narrow width (L = 1pm) when the epitaxial growth is performed for a predetermined period of time. Fig. SB is a schematic cross-sectional view of a portion near the ditch 100 having a large width (L = 2.5 μm) when an epitaxial growth is performed for a predetermined period of time.
    As shown in Fig. 4, the experimental result indicates that the growth rate increases with a decrease in the width L due to migration effect when the ditch 100 having an aspect ratio of 2 or more is filled with the impurity layer 101. Further, as shown in Fig. 5A and SB, the growth portion G of the impurity layer 101 on a bottom of the ditch 100 is larger, since the width L of the ditch 100 is narrower or smaller. Furthermore, due to migration effect, a surface of the impurity layer 101 is rounded at the bottom of the ditch 100.
    Therefore, as described above, the thickness of the first layer 6a formed on the bottom of the ditch 5a in the middle region R1a may be greater than the thickness of the first layer 6a formed on the bottom of the ditch 5b in the connecting region R1b by changing the widths of the ditches Sa, 5b. Since the second layer 6b is formed on the first layer 6a, the depth of the second layer 6b becomes greater in the central region R1a than in the connecting region R1b. Furthermore, the bottom of each second layer 6b is rounded.
    Thereafter, a planing process is performed to remove unnecessary portions of the first and second layers 6a, 6b formed at the outside of the ditch 5. Since a substrate surface becomes flat through the planing process, device processing processes in a subsequent process, such as a photolithographic process, can be easily performed.
    (Process shown in FIG. 3D) After an etching mask, not shown in the drawings, is formed on the p-type base region 3, the n-type emitter region 4 and the p-type deep layer 6. , is formed in an opening in the etching mask at a position where the trench 20 is to be formed in the breakthrough-resistant area R2.
    Thereafter, an anisotropic etching is performed by using the etching mask to form the trench 20. If necessary, an isotropic etching and sacrificial oxidation following the anisotropic etching can be performed. In this way, the ditch 20 is formed in the breakthrough-resistant region R2. Then the etching mask is removed. Then, after a mask (not shown) is placed, having an opening at a position where the p-type RESURF layer 21 is to be formed, an ion implantation of a p-type impurity is performed. Then, the mask used to form the p-type RESURF layer is removed. Furthermore, ion implantation of an n-type impurity is performed after another mask (not shown) is placed, which has an opening at a position where the n * -type contact area 22 is to be formed. Thereafter, a thermal treatment is performed for activation, so that the p-type RESURF layer 21 and the nite-type contact area 22 can be formed.
    Furthermore, after an etching mask, which is not shown in the drawings, is formed on the p-type base area 3, the n-type emitter area 4 and the p-type deep layer 6, an opening is formed in the etching mask at a position where the trench 7 for trench the gate structure in the cell area R1 is to be formed. Thereafter, an anisotropic etching is performed by using the etching mask to form the ditch 7. If necessary, the following can be performed on the anisotropic etching an isotropic etching and a sacrificial oxidation. In this way the ditch 7 is formed. Then the etching mask is removed.
    Thereafter, a process for forming a gate oxide film is formed for forming the gate oxide film 8. In particular, the gate oxide film 8 is formed by gate oxidation (thermal oxidation) effected by a pyrogenic process in a wet atmosphere.
    Thereafter, a polysilicon layer doped with an n-type impurity and having a thickness of about 1 μm is formed at its flat portion on the gate oxide film 8 at a temperature of about 600 ° C to fill the ditch 7. An etch back process is then performed. ), so that the gate oxide film 8 and the gate electrode 9 can be left in the ditch 7.
    Processes that follow the processes described above are not shown in the drawings, since the following processes are the same as conventional processes. After the interlayer insulating film 12 is formed, by a patterning process in the interlayer insulating film 12, a contact hole leading to the emitter region 4 of the n * type and the deep layer 6 of the p-type and a p contact hole leading to the p-type RESURF layer 21 and the n * -type contact area 22. Furthermore, a contact hole leading to the gate electrode 9 is formed on a deviating cross section through the patterning process. Thereafter, an electrode material is applied to fill the contact holes and then patterned so that the emitter electrode 11, the gate wire, the outer electrode 23 and the EQR electrode 24 can be formed. Finally, the drain electrode 13 is formed on the back of the n 'type substrate 1. In this way, the MOSFET shown in Fig. 1 becomes complete. According to the manufacturing method described above, although the depth of the second layer 6b differs between in the central region R1a and in the connecting region R1b, the p-type deep layer 6 can be formed in the same process. Therefore, the manufacturing processes of the MOSFET can be simplified. Furthermore, the center region R1a and the connection area R1b with different drain breakdown voltages can be formed with good controllability, since they are formed in the same process.
    Furthermore, since the surface of the first layer 6a formed below the second layer 6b is rounded by migration effect, the bottom of the second layer 6b may be rounded. It is therefore possible to prevent an electric field concentration caused when the bottom of the second layer 6b is sharp or pointed. Consequently, it is possible to prevent a reduction of breakthrough voltage due to the electric field concentration.
    In the present embodiment, the first layer 6a and the second layer 6b are further formed in different processes. In such an approach, impurity concentrations of the first layer 6a and the second layer 6b may be regulated or controlled, so that the first layer 6a and the layer Bb may have different. Therefore, the impurity concentration of the first layer 6a may be lower than the impurity concentration of the second layer 6b. so that the first layer 6a can serve as an electric field relieving layer. Consequently, an ideal breakthrough structure or construction can be obtained. In the present embodiment, the first layer 6a is made of p-type SiC, so that the first layer 6a can serve as an electric field-relieving layer. Alternatively, the first layer 6a may be made of n-type SiC having a low impurity concentration (eg, equal to the impurity concentration of the nl-type operating layer 2). Even when the first layer 6a is made of n-type SiC, the depth of the second layer 6b may be different between in the middle region R1a and in the connection area R1b, and the bottom of the second layer 6b may also be rounded. Thereby, the advantages described above can be achieved. the other impurity concentrations. Furthermore, since the first layer 6a and the second layer 6b are formed successively, the time required to increase and decrease a temperature for epitaxial growth can be reduced. The second layer 6b is not exposed to the atmosphere after the first layer 6a is formed. Therefore, a defect in the second layer Gb can be reduced.
    The process for forming the p-type deep layer 6 is carried out at a high temperature of about 1600 ° C. However, the process for forming the p-type deep layer 6 is carried out before the ditch 7, the gate oxide film 8 and the the electrode 9 is formed. There is therefore no need to protect the trench gate structure. Accordingly, a process can be used to form a conventional trench gate structure.
    (Second Embodiment) A second embodiment of the present invention is described. A difference between the first and second embodiments consists in an element structure of the MOSFET. Since a base structure is the same between the first and second embodiments, only the difference is described.
    Fig. 6 is a schematic cross-sectional view of a MOSFET according to the present embodiment. As shown in Fig. 6, the MOSFET of the second embodiment has a planar structure, not a trench gate structure.
    In particular, in the MOSFET according to the present invention, several or multiple p-type base regions 3 are arranged at predetermined intervals on the surface portion of the n '-type operating layer 2 formed on the surface of the n-type substrate 1. The n-type emitter region 4 is formed on the surface portion of each p-type base region 3 with the exception of the p-type outer base region 3 formed in the connection region R1 b.
    A surface portion of the p-type base region 3 located between the n-type operating layer 2 and the n-type emitter region 4 acts as a channel region. The gate electrode 9 is formed via the gate oxide film 8 on at least the surface of the channel area.
    Deviating from the first embodiment, the trench 20 is not formed in the breakthrough-resistant area R2 and the p-type RESURF layer 21, and the n-type contact area 22 is formed on the surface portion of the n-type operating layer 2. Accordingly, the same structure as in the first embodiment can be applied to the planar MOSFET and the same advantage as in the first embodiment can be achieved.
    In the following, a method for manufacturing the planar MOSFET shown in Fig. 6. Figs. 7A-7D show cross-sectional views of manufacturing processes for the planar MOSFET shown in Fig. 6. In the following, the method is described with reference to Figs. 7A-7D. .
    First, in a process shown in Fig. 7A, the n 'type drift layer 2 is formed on the surface of the n * type substrate 1.
    Then, in a process shown in Fig. 7B, after a mask (not shown) has been placed having an opening at a position where the p-type base region 3 is to be formed, an ion implantation of a p-type impurity is performed. Then the mask used to form the p-type base region 3 is removed. Furthermore, after another mask (not shown) has been placed, having an aperture at a position where the n-type emitter region 4 is to be formed, an ion implantation of an n-type impurity is performed. Thereafter, a thermal treatment is performed for activation, so that the p-type base region 3 and the n-type emitter region 4 can be formed.
    In addition, after an etching mask, which is not shown in the drawings, has been formed on the operating layer 2 of the n-type, the base region 3 of the p-type, and the emitter region 4 of the n 'type, an opening is formed in the etching mask at a position where the ditch 5 is to be formed. Ie. the opening is formed at a position corresponding to the center of the base region 3 of the p-type and the emitter region 4 of the n "type. If necessary, an isotropic etching and a sacrificial oxidation following the anisotropic etching can be performed: In this way, the ditch Sa having a width of from about 0.8 .mu.m to about 1.2 .mu.m is formed in the central region R1a, and the ditch 5b having a width of from about 0. .5 μm to about 0.8 μm is formed in the joint area R1b. Then the etching mask is removed.
    Then, in a process shown in Fig. 7C, the p-type deep layer having the first and second layers 6a, 6b in the trench 5 is formed by performing the process shown in Fig. 3C of the first embodiment.
    Then, in a process shown in Fig. 7D, after the p-type RESURF layer 21 and the n * -type contact area 22 have been formed in a manner similar to that shown in Fig. 3D, the gate oxide film 8 is formed by a gate oxidation. Further, a polysilicon layer doped with an n-type impurity is formed and then patterned to form the gate electrode 9. Thereafter, the interlayer insulating film 12, the contact holes, the emitter electrode 11, the gate wire or wire, the outer electrode 23 and the EQR electrode 24. In this way, the planar MOSFET shown in Fig. 6 is completed.
    By forming the ditch 5 and the p-type deep layer 6 by the above-described manufacturing method, the same advantage as achieved by the manufacturing method shown in the first embodiment can be achieved.
    (Third Embodiment) A third embodiment of the present invention is described. In the first and second MOSFETs, the vertical SiC semiconductor device. In the present embodiment, instead, a junction barrier Schottky diode (hereinafter referred to as "JBS") is formed as a vertical structural element in the SiC semiconductor device. the embodiments are formed as a structural element 'in Fig. 8 is a schematic cross-sectional view of the JBS according to the present invention.
    As shown in Fig. 8, an operating layer 2 of n 'type and of SiC is formed on a surface of a n 31 type substrate 31. For example, the n-type substrate 31 has an impurity concentration of about from 2x10 18 / cm 3 to about 1x10 2 A Schottky electrode 33 and a surface electrode 34 are formed on a surface of the n-type operating layer 32. The Schottky electrode 33 is made of, for example, molybdenum (Mo) or titanium (Ti). The surface electrode 34 is prohibited with the Schottky electrode 33. Furthermore, a back electrode 35 is formed on a back side of the n * type substrate 31 to be in barrier-free contact with the back side of the n type type substrate 31. For example, the back electrode 35 is made of nickel, titanium, molybdenum or tungsten.
    The breakthrough resistant area R2 has the same structure as that of the second embodiment. Ie. deviating from the first embodiment, the trench 20 is not formed in the breakthrough resistant area R2, and the p-type RESURF layer 21 and the n-type contact area 22 are formed on the surface portion of the n '-type operating layer 32. The p-type RESURF screen 21 is electrically connected to the outer electrode 23 via a contact hole formed in the interlayer insulating film 12. The n-type contact area 22 is electrically connected to the EQR electrode 24 via a contact hole formed in the interlayer insulating film 12.
    As with the first and second embodiments, the JBS has the p-type deep layer 6. The width of the p-type deep layer 6 is larger in the central region R1a than in the junction region R1b. The thickness of the first layer 6a is furthermore greater in the connecting area R1b than in the central area R1a. Since the depth of the ditch 5 is equal between in the central region R1a and the connecting region R1b, the thickness of the second layer 6b is greater in the central region R1a than in the connecting region R1b.
    As described above, the p-type deep layer 6 of the JBS has the same structure as that of the first and second embodiments. Therefore, the same advantage can be obtained as in the first and second embodiments. In the following a method for producing the JBS shown in Fig. 8. Figs. 9A-9D are schematic cross-sectional views showing manufacturing processes for the JBS shown in Fig. 8. The manufacturing process is described below. for the JBS shown in Fig. 8 with reference to Figs. 9A-9D.
    First, in a process shown in Fig. 9A, the n 'type drift layer 32 is formed on the surface of the n' type substrate 31. Then, in a process shown in Fig. 9B, after an etching mask, which is not shown in the drawings, has been formed on the nltype operating layer 32, an opening is formed in the etching mask at a position where the trench 5 is to be formed. Thereafter, an anisotropic etching is performed by using the etching mask to form the trench 5 having a depth of, for example, about 1.5 microns or more. If necessary, an isotropic etching and a sacrificial oxidation can be performed following the anisotropic etching. In this way, the ditch 5a having a width of about 0.7 .mu.m is formed in the central region R1a, and the ditch 5b having a width of about 0.4 .mu.m is formed in the connecting region R1b. Then the etching mask is removed.
    Then, in a process shown in Figs. 9C, the p-type deep layer 6 having the first and second layers 6a, 6b in the trench 5 is formed by performing the process shown in Fig. 3C of the first embodiment.
    Then, in a process shown in Fig. 9D, the p-type RESURF layer 21, the n-type contact area 22, the interlayer insulating film 12, the contact hole, the back electrode 35, the Schottky electrode 33, the surface electrode 34, the outer electrode 23 and EQR are formed. electrode 24. In this way, the JBS shown in Fig. 8 is completed.
    By forming the p-type ditch 5 and the deep layer 6 by the manufacturing method described above, the same advantage as obtained by the manufacturing method shown in the first embodiment can be obtained. (15 Fourth Embodiment) A fourth embodiment of the present invention is described. A difference between the first and fourth embodiments is an element structure of the MOSFET. Since a basic structure is similar between the first and fourth embodiments, only the difference will be described.
    Fig. 10 is a schematic cross-sectional view of a trench gate MOSFET according to the present embodiment. As shown in Fig. 10, in the present embodiment, a ditch 5c is formed at the bottom of the ditch 7, which provides a trench gate structure. The p-type layer 6 is formed in the ditch 5c.
    It is noted that the ditch 5c has the same width as the ditch 5b regardless of whether the ditch 5c is located in the central area R1a or the connecting area R1b. The depth of the second layer 6b in the trench 5a located between the trench gate structures is greater than the depth of the second layer 6b in the trench 5c.
    The deep p-type layer 6 located below the trench gate structure can reduce an electric field acting on the gate oxide film 8 at the corner of the bottom of the ditch 7 at the time of "OFF". Consequently, breakthrough of the gate oxide film 8 can be prevented. Furthermore, since the p-type deep layer extends from the p-type base region 3 between the trench gate structures, a current is conducted or transported through the p-type deep layer 6, so that an inductive load resistance can be improved.
    However, if a breakthrough first occurs in the p-type deep layer 6 located below the trench gate structure, a breakthrough current flows along a surface of the gate oxide film and reduces the useful life of the gate oxide film 8. As described above, since the depth of the second layer 6b in the trench 5a located between the trench-gate structures is greater than the depth of the second layer 6b in the trench 5c located below the trench-gate structure, the breakthrough is preferably caused to occur in the deep layer 6 of p-type format in the trench 5a located between the trench gate structures. In such an approach, it is possible to prevent the breakthrough current from flowing along the surface of the gate oxide film 8, so that the breakthrough current can be conducted without reducing the useful life of the gate oxide film 8.
    In the following, a method for manufacturing the trench gate MOSFET shown in Fig. 10. Figs. 11A-11D show cross-sectional views of manufacturing processes for the trench gate MOSFET shown in Fig. 10. The method associated with the drawings is described below. Since the manufacturing processes of the trench gate MOSFET of the present embodiment are substantially the same as those of the first embodiment, only the differences are described.
    First, in a process shown in Fig. 11A - the same process as shown in Fig. 3A is performed.
    Then, in a process shown in Fig. 118, the same process as shown in Fig. 3B is performed to form the ditch 5. In this case, the ditch 5 is formed located below the trench gate structure while the ditches 5a, 5b are located between the trench gate structures. in the central region R1a and R1b. Then, in a process shown in Fig. 11C, the same process as that shown in Fig. 3G is performed, so that the first and second layers 6a, 6b can also be formed in the trench 5c. The thickness of the first layer 6a is the same between in the ditch 5b and the ditch 5c, and also the depth of the second layer 6b is the same between in the ditch 5b and the ditch 5c. Then, in a process shown in Fig. 11D, the same process as that shown in Fig. 3D is performed, so that the trench gate MOSFET shown in Fig. 10 can be completed.
    As described above, the ditch 5c is formed at the same time as the first and second ditches 5a, 5b are formed. Furthermore, the p-type deep layer 6 is formed in the ditch 5c at the same time as the p-type deep layer 6 is formed in the ditches 5a, 5b. Therefore, the manufacturing processes can be simplified.
    (Modification) The embodiments described above can be modified in various ways, for example as follows. In the SiC semiconductor device according to the embodiments described above, a first type of conductivity is defined as n-type, and a second type of conductivity is defined as p-type. Alternatively, the first type of conductivity may be defined as p-type, and the second type of conductivity may be defined as n-type.
    A vertical MOSFET is taken as an example to describe the first and second embodiments, and a vertical JBS is taken as an example to describe the third embodiment. Alternatively, the present invention can be applied to another vertical structural element, such as IGBT or PN diode, as long as a deep layer can be formed in the vertical structural element.
    In the embodiments described above, the area of the deep layer 6 of p-type is divided into two, and the ditch has two different widths. However, the present invention can be achieved as long as the breakthrough is caused to occur in a planar form in the cell center region. Therefore, the same advantage can be obtained by gradually changing the trench width and depth of the second layer. Such changes and modifications are understood to be within the scope of the present invention as set forth in the appended claims.
    权利要求:
    Claims (12)
    [1]
    A silicon carbide semiconductor device, comprising: a silicon carbide substrate (1, 31) having a first or second type of conductivity; an operating layer (2, 32) of silicon carbide formed on a surface of the substrate (1, 31) and having a first type of conductivity; a semiconductor element formed in a cell region (R1) of the substrate (1, 31) and having a vertical structure for allowing the fate of an electric current between a front electrode (1, 34) formed on a front side of the substrate (1, 31) and a back electrode (13, 35) formed on a back side of the substrate (1, 31); a breakthrough region (R2) surrounding the periphery of the cell region (R1); and a deep layer (6) having a second type of conductivity and extending to the operating layer (2, 32), said deep layer (6) being formed in each of a central region (R1a) of the cell region (R1) and a connecting region (R1b) surrounding the central region (R1a) for connecting the central region (R1a) and the breakthrough resistant region (R2), the deep layer (6) causing a breakdown voltage (BV (R1a)) of the central region (R1a) ) is less than a breakdown voltage (BV (R1b)) of the connection area (R1 b), and the deep layer (6) causes the breakdown voltage (BV (R1b)) of the connection area (R1b) to be less than a breakdown voltage (BV (R2)). ) of the breakthrough resistant region (R2).
    [2]
    The silicon carbide semiconductor device according to claim 1, further comprising: a trench (5) extending to the operating layer (2, 32) and formed in each of the center region (R1a) and the connecting region (R1b), the deep layer (6) comprises a layer (6b) with a second type of conductivity and is arranged in the ditch (5), and wherein the depth of the layer (6b) with the second type of conductivity formed in the middle region (R1a) is greater than the depth of the layer (6b) with the second type of conductive format in the bypass area (R1b).
    [3]
    The silicon carbide semiconductor device according to claim 2, further comprising: a first layer (6a) formed on a bottom of the ditch (5) and having a first or second type of conductivity, the first layer (6a) having an impurity concentration that is less than an impurity concentration of the layer (6b) having the second type of conductivity, wherein the layer (6b) having the second type of conductivity is a second layer (6b) formed on the first layer (6b). 6a), and wherein the thickness of the first layer (6a) in the connecting area (R1b) from the bottom of the ditch (5) is greater than the thickness of the first layer (6a) in the central area (R1a) from the bottom of the ditch (5).
    [4]
    A silicon carbide semiconductor device according to claim 3, wherein a surface of the first layer (6a) at the bottom of the trench (5) is rounded, so that a bottom of the second layer (6b) formed on the first layer (6a) is rounded .
    [5]
    A silicon carbide semiconductor device according to any one of claims 2-4, wherein the width of the trench (5) formed in the central region (R1a) is greater than the width of the trench (5) formed in the connecting region (R1b).
    [6]
    A silicon carbide semiconductor device according to any one of claims 2-5, wherein the semiconductor element has a trench gate structure, the trench gate structure comprising a base region (3) having a second type of conductivity and format on the operating layer (2) , an emitter region (4) having a first type of conductivity and format on the base region (3), a trench (7) extending to the operating layer (2) by penetrating the base region (3) and the emitter region (4), a gate oxide film (8) formed on an inner surface of the ditch (7), a gate electrode (9) formed on a surface of the gate oxide film (8), an emitter electrode (11) electrically connected to the base region (3) and the emitter region ( 4) and a backing electrode (13) formed on the back of the substrate (1), and wherein the deep layer (6) is further formed under the ditch (7) providing the trench gate structure.
    [7]
    The silicon carbide semiconductor device according to claim 6, wherein the layer (6b) having the second type of conductivity is further formed on the deep layer (6) formed below the trench (7) providing the trench gate structure, and wherein the depth of the layer ( 6b) with the second type of conductivity of the deep layer (6) formed in the central region (R1 a) between the trench gate structures is greater than the depth of the layer (6b) with the second type of conductivity of the deep layer (6) formed under the ditch (7) which provides the trench gate structure.
    [8]
    A silicon carbide semiconductor device according to any one of claims 1-7, wherein the area of the central region (R1a) is larger than the area of the connecting region (R1 b).
    [9]
    A method of manufacturing a semiconductor device of silicon carbide, comprising: 95% providing a silicon carbide substrate (1, 31) having a first or second type of conductivity; forming an operating layer (2, 32) having a first type of conductivity on a surface of the substrate (1, 31); forming a semiconductor element in a cell region (R1) of the substrate (1, 31), which semiconductor element has a vertical structure for allowing flow of an electric current between a front electrode (11, 34) formed on a front side of the substrate (1, 31). ) and a back electrode (13, 35) formed on a back side of the substrate (1, 31); forming a breakthrough resistant region (R2) to surround the periphery of the cell region (R1); forming a trench (5) in each of a central region (R1a) and a connecting region (R1b) of the cell region (R1) to reach a predetermined depth of the operating layer (2, 32), which connecting region (R1b) surrounds the target area (R1a) for connecting the target area (R1a) and the breakthrough resistant area (R2), the formation of the ditch (5) comprising producing the width of a ditch (5a) formed in the target area (R1a) larger than the width of a ditch (5b) formed in the connection area (R1b); and forming a deep layer (6) in each of the ditches (5a, 5b) in the middle area (R1 a) and the connecting area (R1 b) by epitaxial growth of a first layer (6a) having a first type of conductivity or a second type of conductivity in the ditches (5a, 5b) and by epitaxial growth of a second layer (6b) on the first layer (6a) in the ditches (5a, 5b), the first layer (6a) having an impurity concentration which is less than an impurity concentration of the second layer (6b).
    [10]
    A method according to claim 9, wherein the forming of the deep layer (6) comprises forming the first and second layers (6a, 6b) in succession in the same apparatus without interruption of supply of material gas.
    [11]
    A method according to claim 9 or 10, wherein the forming of the ditch (5) comprises forming the ditch (5) with a side ratio of two or more, and the forming of the deep layer (6) comprises epitaxial growth of the first and second layers ( 6a, 6b) at a temperature of 1600 degrees C or more.
    [12]
    A method according to any one of claims 9-11, wherein the semiconductor element has a trench gate structure comprising a base region (3) having a second type of conductivity and formed on the operating layer (2), an emitter region (533 962 5125 emitter region). 4) having a first type of conductivity and shape on the base region (3), a trench (7) extending to the operating layer (2) by penetrating the base region (3) and the emitter region (4), a gate oxide film (8 ) formed on an inner surface of the ditch (7), a gate electrode (9) formed on a surface of the gate oxide film (8), an emitter electrode (11) electrically connected to the base region (3) and the emitter region (4), and a backing electrode (13) formed on the back of the substrate (8), and the forming of the deep layer (6) comprises forming an additional deep layer (6) below the trench (7) providing the trench gate structure before forming the trench. the gate structure and the shaping of the deep layer (6) comprise the shaping of the further deep layer (6) under the ditch (7) which provides the trench gate structure at the same time as the formation of the deep layer (6) in the ditches (Sa, 5b) in the central area (R1a) and in the connecting area (R1 b)
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    法律状态:
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