• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Method and device for increasing the security of a cryptographic algorithm for, for example, decryption, encryption or for digital signature using block ciphers such as e.g. AES implemented in e.g. a "white box" model with the encryption key either known or unknown at the time of compilation. This method is secure for use in secure environments especially for cryptographic keys. The look-up tables characteristic of such algorithms are protected against attack by making all such tables of the same size and indistinguishable, and also by masking the output values from such tables especially when the tables perform a permutation function or a logical exclusive-OR operation.
    公开号:SE1350203A1
    申请号:SE1350203
    申请日:2011-08-03
    公开日:2013-05-20
    发明作者:Augustin J Farrugia；Thomas Icart；Mathieu Ciet
    申请人:Apple Inc；
    IPC主号:
    专利说明:

    [6] Note that these block ciphers are symmetric ciphers, which means that the same algorithm and key are used for encryption and decryption, usually with the exception of minor differences in the key scheme. As is typical of most modern ciphers, security is obtained with the (secret) key rather than with the algorithm. The S-boxes or substitution boxes were introduced into DES and accept an n-bit input signal and provide an m-bit output signal. The values of m and n vary with the digit. The input bits specify an input data in the S-box in a certain way, which is well known in the art.
    [7] Implementing AES (with 128 bit blocks, and 10 rounds) arithmetically involves the following operations: (l) ll Add-turn-key operations (l before 10 rounds), (2) 10 Sub-byte operations, (3) l0 Shift-row operations, and (4) 9 Mix-column operations. Each round of rounds 1 to 9 consists of operations (1) to (4), where the output signal from one operation is input to the next operation, and the output signal from operation (4) is input to operation (1). Round 10 consists of operations (1) to (3), where the output signal from operation (3) is the output signal used. Arithmetic implementations of AES do not provide much security against an attacker with access to a secret key, if the attacker has privileged access to the system that implements the cipher.
    [8] Many encryption algorithms are primarily intended to produce encrypted data that is resistant to decryption by an attacker, which can interact with the encryption algorithm only as a "black box" model (input-output), and can not observe the internal workings of the algorithm. or memory content, etc due to lack of access to the system. The black box model is suitable for applications where trusted parties control the computer systems for both encoding and decoding of encrypted material.
    [9] However, many encryption applications do not allow the assumption that an attacker cannot access the internal workings of the algorithm. For example, encrypted digital media often need to be decrypted on computer systems, which are completely controlled by a counterparty (attacker). There are many degrees to which the black box model can be stepped down. An extreme downsizing is called the "White box" model. In a White box model, it is assumed that an attacker has total access to the system, which performs an encryption, including being able to directly observe a memory state, program execution, and so on. In such a model, an encryption key can be observed in or extracted from the memory, and thus measures to conceal operations indicating a secret key are important.
    [10] Publications "White-Box Cryptography in an AES implementation" Lecture Notes in Computer Science Vol. 2595, Revised Papers from the 9th Annual International Workshop on Selected Areas in Cryptography pages 250-270 (2002) by ChoW et al. describes implementations of AES that hide the operations performed under AES using table lookups to hide the secret key in the lookup tables and hide intermediate state information that would otherwise be available in arithmetic implementations of AES.
    [11] ChoW et al. (for his "White box" implementation where the key is known at the computer code compilation time) uses 160 separate tables to implement the 11 Add-Batch key operations and 10 Sub-byte operations (10 batches, with 16 tables per batch, where each table is for 1 byte of the 16 byte 128 bit AES block). These 160 tables contain a certain AES key, so that results from lookups in these tables contain data, which would normally result from Add Batch Key and Sub-byte operations for the AES algorithm, in addition to this data containing input / output permutations , which makes it more difficult to determine which parts of these tables represent round key information derived from the AES key.
    [12] ChoW et al. uses 1008 separate tables to implement the nine Mix column operations (there is no Mix column operation in the00th round of AES). One type of these tables implements a multiplication of a byte with the AES Mix column polynomial (according to the specification), and another type implements the logical XOR (excluding OR) part of the Mix column. Each table is used once during the nine rounds.
    [13] ChoW et al. the solution is smart, but fl your attacks have already been made on it. ChoW et al.'s White box implementation of a given block cipher encryption process breaks down the block cipher (with its key) as a set of table lookups. The table lookups are then masked using permutation functions. (The term permutation, as used herein, refers to a bijective operation that changes the order of bits in a data byte or a word in a predetermined manner.) This is explained in ChoW et al., And this method can be extended to all block ciphers.
    [14] The most recent and powerful extension of this kind was published by Olivier Billet et al. "Cryptanalysis of a White Box AES Implementation" in SAC 2004 LNCS 3357 p. 227-240, 2005. The details of the processed basic operations are necessary to construct this attack. This means that the attacker must distinguish the series of operations to extract the operations per batch, the Mix-column operation, etc.
    [15] The present method and its associated device, which are intended to nullify such attacks, comprise the construction of an AES implementation (or other encryption algorithm including any block cipher algorithm) as a set of basic table operations each of which cannot be distinguished from each other and are masked. Thereby, the attacker is misled in, or confused by, the computer code that contains the cipher (for a passive attack) and / or in the execution path of the computer code (for an active attack). This approach is also possible to implement in a hardware device (circuit-based) which is intended to perform the cryptographic process.
    [16] The Billet et al. the attack is a process that consists of a series of basic problems in obtaining step-by-step information regarding the masks used to hide the cipher operations and the key. Once the masks are known, it is then easy to extract the encryption key itself.
    [17] The Billet et al attack allows the attacker to recover the non-linear portion of the output transformers as soon as the attacker can regroup tables that are a round for the AES algorithm. Billet et al. shows, for example, how to recover the non-linear part of the functions Q used in the Mix column "box" 10, as shown in FIG. 1, from Billet et al., Showing one of the four images in box 10 between four input bytes and four output bytes. The incoming bytes are years x0, x1, xg, xg, and the outgoing bytes are yo, y1, yg, yg.
    [18] One goal of the present cryptographic process is to make this task more difficult. In fact, in the current well-known version of AES, some tables are larger than others and some operations are not of the "White box" type. The mix column tables in FIG. 1 has a size of 8x32 elements instead of 8x8 elements in the other tables. In addition, the outputs of some tables are logically XOR (excluding OR), as opposed to the outputs of the other tables.
    [19] Since the operations are thus discernible, it is possible for the attacker in a White box environment to determine when an AES round ends and when a new one begins.
    [20] An object of the present method is to construct such tables so that they are all exactly the same size, thereby drastically complicating such an attack. Due to the structure of the calculation of the AES cipher algorithm, you can use tables with sizes S-bit input x 4-bit output (which have a size of 128 bytes), 16-bit input x 8-bit output (65 Kbytes) or 32-byte bit input x 16-bit output (8Gbytes).
    [21] Incorporated by reference herein in their entirety are jointly owned U.S. Patent Application Publications US 2009/0252327 A1 "Combination White Box / Black Box Cryptographic Processes and Apparatus" Ciet et al. and US 2010/0054461 A1 "Systems and Methods for Implementing Block Cipher Algorithms on Attacker-Controlled Systems" Ciet et al.
    [22] FIG. 1 shows in the prior art an illustration of the AES Mix column operation.
    [23] FIG. 2 schematically shows an XOR operation table or "box".
    [24] FIG. 3 shows a permutation box.
    [25] FIG. 4A, 4B show the permutation of FIG. 3 in steps.
    [26] FIG. 5 shows another XOR table.
    [27] FIG. 6 shows a general form of FIG. 5 table.
    [28] FIG. 7 shows a completed XOR table.
    [29] FIG. 8A, 8B and SC show a worm permutation.
    [30] FIG. 9 shows a computer system.
    [31] FIG. 10 shows details in FIG. 9 system.
    [32] The tables of the type described above have as input data one byte of data but retrieve only half a byte. Considering the AES cipher as an example, the inventors have determined that two types of 8x4 tables are sufficient for the AES algorithm: (a) The tables that implement S-bit input (2 half-bytes) with a 4-bit (1 half-byte) output are thus limited to a half change on the output side. In this case, to represent a permutation function for a change of input data, two tables of 8x4 each are required. (b) The tables that implement the logical XOR operation on masked half-bytes.
    [33] Having the same size of tables in accordance with the invention does not mean that the tables cannot be separated from each other. This is also the case if the tables are masked using input and output permutations. The inventors have identified a first way of distinguishing between tables that an attacker can use. So even though all the tables involved are the same size, they are easy to distinguish. In fact, an XOR operation table is the table for a team. For each half-byte, there is thus a unique half-byte such that the output signal through the "box" (table) is 0. (The term "box" refers to a table or logical or mathematical operation performed in a table, not to the "White box" environment .) This property (separator) is also verified for each value in the group [1, 24-1], which are the other possible outputs from the XOR operation table.
    [34] This latter feature ensures that each output from an XOR operation table has exactly 16 previews. (A cryptographic image is a value or values that are mapped to a specific output.) Thus, if XOR operation tables are used in a calculation, an attacker can detect them using a known image attack and obtain useful information about implementation, including the structure of such tables.
    [35] The inventors also identified a second way (property) to distinguish between these two types of tables. Each 8x4 table, which represents half of a pernutation, necessarily has a "twin" table, which represents the other part of the pernutation. A "twin" to a particular table A is table B of the interconnection table C for A and B in the sense that C [i] = A [i] B [i], where A, B and C accept the same input signal and for each input signal , the output signal from table C is the interconnection of the A and B output signals and C is a permutation, where "|" denotes interconnection. So given a certain XOR operation table A, does not necessarily mean that it has a twin table B in a certain encryption algorithm. However, it is possible to construct such a table B. So in the present process, such an additional table B is constructed for each XOR operation table A, and these additional tables B are used. Note that in order to manage computer code in a software version, one can construct input and output permutations on two such XOR operation tables such that they are twins.
    [36] An 8X4 table implementing an XOR operation has no such twin as explained above because it receives two half-bytes and returns a single half-byte. A priori, in a set of 8x4 tables, it is thus easy to distinguish an XOR operation table from other tables, and this provides unwanted information about the implementation to the attacker regarding the type of table.
    [37] The following is a computationally efficient method for hiding the character of a table that is either part of a permutation or is an XOR operation table, to block these two ways of distinguishing tables. Let a data byte denoted X be the interconnection of two half bytes denoted X0 and X1, expressed algebraically as: X0 II X1_
    [38] Here, the XOR operation table with the input signals X0 and X1 is represented by the box 12 in FIG. 2.
    [39] Let the result of a permutation denoted P on input change X (= X0 X1) be an interconnection of two pernutations denoted P0, P1 so that P0 (X0 | X1) and P1 (X0 | X1), where P0 and P1 applied to X and not only to a part of X, expressed as: P0 (X0 | X1) | P1 (X0 | X1) -
    [40] A pernutation P with box 14 of size SXS is also represented, as shown in FIG. 3. As explained above, a permutation can be divided into two sub-tables P016 and P118, shown in Figs. 4A, 4B.
    [41] In the following, the construction of a twin table for the XOR operation table to block the second way of separating tables is described. As explained above, the XOR operation table in the algorithm does not have a twin table, as they are (niered (see above) as a table that makes a pernutation when associated with the XOR operation table.
    [42] The following describes how to make the XOR tables indistinguishable from each other thereby blocking the first way of distinguishing. This includes hiding the property of the number of previews of the XOR operation tables. Assume that there is a pernutation that is a complete XOR operation table 24, as described above and shown in FIG. 7. To hide that its upper part consists of an XOR operation table, in a first step two pernutations denoted M and R, respectively, are calculated such that for all half-bytes X0 and X1 where M is the mask 26 in FIG. 8A, and R is the interconnection of MJ and Q in Figure SB: IV (R (X0, X1)) I (X0 + X1, F (X0, X1))
    [43] The letter M indicates "mask" because this permutation masks that the table is in fact an XOR operation table. Permutation M 26 shown in FIG. 8A is selected at random, e.g. from a predetermined set of permutations. This selection is usually performed when the source code of the date is compiled into (executable) object code. From the inverse perinutation of M, denoted M-1, the interconnection of M4 with the finished XOR operation table is calculated. There are now two permutations MJ 27 and Q 28, as shown in Figure. SB which are combined to the pernutation R 29 in figure SC. Advantageously, none of these pernutations, taken separately, have any particular property that would allow an attacker to distinguish them from a random perinutation.
    [44] In a second step of the masking, the output from the XOR operation table is masked. In fact, it is generally better for security to never expose the correct data in the calculation. To do this, two methods can be used: (a) The first method involves calculating a 4x4 random perinutation and assembling it with the upper part of a second permutation. (b) The second method involves calculating an 8x8 random permutation and combining it with the complete second pernutation.
    [45] In both cases, the inverse of the last calculated pernutation is reused. In fact, the goal is to have a set of permutations that can be linked in a chain.
    [46] Thus, in accordance with the invention, any table of a White box implementation of AES or a similar encryption algorithm may be represented as a set of table lookups, which are indistinguishable from each other, using the construction described above. tables.
    [47] The resulting encryption process is expressed (in data code or hardware) as a set of table lookups, which are indistinguishable from each other, of tables each of the size 8x4, for example. This makes it difficult for an attacker to extract what really responds to a full round in order to carry out his attack because it is difficult for him to determine when each round begins or ends. This is especially true when your "unnecessary" operations (each involving an additional pernutation) are added where desired in the process of adding complexity and where these additional and useless tables are indistinguishable from the useful tables. These additional permutations increase security by making some rounds of the encryption algorithm longer than others. In another embodiment, additional operations of this kind are added on a per-byte basis within each round.
    [48] The present method can be extended to cryptographic processes using tables in other formats such as 18x8 or 32x16. However, 8x4 tables may be preferable.
    [49] FIG. 9 shows in a block diagram relevant parts of a computer unit (system) 30 in accordance with the decryption of the invention. This is, e.g. a computer, mobile phone, Smart Phone, personal digital assistant or similar device, or a part of such a device and comprises conventional hardware components which in one embodiment execute software (data code) which performs the above examples of a cryptographic (e.g., encryption or decryption) process. This code can be e.g. in C or C + + computer language or its functionality may be expressed in the form of firmware or hardware logic (circuits), whereby writing such a code or designing such a logic would be routine in light of the above description.
    [50] The computer code is conventionally stored in code memory 40 (computer readable storage medium, e.g., ROM) (in object code or source code) associated with the processor 38 for executing the processor 38. The incoming message (data) to be encrypted or decrypted or on otherwise processed, it is received on port 32 and stored in computer readable storage medium 36 (memory, eg RAM) where it is connected to processor 38. Processor 38 conventionally partitions the message into suitably large blocks in the software division module 42.
    [51] Also coupled to the processor 38 is the computer readable storage medium 52 (memory) for storing the tables, and a third storage medium 58 for the resulting output data, e.g. the decrypted or encrypted input data. The memory slots 36, 52, 58 may be in one or more conventional physical memory devices (for example, semiconductor RAM or its variants or a hard disk drive). 11
    [52] Electrical signals are conventionally transmitted between the various elements of FIG. 9. shown in FIG. 9 is the subsequent conventional use of the resulting encrypted or decrypted message.
    [53] FIG. 10 shows further details of the computer unit in one embodiment. FIG. 10 illustrates a typical and conventional computer system 60, which may be used to implement processing of operations in embodiments of the invention, and shows further details of FIG. 9 system. Computer systems of this type can be used in a computer server or user (client) computer or other computer device, for example. Those skilled in the relevant art will also appreciate how to implement embodiments of the invention using other computer systems or architectures.
    [54] The computer system 60 may also include a main memory 68 (corresponding to the memories 36, 52, 58), such as random access memory (RAM) or other dynamic memory for storing information and instructions to be executed by the processor 64.
    [55] Computer system 60 may also include information storage system 70, which may include, for example, a media drive 72 and an external memory interface 80. The media drive 72 may include a drive or other mechanism for providing support to fixed or surface storage media. for example fl ash memory, a hard disk drive, a floppy disk drive, a 12 magnetic tape drive, an optical drive, a compact disc (CD) or (DVD) drive (R or RW), or other removable or solid media drive. Storage media 78 may include, for example, a hard disk, floppy disk, magnetic tape, optical disc, CD or DVD, or other solid or removable media that is read and written to with media device 72. As these examples show, storage media 78 may include a computer readable storage medium that has been stored. special software or data.
    [56] In alternative embodiments, information storage system 70 may include other similar components to allow computer programs or other instructions or data to be loaded into computer system 60. Such components may include, for example, an external storage unit 82 and an interface 80, such as a program cassette. and a cassette interface, an external memory (eg, an fl memory or other external memory module) and memory card slot, and other external storage devices 82 and interfaces 80, which allow software and data to be transferred from the external storage device 78 to the computer system 60.
    [57] Computer system 60 may also include a communication interface 84 (equivalent to port 32 in FIG. 9). Communication interface 84 can be used to allow programs and data to be transferred between computer systems 60 and external devices. Examples of communication interfaces 84 may include a modem, a network interface (eg, an Ethemet or other network card (N IC)), a communication port (such as a USB port), a PCMCIA card slot and cards, etc. Software and data transmitted via the communication interface 84 is in the form of signals which may be electronic, electromagnetic, optical or other signals which may be received by the communication interface 84. These signals are provided to the communication interface 84 via a channel 88. This channel 88 may transport signals and can be implemented using a wireless medium, wire or cable, professional optics, or other communication medium. Some examples of a channel include a telephone line, a cellular telephone link, an RF link, a network interface, a local or global network, and other communication channels.
    [58] In this specification, the terms "computer program product", "computer readable medium" and the like may be used generally to refer to media such as memory 68, storage unit 78, or storage unit 82. These and other forms of computer readable media may store one or more instructions for using the processor 64, to cause the processor to perform specified operations. Such instructions, generally referred to as "computer program code" (which may be grouped in the form of computer programs or other groupings), when executed, enable the computer system 60 to perform functions in embodiments of the invention. Note that the code can directly cause the processor to perform specified operations, can be compiled to do so, and / or can be combined with other software, hardware and / or firmWare elements (eg libraries to perform common functions) to do so .
    [59] In an embodiment where the elements are implemented by software, the software may be stored in a computer readable medium and loaded into computer systems 60 using, for example, external storage drive 74, drive 72 or communication interface 84. Control logic (in this example, software instructions or computer program code), when executed by the processor 64, causes the processor 64 to perform the functions of embodiments of the invention described herein.
    [60] This description is illustrative and not limiting. Further modifications will be apparent to those skilled in the art in light of this specification and are intended to fall within the scope of the appended claims.
    权利要求:
    Claims (7)
    [1]
    A patent-implemented method for protecting an information, the method comprising: receiving an information on a machine; and applying a number of ciphering permutations to the information, the ciphering permutations being expressed on the machine as sets of equally exclusive-OR tables linked to a twin table, making the linking bijective and (ii) an inverse of a randomly generated masking permutation.
    [2]
    The method of claim 1, wherein each equally large table has twice as many input bits as output bits.
    [3]
    The method of claim 1, wherein the encryption keys are included in the encryption pernations.
    [4]
    The method of claim 1, wherein an input signal to at least one of the exclusive-OR tables for the encryption permutations is masked.
    [5]
    The method of claim 1, wherein the encryption permutations are each performed on a bit-by-bit basis.
    [6]
    The method of claim 1, wherein the number of encryption pernutations is applied to the information during a number of rounds of the encryption process.
    [7]
    An apparatus comprising: a port for receiving information; a set of process units for executing sets of instructions; and a memory for storing a program which, when executed by at least one of the process units, applies an encryption process to information, the program comprising a set of instructions for applying a plurality of encryption pernations to the information, the encryption pernations being expressed on the device as sets of equal-sized tables, and each cipher permutation comprising a combination of an exclusive-OR table linked to a twin table, making the link bijective and (ii) an inverse of a randomly generated masking permutation. The device of claim 7, further comprising a storage unit for an encryption key for the program. Device according to claim 7, wherein the inverse of the randomly generated masking pernutation is composed of only the eXclusive-OR table and not the twin table. The device of claim 7, wherein the inverse of the randomly generated masking permutation is composed of both the exclusive-OR table and the twin table. The apparatus of claim 7, wherein the inverse of the randomly generated masking pernutation includes the same number of tables as the interconnection of the exclusive-OR table and the twin table. Computer readable medium storing a computer program for execution with at least one processor unit on a machine, the program comprising sets of instructions for: receiving an information comprising sets of bits; and applying a number of encryption permutations to the information, the encryption permutations being expressed on the machine as sets of equal tables, and each encryption permutation comprising a combination of (i) an exclusive-OR table linked to a twin table, giving the resulting link the same number of input bits and output bits and (ii) an inverse of a randomly generated masking pernutation. The computer readable medium of claim 12, wherein the program further comprises 14. 15. 16 comprises a set of instructions for applying a number of non-cipher permutations to the information. The computer-readable medium of claim 12, wherein the randomly generated masking pernutation is generated in operation. The computer-readable medium of claim 12, wherein for a particular encrypting pernutation, the randomly generated masking permutation is used in a previously encrypting pernutation.
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    同族专利:
    公开号 | 公开日
    DE112011102765T5|2013-09-19|
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    US20120045050A1|2012-02-23|
    CN103119888A|2013-05-22|
    US8644500B2|2014-02-04|
    AU2011292312A1|2013-03-14|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US6518896B1|2000-01-15|2003-02-11|Sony Electronics, Inc.|Multiple symbol length lookup table|
    JP2002261751A|2001-03-02|2002-09-13|Hitachi Ltd|Code-processing method|
    US7577250B2|2004-08-12|2009-08-18|Cmla, Llc|Key derivation functions to enhance security|
    US8077861B2|2004-08-12|2011-12-13|Cmla, Llc|Permutation data transform to enhance security|
    US8069346B2|2006-11-15|2011-11-29|Certicom Corp.|Implicit certificate verification|
    CN101536398B|2006-11-17|2012-11-07|耶德托公司|Cryptographic method for a white-box implementation|
    US7822207B2|2006-12-22|2010-10-26|Atmel Rousset S.A.S.|Key protection mechanism|
    JP2010515945A|2007-01-11|2010-05-13|コーニンクレッカフィリップスエレクトロニクスエヌヴィ|Tracking a copy of the implementation|
    US8165286B2|2008-04-02|2012-04-24|Apple Inc.|Combination white box/black box cryptographic processes and apparatus|
    US8175265B2|2008-09-02|2012-05-08|Apple Inc.|Systems and methods for implementing block cipher algorithms on attacker-controlled systems|
    US8644500B2|2010-08-20|2014-02-04|Apple Inc.|Apparatus and method for block cipher process for insecure environments|US8644500B2|2010-08-20|2014-02-04|Apple Inc.|Apparatus and method for block cipher process for insecure environments|
    US9274976B2|2010-11-05|2016-03-01|Apple Inc.|Code tampering protection for insecure environments|
    US9654279B2|2014-03-20|2017-05-16|Nxp B.V.|Security module for secure function execution on untrusted platform|
    US9641337B2|2014-04-28|2017-05-02|Nxp B.V.|Interface compatible approach for gluing white-box implementation to surrounding program|
    SG10201405852QA|2014-09-18|2016-04-28|Huawei Internat Pte Ltd|Encryption function and decryption function generating method, encryption and decryption method and related apparatuses|
    US9665699B2|2015-03-13|2017-05-30|Nxp B.V.|Implementing padding in a white-box implementation|
    US10015009B2|2015-11-25|2018-07-03|Nxp B.V.|Protecting white-box feistel network implementation against fault attack|
    US10171234B2|2015-12-16|2019-01-01|Nxp B.V.|Wide encoding of intermediate values within a white-box implementation|
    EP3300291A1|2016-09-27|2018-03-28|Gemalto SA|Method to counter dca attacks of order 2 and higher|
    FR3061822B1|2017-01-10|2019-05-10|Safran Identity & Security|METHOD OF ENCRYPTING OR DE-RECTIFYING A DATA N-UPLET WITH A PREDETERMINED SECRET KEY N-UPLET|
    法律状态:
    2015-11-24| NAV| Patent application has lapsed|
    优先权:
    申请号 | 申请日 | 专利标题
    US12/806,768|US8644500B2|2010-08-20|2010-08-20|Apparatus and method for block cipher process for insecure environments|
    PCT/US2011/046483|WO2012024086A1|2010-08-20|2011-08-03|Apparatus and method for block cipher process for insecure environments|
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