Semiconductor memory device having overdrive bitline sense amplifier therein

专利摘要:
After the data is read, during the equalization operation of the bit line whose potential is amplified by the overdrive voltage and the bit line complementary to the bit line, the charge circuit overcharged with the overdrive voltage is supplied to the discharge circuit 35. Discharge at the ground potential, and the bit line equalization potential is adjusted by adjusting the discharge period in the discharge circuit.
公开号:KR20030066440A
申请号:KR10-2003-0006693
申请日:2003-02-04
公开日:2003-08-09
发明作者:와다마사하루；쯔찌다겐지；이나바쯔네오；이께다도시미
申请人:가부시끼가이샤 도시바；후지쯔 가부시끼가이샤；
IPC主号:

专利说明:

Semiconductor memory device with overdrive bit line sense amplifier TECHNICAL TECHNICAL TECHNICAL DEVICE HAVING OVERDRIVE BITLINE SENSE AMPLIFIER THEREIN
[27] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to correction of a bit line equalization potential when an overdrive method is employed in a memory core portion to improve the read speed of a bit line sense amplifier. The present invention is applied to, for example, a memory integrated circuit, a logic mixed semiconductor memory, and the like.
[28] In a dynamic random access memory (DRAM), reading, amplifying and restoring micro signal data from a memory cell are performed by a bit line sense amplifier. In order to improve the read speed of the bit line sense amplifier, an overdrive method that drives the bit line sense amplifier at a voltage higher than the restore potential (overdrive voltage) at the initial stage of cell data amplification and amplifies data at high speed is employed. DLAM is disclosed in Japanese Patent Laid-Open No. 2002-25264.
[29] In the DRAM disclosed in the above publication, in the initial stage of reading of the cell data, an overdrive operation is performed by applying an overdrive potential higher than the restore potential to the P-type sense amplifier. This speeds up the timing of detecting the bit line potential. Thereafter, the overdrive operation is stopped and the restore potential is supplied to the bit line charged to the overdrive potential, whereby the bit line potential is stabilized to the restore potential. Subsequently, the bit line pairs are precharged to the precharge potential and equalized.
[30] However, as the speed of DRAM increases, if the active period is shortened to speed up the read operation as described above, the period for stabilizing the bit line to the restore potential is shortened. As a result, the bit line potential at the time of equalizing the bit line on the high potential side charged to the high potential by the overdrive operation and the bit line potential on the low potential side charged to the low potential is affected by the potential rise due to the overdrive operation. Receives. For this reason, the bit line potential at the time of equalization becomes higher than the intermediate value of the restore potential of the bit line pair.
[31] The bit line potential of either of the equalized bit line pairs is used as the reference potential when reading the cell data in the next cycle. For this reason, as a result of being affected by the potential rise due to the overdrive operation, when the read operation of the cell data is performed while the potential of the bit line pair is high, the read margin of "1" data is reduced, and the cell data is read correctly. I can't make it. Therefore, it is desired to improve this conventionally.
[32] An object of the present invention is to adjust the bit line reference potential at the time of reading a bit line potential by means of a bit line sense amplifier employing an overdrive method, so that the cell data can be read accurately even with a short cycle of read operation. It is to provide a semiconductor memory.
[1] 1 is a diagram showing a pattern layout of an entire DRAM chip according to a first embodiment of the present invention.
[2] FIG. 2A is an enlarged pattern layout diagram of a portion of the DRAM of FIG. 1; FIG.
[3] FIG. 2B is a pattern layout diagram showing one subarray and its peripheral circuits from the DRAM of FIG.
[4] FIG. 3 is a block diagram showing a circuit configuration of a part of the subarray of FIG. 2 (b). FIG.
[5] 4 is a circuit diagram showing the configuration of the circuit and cell array shown in FIG.
[6] FIG. 5 is a waveform diagram showing an example of the operation of the circuit shown in FIG. 4; FIG.
[7] FIG. 6 is a waveform diagram showing another example of the operation of the circuit shown in FIG. 4; FIG.
[8] FIG. 7 is a waveform diagram showing the operation shown in FIGS. 5 and 6 unified.
[9] FIG. 8 is a circuit diagram showing one configuration of a timing generating circuit for generating each control signal shown in FIG.
[10] 9 is a waveform diagram of input and output signals of the timing generation circuit of FIG. 8;
[11] 10 is a circuit diagram showing an example of a bit line precharge potential generating circuit provided in the circuit of FIG.
[12] Fig. 11 is a circuit diagram showing a partial circuit configuration of a subarray of a DRAM according to the second embodiment of the present invention.
[13] Fig. 12 is a circuit diagram showing a partial circuit configuration of a subarray of a DRAM according to the third embodiment of the present invention.
[14] FIG. 13A is a pattern layout diagram showing an excerpt of the circuit configuration of a part of the DRAM subarray of the third embodiment. FIG.
[15] FIG. 13B is a pattern layout diagram in which a part of the subarray of FIG. 13A is enlarged.
[16] FIG. 13C is a circuit diagram of a part of the circuit of FIG. 13B;
[17] Fig. 14 is a circuit diagram showing a partial circuit configuration of a DRAM subarray according to the fourth embodiment of the present invention.
[18] Fig. 15A is a pattern layout diagram showing an excerpt of the circuit configuration of a part of the DRAM subarray of the fourth embodiment.
[19] FIG. 15B is an enlarged pattern layout view of a part of the subarray of FIG. 15A. FIG.
[20] FIG. 15C is a circuit diagram of a part of the circuit of FIG. 15B.
[21] <Explanation of symbols for the main parts of the drawings>
[22] 12: subarray
[23] 14: 256k bit cell array
[24] 15: Segment Row Decoder Array
[25] 16: bit line sense amplifier array
[26] 17: intersection area
[33] According to the present invention, a plurality of bit lines are connected to a plurality of memory cells, a plurality of pairs of bit lines connected to the plurality of memory cells, and a plurality of pairs of bit lines, and amplifies potentials of the plurality of pairs of bit lines, respectively. An overdrive potential generation circuit for generating an overdrive potential, a plurality of bit line sense amplifiers and the overdrive potential generation circuit, and outputting the overdrive potential to the bitline sense amplifier; A sense amplifier driver, a second sense amplifier driver connected to the bit line sense amplifier and a predetermined potential, and outputting the predetermined potential to the bit line sense amplifier, the plurality of bit line pairs and a precharge potential, Precharge the plurality of bit line pairs by the precharge potential or equalize the potential of each bit line pair Pre-charging a plurality of bit lines, and the equalizing circuit, the rise is coupled to the plurality of bit line pairs, a semiconductor memory is provided which includes at least one discharge circuit for discharging the potential of the plurality of bit line pairs to the discharge potential.
[34] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. In addition, the same code | symbol is attached | subjected to the corresponding part over overturning, and the overlapping description is abbreviate | omitted.
[35] (First embodiment)
[36] Fig. 1 shows a pattern layout of the entire DRAM chip 10 having a storage capacity of 512M bits and employing the overdrive method.
[37] The chip 10 is provided with 16 32M bit arrays 11 each having a storage capacity of 32M bits.
[38] FIG. 2A shows an enlarged view of one portion of the 32M bit array 11 in FIG. 1. In each 32M bit array 11, 128 subarrays 12 each having a storage capacity of 256k bits are arranged in a matrix form of 16 rows x 8 columns. An array 13 of main row decoders MRD is disposed on one end side in the column direction. The 32M bit array 11 has 8k word lines (8k word lines) and 4k bit lines (4k-bit lines) as a whole.
[39] FIG. 2B shows an enlarged pattern layout by extracting one subarray 12 from its 32M bit array 11 in FIG. 2A together with its peripheral circuits.
[40] In the subarray 12, segment row decoder arrays 15 in which a plurality of segment row decoders are arranged in an array shape at both ends of the column direction of the cell array 256256 bit cell array 14 having a storage capacity of 256k bits are arranged. The bit line sense amplifier arrays 16, in which a plurality of bit line sense amplifiers are arranged in an array shape, are arranged at both ends in the row direction. Reference numeral 17 denotes an intersection area where the segment row decoder array 15 and the bit line sense amplifier array 16 intersect, and each of the four intersection areas 17 includes a bit line sense amplifier array and a segment row decoder. A circuit for controlling the is arranged.
[41] FIG. 3 is a block diagram illustrating a partial circuit of the bit line sense amplifier array 16 of FIG. 2B. 4 is a circuit diagram showing the circuit shown in FIG. 3 together with the cell array.
[42] 3 and 4, the bit line pair 20 is composed of a bit line BL_T corresponding to external I / O and positive logic and a bit line BL_C corresponding to external I / O and negative logic. Although a plurality of bit line pairs are provided in the subarray 12, only one bit line pair 20 is shown in FIG. A plurality of memory cells 21 are connected to bit lines BL_T and BL_C constituting the bit line pair 20, respectively. In FIG. 4, for convenience, one memory cell 21 is connected to the bit lines BL_T and BL_C, respectively. A word line is connected to each memory cell 21. In FIG. 4, the word line WL_N is connected to the memory cell 21 connected to the bit line BL_T, and the word line WL_N + 1 is connected to the memory cell 21 connected to the bit line BL_C.
[43] A bit line sense amplifier S / A 22 is connected to the bit line pair 20. The bit line sense amplifier 22 is composed of a P-type sense amplifier (P-S / A: 23) and an N-type sense amplifier (N-S / A: 24). The P-type sense amplifier 23 is composed of two PMOSFETs. The P-type sense amplifier 23 is connected to the P-type sense amplifier driver PSD 26 through the P-type sense amplifier drive line SAP 25. The P-type sense amplifier 23 is supplied with positive charge through the P-type sense amplifier driver 26. The N-type sense amplifier 24 is composed of two NMOSFETs. The N-type sense amplifier 24 is connected to an N-type sense amplifier driver NSD 28 through an N-type sense amplifier drive line SAN 27. The N-type sense amplifier 24 is supplied with negative charge through the N-type sense amplifier driver 28.
[44] The P-type sense amplifier driver 26 has an overdrive PMOSFET through which the overdrive control signal / OD is supplied to the gate electrode via the overdrive control signal line 29. The current path between the source and the drain of the overdrive PMOSFET is inserted between the output node of the overdrive potential generation circuit 30 and the P-type sense amplifier drive line 25. The overdrive potential generation circuit 30 generates an overdrive potential higher than the restore potential of the bit line pair 20.
[45] The N-type sense amplifier driver 28 has a sensing NMOSFET through which the sense drive control signal SD is supplied to the gate electrode through the sense drive control signal line 31. The current path between the source and the drain of the sensing NMOSFET is inserted between the N-type sense amplifier drive line 27 and the ground line. The ground wire is connected to the ground potential GND.
[46] In the sense amplifier region in which the bit line sense amplifier 22 is disposed in the chip, a bit line precharge equalization circuit (EQL) for precharging and equalizing the bit line pair 20 in addition to the bit line sense amplifier 22 32) are arranged. The bit line equalization circuit 32 is composed of a precharge circuit 33 and an equalization circuit 34. In this embodiment, a discharge circuit (DSC) 35 for discharging the bit line pair 20 is added to the sense amplifier area.
[47] The precharge circuit 33 includes a bit line precharge potential line 36 for supplying a bit line precharge potential VBLEQ and an NMOSFET 37 in which a current path between a source and a drain is inserted between each of the bit lines BL_T and BL_C. 38). The gate electrodes of both NMOSFETs 37 and 38 are connected to the precharge control signal line 39 which supplies the bit line precharge control signal EQLCN.
[48] The equalizing circuit 34 is constituted by the NMOSFET 40 in which a current path between the source and the drain is inserted between the bit lines BL_T and BL_C. The gate electrode of this NMOSFET 40 is connected to the equalization control signal line 41 which supplies the bit line equalization control signal BLEQL.
[49] The precharge circuit 33 controls the precharge operation by the bit line precharge control signal EQLCN supplied from the precharge control signal line 39, and the equalization circuit 34 receives the bit line given from the equalization control signal line 41. The equalization operation is controlled by the equalization control signal BLEQL.
[50] The discharge circuit 35 is disposed in the vicinity of the precharge equalization circuit 32. The discharge circuit 35 includes two NMOSFETs 42 and 43 in which a current path between a source and a drain is inserted between the bit line pair 20 and a discharge potential, for example, a ground potential GND, which is a potential lower than the restore potential of the bit line. ), The discharge operation of each gate electrode is controlled by the discharge control signal DCS given from the discharge control signal line 44.
[51] FIG. 5 shows an example of operation waveforms when reading " 1 " data from a memory cell (" 1 " read) in a DRAM having the circuit shown in FIG. 6 similarly shows an example of an operation waveform when reading out "0" data ("0" read). 7 shows the relationship between the operation shown in FIGS. 5 and 6 and the timing of the control signal.
[52] Here, the overdrive control signal OD, the discharge control signal DSC, the bit line equalization control signal BLEQL, and the bit line precharge control signal EQLN in Fig. 7 are all expressed in positive logic.
[53] 5 and 6, reference numeral 1 denotes the potential of the storage node SN_H of the cell capacitor to which "1" data is written, reference numeral 2 denotes the potential of the storage node SN_L to which the "0" data is written, and reference numeral. 3 is the potential of the bit line BL_T for reading "1" data, 4 is the potential of the bit line BL_C for reading "0" data, and 5 is the output of the P-type sense amplifier driver 26. The potential of the node SAP-P, 6 is the potential of the output node SAN-N of the N-type sense amplifier driver 28, and 7 is the potential of the word line WL.
[54] As shown in Fig. 7, when the active period starts, the potential of the word line WL rises, the memory cell is selected, and data is read from the storage node of the cell capacitor into the bit line pair. Thereafter, the overdrive control signal OD is activated. During the period during which the control signal OD is activated, a signal of the "L" level is input to the gate electrode of the overdrive PMOSFET in the P-type sense amplifier driver 26 so that the PMOSFET is conducted. As a result, an overdrive potential higher than the restore potential generated by the overdrive potential generation circuit 30 is output to the P-type sense amplifier drive line 25, and the P-type sense amplifier 23 is driven by the overdrive potential. . In the period in which the overdrive control signal OD is activated, the sense drive control signal SD having the "H" level is input to the gate electrode of the sensing NMOSFET in the N-type sense amplifier driver 28, and the NMOSFET also conducts. Thereby, the ground potential is output to the N-type sense amplifier drive line 27, and the N-type sense amplifier 24 is driven by the ground potential. That is, the P-type sense amplifier driver 26 and the N-type sense amplifier driver 28 start the outputs of the overdrive potential and the ground potential at approximately the same timing. In addition, when the active period ends, the P-type sense amplifier driver 26 and the N-type sense amplifier driver 28 stop the output of the overdrive potential and the ground potential at approximately the same timing.
[55] In the precharge period after the end of the active period, the discharge control signal DSC and the bit line equalization control signal BLEQL are respectively activated. After the end of the precharge period, the discharge control signal DSC becomes inactive and the bit line precharge control signal EQLCN is activated.
[56] That is, in FIG. 7, before the potential of the word line WL rises, the bit line equalization control signal BLEQL and the bit line precharge control signal EQLCN become inactive, and after the potential of the word line WL rises, the cell data becomes a bit line. Is sent to. Thereafter, the P-type sense amplifier 23 is driven by the overdrive potential which is a potential higher than the restore potential, the N-type sense amplifier 24 is driven by the ground potential, and the potential difference between the bit line pairs 20 Is amplified. At this time, since the P-type sense amplifier 23 is driven by the overdrive potential which is a potential higher than the restore potential, the " 1 " data read from the storage node rises to a sufficiently high potential on the bit line. At this time, "1" data is restored to the storage node of the original memory cell from which the data is read. In addition, the sensed data is output to the outside of the memory through a data I / O circuit (not shown). Then, when the potential 1 of the storage node for restoring the "1" data is sufficiently charged, the overdrive operation is terminated, and the equalization operation and the discharge operation of the bit line pair 20 are subsequently performed.
[57] By the overdrive operation, the bit line potential BL_H on the side where "1" data is read among the bit line pairs rises to a quite high potential. Thus, by the discharge operation, the potential of the bit line pair including the bit line raised to the high potential is discharged. That is, in the precharge period, the discharge control signal DSC is at " H " level, and the two NMOSFETs 42 and 43 in the discharge circuit 35 are turned on, so that the bit line pair 20 is discharged to the ground potential. In the precharge period, the bit line equalization control signal BLEQL supplied from the equalization control signal line 41 also becomes " H " level, so that the NMOSFET 40 in the equalizing circuit 34 becomes conductive. As a result, the bit lines BL_T and BL_C are shorted. That is, in the precharge period, the bit lines BL_T and BL_C are rapidly discharged in a shorted state. Then, by adjusting the "H" level period of the discharge control signal DSC, the bit line reference potential after bit line discharge can be corrected to match the subsequent bit line precharge potential. 5 to 7, this corrected potential difference is indicated as the discharge level.
[58] After that, the discharge control signal DSC becomes inactive and the bit line precharge control signal EQLCN is activated. As a result, the NMOSFETs 37 and 38 in the precharge circuit 33 become conductive, and the bit lines BL_T and BL_C are precharged by the bit line precharge potential VBLEQ. During this precharge, the bit lines BL_T and BL_C are corrected to the bit line reference potential in advance, so that the potentials of the bit lines BL_T and BL_C are quickly stabilized to the bit line reference potential.
[59] In FIG. 7, the bit line equalization control signal BLEQL is still active even after the discharge control signal DSC is inactivated. However, when the discharge control signal DSC is inactive, the bit line equalization control signal BLEQL is also simultaneously. It may be made inactive.
[60] FIG. 8 representatively shows one of a plurality of timing generation circuits for adjusting and generating each control signal shown in FIG. 7 at a desired timing, respectively.
[61] The timing generating circuit 51 of FIG. 8 includes a flip-flop circuit 52 composed of two input NAND gates thereof, a delay circuit 53 composed of a resistor R and a MOS capacitor C, and two inverter circuits ( 54, 55).
[62] FIG. 9 shows an example of the operation of the timing generating circuit 51 of FIG. After the input signal input drops to the "L" level, the output signal output rises to the "H" level, and then the output signal output is at the "H" level by the time Td until the signal passes through the delay circuit 53. Keep it.
[63] The delay circuit 53 is configured to change the circuit connection by using a metal wiring, a switch or a fuse made of a transistor, although not shown, so that the resistance value of the resistor R and the capacitance value of the MOS capacitor C are changed as necessary. It is.
[64] By changing the resistance value and the capacitance value, the timing can be adjusted at an appropriate timing in the evaluation of the actual device. For example, as shown in Fig. 7, the timing of the drop of the overdrive control signal OD and the drop of the discharge control signal DSC is changed to change the period of the "H" level (activation) of the overdrive control signal OD or the discharge control signal DSC. By adjusting, it becomes possible to adjust the equalization potential of a bit line to a desired value.
[65] The bit line precharge potential VBLEQ generated by the bit line precharge potential generation circuit described later with reference to FIG. 10 is adjusted so that the bit line equalization potential matches the desired value of the equalization potential.
[66] FIG. 10 shows an example of a bit line precharge potential generating circuit that generates and adjusts the bit line precharge potential VBLEQ such that the bit line equalization potential is at a desired level.
[67] The bit line precharge potential generating circuit 61 is provided with a resistance divider circuit 62 composed of three resistors connected in series to generate two different reference voltages V1 and V2 from the power supply voltage VCC. The bit line precharge potential generating circuit 61 is provided with first and second voltage comparison circuits (operation amplifiers 63 and 64), a driver PMOSFET 65 and an NMOSFET 66. The potential VBLEQ of the bit line precharge potential line 36 is input to the non-inverting input terminal (+) of the first voltage comparison circuit 63, and the reference voltage V1 is input to the inverting input terminal (−). The output potential of this first voltage comparison circuit 63 is input to the gate electrode of the driver PMOSFET 65. The current path between the source and the drain of the driver PMOSFET 65 is inserted between the VCC node and the bit line precharge potential line 36.
[68] The potential VBLEQ of the bit line precharge potential line 36 is input to the non-inverting input terminal (+) of the second voltage comparison circuit 64, and the reference voltage V2 is input to the inverting input terminal (−). The output potential of this second voltage comparison circuit 64 is input to the gate electrode of the driver NMOSFET 66. The current path between the source and the drain of the driver NMOSFET 66 is inserted between the bit line precharge potential line 36 and the VSS node.
[69] Although not shown in the bit line precharge potential generating circuit 61 shown in FIG. 10, it is possible to change the voltage division ratio in the resistance voltage divider circuit 62 using a metal wiring, a switch or a fuse made of a transistor or the like. It is configured to. Therefore, by changing the voltage division ratio as necessary, the bit line precharge potential VBLEQ can be adjusted to a desired value.
[70] According to the DRAM according to the first embodiment, the bit line sense amplifier 22, in particular, the P-type sense amplifier 23 is driven by the overdrive potential, and the potential of the bit line on the side from which the "1" level data is read out is sufficiently made. Since it raises, the detection timing of data can be made quick. After the data is sensed, the equalization circuit 34 equalizes the bit line pairs while discharging the bit line pairs by the discharge circuit 35, so that the potential of the bit line pair 20 matches the bit line reference potential. Can be adjusted. Therefore, even if the cycle of the read operation is shortened, the cell data can be read accurately.
[71] In addition, even when one of the read data "1" and "0" has few read margins, the bit line of the cycle of the next read operation is adjusted by timing of discharge of the bit line pair 20 or adjustment of the bit line precharge potential. Since the reference potential can be adjusted, a reading margin can be earned.
[72] (2nd Example)
[73] 11 shows the configuration of some circuits of the DLXM of the second embodiment.
[74] In Fig. 11, the discharge circuit 35 includes an NMOSFET 45 in which a current path between a source and a drain is inserted between the bit line precharge potential line 36 and the discharge potential GND for supplying the bit line precharge potential VBLEQ. Consists of The discharge control signal line 44 is connected to the gate electrode of the NMOSFET 45.
[75] In the case of this second embodiment, as in the case of the first embodiment, the discharge circuit 35 is provided corresponding to each bit line pair. However, unlike the first embodiment, the discharge circuit 35 is composed of one NMOSFET 45, and the NMOSFET 45 is connected between the bit line precharge potential line 36 and the ground potential.
[76] The timing of each control signal used in the circuit of Fig. 11 is basically the same as in the first embodiment. However, in the case of FIG. 11, since the NMOSFET 45 is connected to the bit line precharge potential line 36, the bit line precharge circuit 33 also operates in the period during which the discharge circuit 35 is operating. The timing of the bit line precharge control signal EQLCN is changed.
[77] According to this structure, the discharge operation of the bit line pair 20 is performed by the discharge circuit 35 via the bit line precharge potential line 36 at the beginning of the precharge period.
[78] Thus, since the equalization potential of the bit line pair 20 can be correct | amended by discharging the electric potential of the bit line pair 20, the effect similar to 1st Example is acquired.
[79] In addition, according to the second embodiment, the effect of reducing the number of MOSFETs for discharging by half compared with the first embodiment is obtained.
[80] (Third Embodiment)
[81] 12 shows the configuration of some circuits of the DRAM of the third embodiment.
[82] In the first and second embodiments, the case where the discharge circuit 35 is provided corresponding to each bit line pair has been described. However, in this third embodiment, one discharge circuit 35 is provided for each of the plurality of bit line pairs. As in the case of the second embodiment, each discharge circuit 35 is composed of one NMOSFET 45.
[83] 13A to 13C show a state in which the discharge circuit 35 shown in FIG. 12 is distributedly arranged in an array of sense amplifiers. That is, FIG. 13A shows a part of the 32M bit array 11 shown in FIG. 1 in an enlarged manner. In addition, the bit line sense amplifier array 16 of FIG. 13A is extracted and enlarged in FIG. 13B. In addition, the bit line sense amplifier 32 and the discharge circuit 35 of each of Fig. 13B are extracted and enlarged in Fig. 13C.
[84] According to the third embodiment, the number of discharge NMOSFETs 45 can be significantly reduced in comparison with the second embodiment, except that basically the same effect is obtained by the same operation as the second embodiment. The layout area can be reduced.
[85] (Example 4)
[86] Fig. 14 shows the structure of some circuits of the DRAM of the fourth embodiment.
[87] In this fourth embodiment, as in the third embodiment, one discharge circuit 35 is provided for each of the plurality of bit line pairs. However, unlike the third embodiment, the switch circuit 47 made of the NMOSFET 46 is inserted in the middle of the bit line precharge potential line 36a branched from the bit line precharge potential line 36. The bit line equalization control signal BLEQL is supplied to the gate electrode of the NMOSFET 46.
[88] In the circuit shown in Fig. 14, the following (1) and (2) are different from each other in comparison with the circuit of the third embodiment shown in Fig. 12, and others are the same.
[89] (1) The switch circuit 47 is inserted in the middle of the bit line precharge potential line 36a closer to the bit line precharge potential line 36 than the connection node of the discharge circuit 35. The switch circuit 47 is controlled by the bit line equalization control signal BLEQL so that the activation period of the discharge control signal DCS is turned off.
[90] (2) The bit line precharge control signal EQLCN is supplied from the same wiring 41 as the bit line equalization control signal BLEQL, i.e., both the precharge circuit 33 and the equalizing circuit 34 are bit line equalizing control signals. Controlled by BLEQL.
[91] The operation of the circuit of FIG. 14 is basically the same as the operation of the circuit described above with reference to FIG. 12, but the precharge circuit 33 and the equalizing circuit 34 are controlled at the same timing, and discharge The point that the switch circuit 47 is controlled to the off state when the circuit 35 is operating differs from each other.
[92] Accordingly, the bit line precharge potential line 36a is discharged by the discharge circuit 35 at an initial stage during the precharge equalization operation of the bit line pair 20 by the bit line precharge equalization circuit 32. The discharge operation of the bit line pair 20 is performed through this. In this discharge operation, since the switch circuit 47 is controlled to the off state, the influence of the discharge operation on other circuits through the bit line precharge signal line 36 is prevented.
[93] 15A to 15C show a state in which the discharge circuit 35 shown in FIG. 14 is distributedly arranged in an array of sense amplifiers. That is, FIG. 15A is an enlarged view of a part of the 32M bit array 11 shown in FIG. In addition, the bit line sense amplifier array 16 of FIG. 15A is extracted and enlarged in FIG. 15B. In addition, the bit line sense amplifier 32, the discharge circuit 35, and the switch circuit 47 of each of Fig. 15B are extracted and enlarged in Fig. 15C.
[94] According to the fourth embodiment, basically, the same effect is obtained by the same operation as the third embodiment, and the operation of the discharge circuit 35 extends to other circuits through the bit line precharge signal line 36. In this case, the bit line precharge control signal line dedicated to the precharge circuit 33 can be omitted, so that the number of wirings can be reduced by one compared with the circuit of the third embodiment.
[95] If the precharge circuit 33 and the equalization circuit 34 are controlled at the same timing as described in the fourth embodiment, the wirings of the first to third embodiments are used as they are and the precharge circuit 33 is used. It is also possible to supply the bit line precharge control signal for controlling the control signal and the bit line equalization control signal for controlling the equalizing circuit 34 from separate wirings.
[96] Additional advantages and modifications can be readily realized by those skilled in the art, and therefore, the scope of the present invention is not limited to the above description and examples. Accordingly, various modifications may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims and their equivalents.
[97] According to the present invention, the bit line reference potential at the time of reading the bit line potential can be adjusted by the bit line sense amplifier adopting the overdrive method, and the semiconductor can read the cell data accurately even if the cycle of the read operation is shortened. Memory can be provided.

权利要求:
Claims (25)
[1" claim-type="Currently amended] A plurality of memory cells,
A plurality of bit line pairs connected to the plurality of memory cells,
A plurality of bit line sense amplifiers connected to the plurality of bit line pairs and amplifying the potentials of the plurality of bit line pairs, respectively;
An overdrive potential generation circuit for generating an overdrive potential,
A first sense amplifier driver connected to each of the plurality of bit line sense amplifiers and the overdrive potential generating circuit, the first sense amplifier driver outputting the overdrive potential to the bit line sense amplifier;
A second sense amplifier driver connected to the bit line sense amplifier and outputting the predetermined potential to the bit line sense amplifier;
A plurality of bit line precharge / equalization circuits connected to the plurality of bit line pairs and the precharge potential, and precharge the plurality of bit line pairs by the precharge potential, and equalize the potential of each bit line pair;
At least one discharge circuit coupled to the plurality of bit line pairs and discharging the potentials of the plurality of bit line pairs to a discharge potential
Semiconductor memory device comprising a.
[2" claim-type="Currently amended] The method of claim 1,
The overdrive potential generating circuit generates a potential higher than the restore potential of the plurality of bit line pairs as the overdrive potential.
[3" claim-type="Currently amended] The method of claim 1,
And the discharge potential is a ground potential.
[4" claim-type="Currently amended] The method of claim 1,
And the overdrive potential is higher than the precharge potential.
[5" claim-type="Currently amended] The method of claim 1,
And a precharge potential generation circuit for generating the precharge potential, wherein the precharge potential generation circuit has a function of adjusting the precharge potential.
[6" claim-type="Currently amended] The method of claim 1,
Each of the plurality of bit line sense amplifiers,
A first sense amplifier connected to a corresponding bit line pair of the plurality of bit line pairs and the first sense amplifier driver;
And a second sense amplifier connected to a corresponding bit line pair of the plurality of bit line pairs and the second sense amplifier driver.
[7" claim-type="Currently amended] The method of claim 6,
Wherein the first sense amplifier comprises two PMOSFETs and the second sense amplifier comprises two NMOSFETs.
[8" claim-type="Currently amended] The method of claim 1,
And the first sense amplifier driver and the second sense amplifier driver start output of the overdrive potential and the predetermined potential at approximately the same timing, and stop the output respectively after a predetermined period.
[9" claim-type="Currently amended] The method of claim 6,
The first sense amplifier driver,
A PMOSFET having a first current path, wherein the first current path is inserted between the overdrive potential generation circuit and the first sense amplifier,
The second sense amplifier driver,
And a NMOSFET having a second current path, wherein the second current path is inserted between the second sense amplifier and the predetermined potential.
[10" claim-type="Currently amended] The method of claim 9,
And the PMOSFET and the NMOSFET are controlled to conduct at approximately the same timing.
[11" claim-type="Currently amended] The method of claim 9,
And the PMOSFET and the NMOSFET are controlled to conduct after the plurality of memory cells are selected.
[12" claim-type="Currently amended] The method of claim 1,
And said at least one discharge circuit is controlled in accordance with a discharge control signal.
[13" claim-type="Currently amended] The method of claim 12,
And a discharge control signal generation circuit for generating the discharge control signal, wherein the discharge control signal generation circuit has a function of adjusting an active period of the discharge control signal.
[14" claim-type="Currently amended] The method of claim 8,
After the output of the overdrive potential and the predetermined potential from the first sense amplifier driver and the second sense amplifier driver are stopped, the at least one discharge circuit discharges the potentials of the plurality of bit line pairs to a discharge potential. A semiconductor memory device that initiates an operation.
[15" claim-type="Currently amended] The method of claim 1,
The at least one discharge circuit is a plurality of discharge circuits provided corresponding to each of the plurality of bit line pairs,
Each of the plurality of discharge circuits,
A first NMOSFET having a first current path, wherein the first current path is inserted between one bit line of the corresponding bit line pair and the discharge potential;
And a second NMOSFET having a second current path, wherein the second current path is inserted between the other bit line of the corresponding bit line pair and the discharge potential.
[16" claim-type="Currently amended] The method of claim 15,
And the first and second NMOSFETs operate during a period of discharging the potentials of the plurality of bit line pairs to a discharge potential.
[17" claim-type="Currently amended] The method of claim 1,
The at least one discharge circuit is a plurality of discharge circuits provided corresponding to each of the plurality of bit line pairs,
Each of the plurality of discharge circuits,
And a NMOSFET having a current path in which the current path is inserted between the precharge potential and the discharge potential.
[18" claim-type="Currently amended] The method of claim 1,
The at least one discharge circuit is a plurality of discharge circuits correspondingly provided for any number of bit line pairs among the plurality of bit line pairs,
The plurality of discharge circuits, respectively
And a NMOSFET having a current path in which the current path is inserted between the precharge potential and the discharge potential.
[19" claim-type="Currently amended] The method of claim 17 or 18,
And the NMOSFET operates in a period of discharging the potentials of the plurality of bit line pairs to a discharge potential.
[20" claim-type="Currently amended] The method of claim 18,
And a switch circuit inserted in the middle of the signal line for supplying the precharge potential.
[21" claim-type="Currently amended] The method of claim 20,
And the switch circuit is controlled to be non-conductive during a period during which the discharge operation of the precharge potential line is performed by the plurality of discharge circuits, and to be conductive when the discharge operation is not performed.
[22" claim-type="Currently amended] The method of claim 20,
And the switch circuit comprises an NMOSFET.
[23" claim-type="Currently amended] The method of claim 1,
The plurality of bit line precharge equalization circuits, respectively,
A precharge circuit connected to said precharge potential and a corresponding bit line pair among said plurality of bit line pairs, and precharges a corresponding bit line pair to said precharge potential;
And an equalization circuit connected to a corresponding bit line pair among the plurality of bit line pairs and equalizing the corresponding bit line pair.
[24" claim-type="Currently amended] The method of claim 23, wherein
The precharge circuit,
A first NMOSFET having a first current path, wherein the first current path is inserted between one bit line of the corresponding bit line pair among the plurality of bit line pairs and the precharge potential;
And a second NMOSFET having a second current path, wherein the second current path is inserted between the other bit line of the corresponding bit line pair among the plurality of bit line pairs and the precharge potential.
[25" claim-type="Currently amended] The method of claim 23, wherein
The equalization circuit,
And a NMOSFET having a current path, wherein the current path is inserted between one and the other bit lines of the corresponding bit line pair among the plurality of bit line pairs.

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同族专利:

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公开号 | 公开日

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TW588356B|2004-05-21|

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JP2003228981A|2003-08-15|

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KR100567686B1|2006-04-05|

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US6754122B2|2004-06-22|

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TW200400510A|2004-01-01|

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US20030174545A1|2003-09-18|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2002-02-05|Priority to JPJP-P-2002-00028559

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2002-02-05|Priority to JP2002028559A

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2003-02-04|Application filed by 가부시끼가이샤 도시바, 후지쯔 가부시끼가이샤

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2003-08-09|Publication of KR20030066440A

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2006-04-05|Application granted

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2006-04-05|Publication of KR100567686B1

优先权:

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申请号 | 申请日 | 专利标题

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JPJP-P-2002-00028559|2002-02-05|

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JP2002028559A|JP2003228981A|2002-02-05|2002-02-05|Semiconductor memory device|