Phase locked loop circuit for reducing electromagnetic interference and control method thereof

专利摘要:
PURPOSE: A phase locked loop(PLL) to reduce electromagnetic interference and a control method thereof are provided, which reduces electromagnetic interference effectively by reducing an energy level of frequencies generated from the electromagnetic interference in a broadband. CONSTITUTION: The phase locked loop(PLL) to reduce electromagnetic interference includes a phase comparator(10) comparing phases of a reference clock signal(Fref) and a feedback clock signal(Ffb) and outputting an up signal(UP) or a down signal(DN) according to the comparison result, and a charge pump(12) generating a charge signal to supply or sink charges in response to the up signal or the down signal, and a loop filter(14) generates a DC control voltage by filtering the charge signal in a low pass band. A voltage controlled oscillator(16) generates an output clock signal oscillated as an oscillation frequency corresponding to the control voltage. A multi phase interpolator(18) generates overlapping signals(CLK0-CLKn-1) having an offset using the output clock signal. And a feedback signal output part(24) judges whether the feedback clock signal is locked to the reference clock signal by inputting the up/down signal, and outputs the output clock signal as the feedback clock signal before it is locked, and outputs the feedback clock signal by selecting overlapping clock signals sequentially when it is locked.
公开号:KR20030001825A
申请号:KR1020010037632
申请日:2001-06-28
公开日:2003-01-08
发明作者:김상영；전필재
申请人:삼성전자 주식회사；
IPC主号:

专利说明:

Phase locked loop circuit for reducing electromagnetic waves and a control method thereof
[9] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) circuit, and more particularly, to a phase locked loop and a control method thereof for reducing the occurrence of electromagnetic interference (EMI) in a high speed system.
[10] Recently, the system is getting faster, and the data processing speed is getting faster for the system. As such, a clock signal operating at a high speed is required to speed up the data processing. On the other hand, when generating a high-speed clock signal, the clock signal includes a harmonic component, the electromagnetic wave harmful to the human body is generated by such a harmonic component. In order to reduce these electromagnetic waves, shielding or capacitance has been used in the past to reduce electromagnetic waves of a system. However, the use of shielding or capacitance is limited in reducing the electromagnetic waves of the system.
[11] On the other hand, the most frequently generated electromagnetic waves in the system is a clock generator for generating a high-speed clock signal. That is, electromagnetic waves are generated due to a large number of harmonics in a high speed clock signal. Recently, technologies for reducing electromagnetic waves by lowering the energy level of such harmonics have been developed. Generally, a phase locked loop (PLL) is used to generate a clock signal, and the phase locked loop generates a modulated clock signal known as a spread spectrum to lower the energy level of harmonics included in the clock signal. .
[12] A method of generating a clock signal modulated as described above in a phase locked loop circuit is classified into a phase modulation method and a frequency modulation method. As a phase modulation method, a sigma delta modulation method is used. This is a technique that modulates a phase difference between a reference input frequency and a feedback frequency in a sigma delta modulation block in a phase locked loop, thereby lowering electromagnetic energy levels through fine control of current through a charge pump block. In addition, the frequency modulation scheme is a technique of reducing electromagnetic energy by utilizing a phase lock range of a PLL circuit by using a multi-stage counter or ROM while feeding back a frequency generated from a voltage controlled oscillator in a phase locked loop circuit.
[13] However, as described above, the spread spectrum clock signal generator using the sigma delta modulation method or the ROM code is designed to attenuate the energy level of the frequency appearing at a specific frequency, and has a problem in that the characteristic variation is severe depending on the process characteristics. . In addition, since the physical data size of the PLL circuit is large and timing adjustment between neighboring blocks is difficult when controlling the PLL circuit, malfunction of the PLL circuit is caused.
[14] An object of the present invention is to provide a phase locked loop circuit which effectively reduces electromagnetic waves by reducing energy levels of frequencies generated by electromagnetic waves in a wide frequency band by a simple control method.
[15] Another object of the present invention is to provide a method of controlling the phase-locked loop circuit to reduce the energy level of the frequency generated by electromagnetic waves in a wide frequency band.
[1] 1 is a block diagram schematically showing an embodiment of a phase locked loop circuit for reducing electromagnetic waves according to the present invention.
[2] FIG. 2 is a circuit diagram of one embodiment of the multi-phase interpolator 18 and voltage controlled oscillator 16 shown in FIG.
[3] FIG. 3 is a waveform diagram illustrating first to 63rd non-overlapping clock signals CLK0 to CLK63 output from the multi-phase interpolator in FIG. 2, respectively.
[4] 4 illustrates an embodiment of the clock selector 20 illustrated in FIG. 1.
[5] FIG. 5 illustrates input / output signals of the apparatus shown in FIG. 4.
[6] FIG. 6 is a waveform diagram showing the control voltage Vc generated in the loop filter 14 after the phase locked loop shown in FIG. 1 is locked.
[7] FIG. 7 illustrates that the frequency of the clock signal CK output from the voltage controlled oscillator 16 shown in FIG. 1 is modulated according to the control voltage Vc shown in FIG.
[8] 8A and 8B are diagrams illustrating an electromagnetic attenuation effect of the phase locked loop shown in FIG. 1.
[16] In order to achieve the above object, a phase comparator for comparing a phase of a reference clock signal input from an external source and a feedback clock signal, and outputting or sinking a charge in response to a phase comparator, an up or down signal according to the result of the comparison. The phase-locked loop circuit according to the present invention for reducing electromagnetic waves, including a charge pump for generating a charge signal for generating a charge signal and a loop filter for generating a control voltage of direct current by low-pass filtering the charge signal, has an oscillation frequency corresponding to the control voltage. A voltage controlled oscillator for generating an oscillating output clock signal, a multiphase interpolator for generating first to nth non-overlapping signals having a predetermined offset so as not to overlap each other using an output clock signal, and an up / down signal It is determined whether the feedback clock signal is locked to the reference clock signal. Outputting a clock signal as the feedback clock signal, and when the lock comprises first to n-th non-overlapping clock signals for ascending / descending order are sequentially selected by the parts of the feedback clock signal output for outputting a feedback clock signal.
[17] In order to achieve the above object, a phase comparator for comparing a phase of a reference clock signal input from an external source and a feedback clock signal, and outputting or sinking a charge in response to a phase comparator, an up or down signal according to the result of the comparison. The phase-locked loop circuit according to the present invention for reducing electromagnetic waves, including a charge pump for generating a charge signal for generating a charge signal and a loop filter for generating a control voltage of direct current by low-pass filtering the charge signal, each of the first predetermined circuits does not overlap each other. A voltage controlled oscillator which generates m clock signals having an offset of m and is generated as an output clock signal by selecting one of m clock signals, and has a second predetermined offset so as not to overlap each other using m clock signals Input a multiphase interpolator and an up / down signal to generate a 1 to nth non-overlapping clock signal. It determines whether the feedback clock signal is locked to the reference clock signal, and outputs the output clock signal as the feedback clock signal before locking, and sequentially locks the first to nth non-overlapping clock signals in ascending / descending order. And a feedback clock signal output section for selecting and outputting the feedback clock signal.
[18] In order to achieve the above object, a phase comparator for comparing a phase of a reference clock signal input from an external source and a feedback clock signal, and supplying or sinking charges in response to a phase comparator, an up or down signal according to the result of the comparison A phase-locked loop circuit including a charge pump for generating a charge signal, a loop filter for low-pass filtering the charge signal to generate a DC control voltage, and a voltage controlled oscillator for outputting a clock signal having an oscillation frequency corresponding to the control voltage In the phase locked loop control method according to the present invention for reducing electromagnetic waves, (a) generating first to nth non-overlapping clock signals having a predetermined offset so as not to overlap each other using a clock signal, The phase locked loop is locked in steps (b) and (b) of determining whether the phase locked loop is locked using the down signal. If it is determined that the first to nth non-overlapping clock signal, the signal having the same phase as the clock signal is selected as a feedback clock signal to generate a phase comparator and proceed to step (a) and (b) and (b). If it is determined that the phase lock loop is locked in step), the first to n-th non-overlapping clock signals are sequentially selected in an ascending / descending order to be generated as a feedback clock signal.
[19] Hereinafter, with reference to the accompanying drawings, a phase synchronization loop circuit for reducing electromagnetic waves according to the present invention will be described.
[20] 1 is a block diagram schematically showing an embodiment of a phase locked loop circuit for reducing electromagnetic waves in a broadband according to the present invention. The broadband electromagnetic cancellation phase locked loop according to the embodiment of the present invention includes a phase comparator 10, a charge pump 12, a loop filter 14, a voltage controlled oscillator 16, a multi-phase interpolator 18, and a feedback clock. And an output unit 24.
[21] Referring to FIG. 1, the phase comparator 10 compares a phase of a reference clock signal Fref and a feedback clock signal Ffb output from the clock selector 24, and compares the result of the up / down signal UP. / DN). The charge pump 12 generates a charge signal for supplying charge to the loop filter 14 or sinking charge from the loop filter 14 in response to the up / down signal UP / DN.
[22] The loop filter 14 outputs a voltage corresponding to the charge signal generated from the charge pump 12 to the voltage controlled oscillator 16 as a control voltage.
[23] The voltage controlled oscillator 16 outputs a clock signal oscillated at an oscillation frequency corresponding to the control voltage generated from the loop filter 14 to the output terminal OUT.
[24] The multiphase interpolator 18 uses first to nth non-overlapping clock signals CLK0 to CLKn-1 having a predetermined offset so as not to overlap each other using the clock signal CK output from the voltage controlled oscillator 16. Occurs. The offset between the overlapping clock signals corresponds to one width obtained by dividing one period of the clock signal CK by n, and the first non-overlapping clock signal CLK0 has the same phase as the clock signal CK. Shall be.
[25] The feedback clock output unit 24 inputs an up / down signal UP / DN generated by the phase comparator 10 to determine whether the feedback clock signal Ffb is locked to the clock signal CK. The feedback clock output unit 24 supplies the first non-overlapping clock signal CLK0 having the same phase as the clock signal CK until the feedback clock signal Ffb is locked to the reference clock signal Fref. It outputs to the phase comparator 10 as (Fbf). Meanwhile, when the feedback clock signal Ffb is locked to the reference clock signal Fref, the first to nth non-overlapping clock signals CLK0 to CLKn-1 are sequentially selected in the ascending / descending order. The non-overlapping clock signal is output to the phase comparator 10 as a feedback clock signal Ffb. Preferably, the feedback clock output 24 includes a clock selector 20 and a lock detector 22.
[26] The lock detector 22 determines whether or not the feedback clock signal Ffb is locked to the reference clock signal Fref in response to the up / down signal UP / DN output from the phase comparator 10. Is output to the clock selector 20 as a lock discrimination signal ROCK.
[27] The clock selector 22 sequentially selects the first to nth non-overlapping clock signals CLK0 to CLKn-1 in ascending and descending order in response to the lock discrimination signal ROCK, and selects the selected overlap clock signal. The feedback clock signal Ffb is output to the phase comparator 10. Here, when the clock selector 22 selects the non-overlapping clock signal in ascending order, the clock selector 22 sequentially selects and outputs the first non-overlapping clock signal CLK0 to the n-th non-overlapping clock signal CLKn-1. . When the clock selector 22 selects the non-overlapping clock signal in descending order, the clock selector 22 sequentially selects and outputs the nth non-overlapping clock signal CLKn-1 to the first non-overlapping clock signal CLK0. .
[28] Meanwhile, the clock selector 24 selects some consecutive non-overlapping clock signals among the n non-overlapping clock signals in ascending and descending order in response to an up / down signal UP / DN indicating a locked state. You can print
[29] FIG. 2 is a circuit diagram of one embodiment of the multi-phase interpolator 18 and voltage controlled oscillator 16 shown in FIG. The voltage controlled oscillator 16 and the multi-phase interpolator 18 shown in FIG. 2 include a plurality of delayers D1 to D64. In FIG. 2, for convenience of description, the multi-phase interpolator 18 generates the first to 64th non-overlapping clock signals CLKO to CLK63.
[30] Referring to FIG. 2, the voltage controlled oscillator 16 is a ring oscillator composed of 16 delayers D1 to D16. The delay time is determined by the control voltage Vcnt of the 16 delays D1 to D16 constituting the ring oscillator, and the frequency of the clock signal CLK output from the delay D16 is determined according to the delay time. . In each of the sixteen delay units D1 to D16 constituting the ring oscillator, delay signals having a predetermined offset and not inverted with each other are output. As a result, the voltage controlled oscillator 16 including the delayers D1 to D16 outputs the first to 32nd delay signals DS0 to DS31 having predetermined offsets that do not overlap each other.
[31] The first to 32nd delay signals DS0 to DS31 output from the voltage controlled oscillator 16 are delayed again through the delayers D17 to D64 constituting the multi-phase interpolator 18, and these are shown in FIG. 2. As described above, the first to 64th non-overlap clock signals CLK0 to CLK63 are generated. At this time, the delayers D17 to D64 have the same delay characteristics, and each of the first to 64th non-overlapping clock signals CLK0 to CLK63 has a predetermined offset so as not to overlap each other.
[32] FIG. 3 is a waveform diagram illustrating first to 63rd non-overlapping clock signals CLK0 to CLK63 output from the multi-phase interpolator in FIG. 2, respectively. Referring to FIG. 3, it is shown that each of the first to 63rd non-overlapping clock signals CLK0 to CLK63 is delayed with a predetermined offset.
[33] 4 illustrates an embodiment of the clock selector 20 illustrated in FIG. 1. The clock selector illustrated in FIG. 4 includes an up / down counter 30 and a selector 32. For convenience of explanation, the up / down counter 30 shown in FIG. 4 is a 6-bit up / down counter, and is assumed to be.
[34] FIG. 5 illustrates input / output signals of the apparatus shown in FIG. 4. 5A to 5D show feedback clock signals, FIG. 5E shows a non-overlapping clock signal input to the up / down counter 30, and FIG. Each of the output feedback clock signals Ffb is shown.
[35] 4 and 5, the up / down counter 30 is a 6-bit counter as described above, and counts the non-overlapping clock signal shown in FIG. 5 (e) in response to the lock discrimination signal LOCK. The counting result is output to the selector 32 as a 6-bit select signal SEL. Here, the non-overlapping clock signal input to the up / down counter 30 is one of the first to 63rd non-overlapping clock signals CLK0 to CLK63. In the present embodiment, the first non-overlapping clock signal ( CLK0). As a result, the 6-bit up / down counter 30 sequentially counts up to 0 to 63 in response to the lock discrimination signal LOCK, and then repeats down counting again to 63 to 0.
[36] The selector 32 receives the first to 63rd non-overlapping clock signals CLK0 to ˜63 from the multi-phase interpolator 18 in response to the 6-bit selection signal SEL input from the up / down counter 30. One of CLK63 is selected and output as the feedback signal Ffb. That is, the selector 32 sequentially selects and outputs the first to the 64th non-non-overlapping clock signals CLK0 to CLK63 in response to the counting result of the up / down counter 30, and then outputs the 64th to the first. The non-overlapping clock signals CLK63 to CLK0 are sequentially selected and output. As a result, the selector 32 counts the first non-overlapping clock signal CLK0 by 1 in the period T1 in which the up / down counter 30 counts 0, as shown in FIG. 5 (f). In the period T2, the second non-overlapping clock signal CLK1 is selectively output. In the period T3 in which the second non-overlapping clock signal CLK1 is counted, the third non-overlapping clock signal CLK2 is output. In the period T63 in which the up / down counter 30 counts 63, the 64th non-overlapping clock signal CLK63 is selectively output.
[37] On the other hand, if the up / down counter 30 is a 5-bit counter and the initial value is set to 16, the up / down counter 30 counts up / down between 16 and 47 in response to the lock determination signal LOCK. do. The selector 32 selects and outputs the sixteenth to 47th non-overlapping clock signals CLK15 to CLK46 according to the counting result of the up / down counter 30.
[38] FIG. 6 is a waveform diagram showing the control voltage Vc generated in the loop filter 14 after the phase locked loop shown in FIG. 1 is locked. Referring to FIG. 6, it is shown that the control voltage Vc is increased and decreased periodically. That is, when the phase locked loop shown in FIG. 1 is locked, the feedback clock signal output unit 24 sequentially selects the first to 64th non-overlapping clock signals CLK0 to CLK63 with a phase delay in ascending and descending order. It outputs as clock signal Ffb. As a result, a phase difference is generated between the reference clock signal Fref and the feedback clock signal Ffb, and the control voltage Vc changes as much as the phase difference. That is, while the feedback clock signal output unit 24 sequentially generates the first to 64th non-overlapping clock signals CLK0 to CLK63, the phase difference between the reference clock signal Fref and the feedback clock signal Ffb becomes larger. Therefore, the control voltage Vc generated by the loop filter 14 becomes larger. On the other hand, while the feedback clock signal output unit 24 sequentially generates the 64th to 1st non-overlap clock signals CLK63 to CLK0, the phase difference between the reference clock signal Fref and the feedback clock signal Ffb gradually decreases. Therefore, the control voltage Vc generated by the loop filter 14 becomes smaller. As a result, the control voltage Vc generated in the loop filter 14 is modulated in the form of a sine wave, as shown in FIG. By the modulation of the control voltage Vc, modulation is generated in the clock signal CK generated by the voltage controlled oscillator 16, and as a result, electromagnetic waves generated in the clock signal CK can be reduced.
[39] FIG. 7 illustrates that the frequency of the clock signal CK output from the voltage controlled oscillator 16 shown in FIG. 1 is modulated according to the control voltage Vc shown in FIG.
[40] Referring to FIG. 7, the clock signal CK, which is the output of the voltage controlled oscillator 14, does not output the clock signal CK having the frequency locked to the reference clock signal Fref after the phase locked loop is locked. The modulated clock signal is output in response to the control voltage Vc shown in FIG.
[41] 8A and 8B are diagrams illustrating an electromagnetic attenuation effect of the phase locked loop shown in FIG. 1. FIG. 8A illustrates an electromagnetic wave energy level included in a clock signal output from a general PLL circuit. Here, the general PLL circuit does not use the multi-phase interpolator 18 and the clock selector 20 in the circuit shown in FIG. 1, and replaces the clock signal CK generated by the voltage controlled oscillator 14 with a phase comparator ( It shall have a structure to input directly into 10). FIG. 8B is a diagram illustrating an electromagnetic wave energy level included in a clock signal output from the phase locked loop shown in FIG. 1. In addition, for convenience of explanation, it is assumed that the phase locked loop shown in FIG. 1 generates a clock of 160 MHz. 8A and 8B, the absolute values of the electromagnetic wave energy included in the clock signal output from each phase locked loop are taken as absolute values, and the absolute values are expressed in decibels. Display.
[42] Referring to FIG. 8A, a clock signal output in a general phase locked loop includes a great deal of white noise over all frequencies. Currently, according to the electromagnetic regulations set forth by the Federal Communications Commission (FCC), the energy level of electromagnetic waves generated from TVs, computers, mobile phones, etc. is set to 47 DBM or less. According to this rule, a phase locked loop that generates the output shown in FIG. 8A does not meet FCC regulations.
[43] However, referring to FIG. 8B, it is shown that most of the white noises have been removed over all frequencies. That is, the PLL circuit according to the present invention shown in FIG. 1 can fully satisfy FCC regulations.
[44] As described above, the phase-locked loop circuit according to the present invention uses a multi-phase interpolator 16 and a feedback clock signal output unit 18 having a simple circuit configuration to feedback the control voltage of the voltage controlled oscillator 14. The clock signal may be generated to attenuate electromagnetic waves present in the clock signal CK generated by the voltage controlled oscillator 14. In addition, the phase-locked loop circuit according to the present invention can effectively reduce the energy of the frequency generated by electromagnetic waves in the wide frequency band as well as a specific frequency.
[45] The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
[46] As described above, the phase-locked loop circuit and its control method for reducing the electromagnetic wave according to the present invention can simplify the simple circuit configuration, and effectively reduce the energy of the frequency generated by the electromagnetic waves in a wide frequency band as well as a specific frequency. Can be.

权利要求:
Claims (11)
[1" claim-type="Currently amended] A phase comparator for comparing a phase of a reference clock signal input from an external source and a feedback clock signal, and outputting an up or down signal according to the comparison result, and a charge signal for supplying or sinking charge in response to the up or down signal; A phase locked loop circuit for reducing electromagnetic waves comprising a charge pump generated and a low pass filtering of the charge signal to generate a DC control voltage.
A voltage controlled oscillator for generating an output clock signal oscillated at an oscillation frequency corresponding to the control voltage;
A multiphase interpolator for generating first to nth non-overlapping signals having a predetermined offset so as not to overlap each other using the output clock signal; And
It is determined whether the feedback clock signal is locked to the reference clock signal by inputting the up / down signal, and outputs the output clock signal as the feedback clock signal before being locked, and if locked, the first to nth non-over And a feedback clock signal output unit which sequentially selects a lapping clock signal in an ascending / descending order and outputs the feedback clock signal as the feedback clock signal.
[2" claim-type="Currently amended] The method of claim 1, wherein the feedback clock signal output unit
A lock detector for inputting the up / down signal to determine whether the feedback clock signal is locked to the reference clock signal, and outputting a determination result as a lock discrimination signal; And
A clock which outputs the output clock signal as the feedback clock signal in response to the lock discrimination signal, or sequentially selects the first to nth non-overlapping clock signals in ascending / descending order and outputs the feedback clock signal as the feedback clock signal; A phase locked loop circuit including a selection unit.
[3" claim-type="Currently amended] The clock selector of claim 2, wherein the clock selector
An up / down counter outputting a predetermined counter value as a selection signal or up / down counting the output clock signal in response to the lock determination signal, and outputting a counted result as the selection signal; And
A selector configured to input the first to n-th non-overlap clock signals, select one of the first to n-th non-overlap overlapped clock signals, and output the selected one of the first to n-th non-overlap clock signals as the feedback clock signal;
And said predetermined counter value corresponds to a non-overlapping clock signal having the same phase as said output clock signal among said first to nth non-overlapping clock signals.
[4" claim-type="Currently amended] 4. The phase of claim 3, wherein the up / down counter generates the selection signal such that the selector selects some consecutive non-overlapping clock signals from among the first to nth non-overlapping clock signals. Synchronous loop circuit.
[5" claim-type="Currently amended] A phase comparator for comparing a phase of a reference clock signal input from an external source and a feedback clock signal, and outputting an up or down signal according to the comparison result, and a charge signal for supplying or sinking charge in response to the up or down signal; A phase locked loop circuit for reducing electromagnetic waves comprising a charge pump generated and a low pass filtering of the charge signal to generate a DC control voltage.
A voltage controlled oscillator for generating m clock signals each having a first predetermined offset so as not to overlap each other, and selecting one of the m clock signals to generate an output clock signal;
A multiphase interpolator for generating first to nth non-overlapping clock signals having a second predetermined offset such that the m clock signals do not overlap each other; And
It is determined whether the feedback clock signal is locked to the reference clock signal by inputting the up / down signal, and outputs the output clock signal as the feedback clock signal before being locked, and if locked, the first to nth non-over And a feedback clock signal output unit which sequentially selects lapping clock signals in ascending / descending order and outputs the feedback clock signal as the feedback clock signal.
[6" claim-type="Currently amended] The method of claim 5, wherein the feedback clock signal output unit
A lock detector for inputting the up / down signal to determine whether the feedback clock signal is locked to the reference clock signal, and outputting a determination result as a lock discrimination signal; And
A clock selection for outputting the output clock signal as the feedback clock signal in response to the lock discrimination signal, or sequentially selecting the first to nth non-overlapping signals in ascending / descending order and outputting the feedback clock signal as the feedback clock signal; Phase locked loop circuit comprising a portion.
[7" claim-type="Currently amended] The method of claim 6, wherein the clock selector
An up / down counter outputting a predetermined counter value as a selection signal or up / down counting the output clock signal in response to the lock determination signal, and outputting a counted result as the selection signal; And
A selector configured to input the first to n-th non-overlap clock signals, select one of the first to n-th non-overlap overlapped clock signals, and output the selected one of the first to n-th non-overlap clock signals as the feedback clock signal;
And said predetermined counter value corresponds to a non-overlapping clock signal having the same phase as said output clock signal among said first to nth non-overlapping clock signals.
[8" claim-type="Currently amended] 8. The phase of claim 7, wherein the up / down counter generates the selection signal such that the selection unit selects a plurality of consecutive non-overlapping clock signals among the first to nth non-overlapping clock signals. Synchronous loop circuit.
[9" claim-type="Currently amended] A phase comparator for comparing a phase of a reference clock signal input from an external source and a feedback clock signal, and outputting an up / down signal according to a result of comparison, and a charge signal for supplying or sinking charge in response to the up or down signal. In a phase locked loop circuit including a charge pump generated, a loop filter for low-pass filtering the charge signal to generate a DC control voltage and a voltage controlled oscillator for outputting a clock signal having an oscillation frequency corresponding to the control voltage. In the control method of the phase locked loop circuit for reducing
(a) generating first to nth non-overlapping clock signals having a predetermined offset so as not to overlap each other using the clock signals;
determining whether the phase locked loop is locked using the up / down signals;
(c) if it is determined in step (b) that the phase lock loop is not locked, a signal having the same phase as the clock signal is selected as the feedback clock signal from the first to nth non-overlapping clock signals; Generating a phase comparator and proceeding to step (a); And
(d) if it is determined in step (b) that the phase locked loop is locked, sequentially selecting the first to nth non-overlapping clock signals in ascending / descending order to generate the feedback clock signal; Phase locked loop control method, characterized in that.
[10" claim-type="Currently amended] The method of claim 9, wherein step (d)
(d1) if it is determined in step (b) that the phase locked loop is locked, counting up and down the clock signal; And
and (d2) selecting one of the first to nth non-overlapping clock signals as the feedback clock signal according to the result counted in step (d1).
[11" claim-type="Currently amended] 11. The method of claim 10, wherein step (d2) corresponds to a result of counting in step (d1), ascending / descending a portion of consecutive non-overlapping clock signals among the first to n-th non-overlapping clock signals. And sequentially generating the feedback clock signal as the feedback clock signal.

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同族专利:

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公开号 | 公开日

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KR100374648B1|2003-03-03|

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US6888412B2|2005-05-03|

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US20040001600A1|2004-01-01|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2001-06-28|Application filed by 삼성전자 주식회사

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2001-06-28|Priority to KR20010037632A

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2003-01-08|Publication of KR20030001825A

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2003-03-03|Application granted

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2003-03-03|Publication of KR100374648B1

优先权:

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申请号 | 申请日 | 专利标题

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KR20010037632A|KR100374648B1|2001-06-28|2001-06-28|Phase locked loop circuit for reducing electromagnetic interference and control method thereof|