Method for fabricating contacts of semiconductor device

专利摘要:
PURPOSE: A method for manufacturing the contact of a semiconductor device is provided to reduce the contact resistance of an upper electrode by contact etching between multi-layers. CONSTITUTION: A lower electrode(10) of a capacitor is formed on a semiconductor substrate. After forming a dielectric film on the lower electrode, an upper electrode(12) is formed on the dielectric film. After forming an oxide layer(14) on the resultant structure, an active contact(18) is formed by selectively etching the oxide layer(14). A first metal wire(20) is formed to connect with the active contact(18). An inter-metal insulating layer(22) is formed on the resultant structure. A via contact(24) and a capacitor contact are simultaneously formed by selectively etching the inter-metal insulating layer(22). A second metal wire(26) is formed to connect with the via contact and the capacitor contact.
公开号:KR20020058481A
申请号:KR1020000086588
申请日:2000-12-30
公开日:2002-07-12
发明作者:박원성；박수영；이홍구
申请人:박종섭；주식회사 하이닉스반도체；
IPC主号:

专利说明:

Method for fabricating contacts of semiconductor device
[10] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device, and more particularly, to a method for reducing contact resistance of a capacitor upper electrode through interlayer contact etching.
[11] In DRAM manufacturing of 0.13 mu m or less, a hole type is preferred as a method of forming a capacitor. The prior art for connecting the upper electrode and the lower electrode on the hole-type capacitor will be briefly described with reference to FIGS. 1 to 7 as follows. First, as shown in FIG. 1, an oxide film 8 is formed on a substrate 1 on which a predetermined substructure (gate, bit line, plug contact, etc.) is formed, and the plug contact 6 formed in the DRAM cell region is exposed. After the oxide film 8 is selectively removed to form a contact hole, a capacitor lower electrode 10 is formed in the contact hole so as to be connected to the substrate through the plug contact 6.
[12] Subsequently, as shown in FIG. 2, an upper electrode 12 is formed on the lower electrode via a dielectric film (not shown), and then an oxide film 14 is formed over the entire surface thereof.
[13] Next, as shown in FIG. 3, the oxide layer 14 is selectively etched to connect the upper electrode contact 16 to the metal wiring to be formed later, and the active contact 18 to connect the substrate and the metal wiring. Form simultaneously. At this time, there is a height difference of about 2 μm between the two contacts 16 and 18. Next, as shown in FIG. 4, the first layer metal wiring 20 is formed to be connected to the contacts 16 and 18.
[14] Subsequently, as shown in FIG. 5, the interlayer metallization insulating layer 22 is formed on the entire surface of the substrate, and then the interlayer metallization insulating layer 22 is selectively etched as shown in FIG. A via contact 24 for connecting the second layer metal wiring to be formed later is formed. Next, as shown in FIG. 7, the second layer metal wiring 26 is formed to be connected to the first layer metal wiring through the via contact 24.
[15] As described above, the lower electrode 10 is connected to the first layer metal wiring 20 through a metal contact (not shown) and is connected to the second layer metal wiring 26 through the via contact 26. In general, the contacts connected to the capacitor upper electrode and the lower electrode are etched simultaneously. Therefore, the upper electrode is also connected to the uppermost metal wiring along the same path. The problem is that when dry etching the contact connected to the upper electrode and the contact connected to the lower electrode at the same time, a through hole is formed in the upper electrode due to the high step (difference in height) between the upper electrode and the lower electrode, thereby increasing the contact resistance. Is that. Since the upper electrode penetrates, the upper electrode and the tungsten on the contact hole are connected only to the sidewalls, thereby increasing the contact resistance.
[16] In addition, in the case of forming a barrier metal in the contact hole, it is necessary to set the process conditions in which the diffusion barrier film is well deposited on the sidewalls so as to allow electricity to pass through the sidewalls. When the diffusion barrier is deposited by sputtering, the diffusion barrier is not deposited on the sidewalls of the contact holes. Therefore, the diffusion barrier must be deposited by CVD, which increases production costs. In addition, even when the diffusion barrier is deposited by CVD, the contact area between the capacitor upper electrode and the conductive material in the contact hole is small, so that the contact resistance value cannot be increased.
[17] The present invention is to solve the above problems, by moving the contact forming time of the upper electrode of the capacitor to the via contact etching time and carried out simultaneously with the via contact to avoid the effect of the step difference between the upper electrode and the substrate to penetrate the upper electrode It is an object of the present invention to provide a method of manufacturing a capacitor of a semiconductor device capable of preventing low contact resistance.
[1] 1 to 7 are process flowcharts showing a contact manufacturing method of a semiconductor device according to the prior art.
[2] 8 to 12 are process flowcharts showing a method for manufacturing a contact of a semiconductor device according to the present invention.
[3] * Explanation of symbols for main parts of the drawings
[4] 1: semiconductor substrate 6: plug contact
[5] 8 oxide film 10 capacitor lower electrode
[6] 12 capacitor upper electrode 14 oxide film
[7] 16: capacitor contact 18: active contact
[8] 20: first layer metal wiring 22: insulating film between metal wiring
[9] 24: Via contact 26: 2nd layer metal wiring
[18] According to an aspect of the present invention, there is provided a contact forming method of a semiconductor device, the method comprising: forming a capacitor lower electrode on an upper portion of a semiconductor substrate on which a predetermined structure is formed; Forming a capacitor upper electrode on the lower electrode through a dielectric film; Forming an oxide film on the entire surface of the substrate; Selectively etching the oxide film to expose a predetermined portion of the substrate to form an active contact for connecting the substrate and the first layer metal wiring formed later; Forming a first layer metal wiring on a predetermined region of the oxide layer so as to be connected to the active contact; Forming an insulating layer between metal wirings on the entire surface of the substrate as described above; A via contact for connecting the first layer metal wiring and a second layer metal wiring to be formed later by selectively etching the insulating layer between the metal lines and a capacitor contact for connecting the upper electrode of the capacitor with the second metal wiring Simultaneously forming; And forming a second layer metal wiring in a predetermined region of the interlayer insulating film between the metal wiring layer so as to be connected to the via contact and the capacitor contact.
[19] DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
[20] In DRAM fabrication of 0.13 mu m or less, a hole type is the preferred method for forming a capacitor. This is to solve the process problems due to miniaturization and to simplify the process. However, in this case, there is no oxide layer difference between the cell region and the peripheral circuit region of the DRAM, so that a high etching step is naturally formed when forming contact holes between the capacitor upper and lower electrodes. In the case of contact etching for connecting the silicon substrate and the upper metal wiring, the contact etching for connecting the capacitor upper electrode to the metal wiring is also simultaneously performed. However, since the upper electrode is in a relatively high region and the silicon substrate is in a very low position, this causes excessive etching to the upper electrode during oxide contact etching, resulting in the formation of holes in the upper electrode. In order to prevent such a phenomenon, the etching time of the contact reaching the upper electrode of the capacitor is different from that of the conventional art. That is, a contact reaching the upper electrode is formed at the time of forming the via contact (a contact connecting the first layer metal wiring and the second layer metal wiring). In the case of the via contact, the lower material is aluminum, which is a metal wiring, and in this case, it is very easy to secure an etching selectivity with an oxide film of 100: 1 or more. Does not happen. In terms of the step, the step between the capacitor upper electrode and the silicon substrate is usually 2 µm or more, but the step between the via contact and the capacitor upper electrode is 1 µm, which is relatively small. Does not occur.
[21] 8 to 12, a method for forming a contact of a semiconductor device according to the present invention will be described.
[22] First, the capacitor upper electrode 12 is formed through the same process as the process of FIGS. 1 and 2 of the prior art described above, and an oxide film 14 is formed on the entire surface thereof. Then, as shown in FIG. 14 is selectively etched to form an active contact 18 for connecting the substrate 1 and the later formed first layer metallization.
[23] Next, as shown in FIG. 9, a first layer metal wiring 20 is formed in a predetermined region of the oxide film so as to be connected to the active contact 18.
[24] Next, as shown in FIG. 10, an interlayer metallization insulating layer 22 is formed on the entire surface of the substrate, and then as shown in FIG. 11, the interlayer metallization insulating layer 22 is selectively etched to form the first layer metallization. The via contact 24 for connecting the second layer metal wiring to be formed later and later and the capacitor contact 16 for connecting the capacitor upper electrode 12 with the second layer metal wiring are simultaneously formed. In this case, the via contact 24 is formed on the first layer metal wiring 20, and the capacitor contact 16 is formed on the capacitor upper electrode 12.
[25] Next, as shown in FIG. 12, a second layer metal wiring 26 is formed in a predetermined region on the interlayer insulating film 22 to be connected to the via contact 24 and the capacitor contact 16.
[26] Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
[27] According to the present invention, the contact formation time of the upper electrode of the capacitor is moved to the via contact etching time and simultaneously performed with the via contact, thereby avoiding the effect of the step difference between the upper electrode and the substrate, thereby preventing the penetration of the upper electrode, thereby ensuring a low contact resistance. Can be.

权利要求:
Claims (1)
[1" claim-type="Currently amended] Forming a capacitor lower electrode on the semiconductor substrate on which the predetermined structure is formed;
Forming a capacitor upper electrode on the lower electrode through a dielectric film;
Forming an oxide film on the entire surface of the substrate;
Selectively etching the oxide film to expose a predetermined portion of the substrate to form an active contact for connecting the substrate and the first layer metal wiring formed later;
Forming a first layer metal wiring on a predetermined region of the oxide layer so as to be connected to the active contact;
Forming an insulating layer between metal wirings on the entire surface of the substrate as described above;
A via contact for connecting the first layer metal wiring and a second layer metal wiring to be formed later by selectively etching the insulating layer between the metal lines and a capacitor contact for connecting the upper electrode of the capacitor with the second metal wiring Simultaneously forming; And
Forming a second layer metal wiring on a predetermined region of the insulating film between the metal wiring layers so as to be connected to the via contact and the capacitor contact;
A contact forming method of a semiconductor device comprising a.

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同族专利:

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公开号 | 公开日

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KR100679941B1|2007-02-08|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2000-12-30|Application filed by 박종섭, 주식회사 하이닉스반도체

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2000-12-30|Priority to KR1020000086588A

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2002-07-12|Publication of KR20020058481A

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2007-02-08|Application granted

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2007-02-08|Publication of KR100679941B1

优先权:

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申请号 | 申请日 | 专利标题

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KR1020000086588A|KR100679941B1|2000-12-30|2000-12-30|Method for fabricating contacts of semiconductor device|