• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention is to provide an encoder of the analog-to-digital conversion that can correct the encoding error caused by the bubble of the temperature code caused by the problem of the comparator, the present invention comprises a comparator to convert the analog input signal into a digital code An encoder of an analog-to-digital converter for converting, comprising: code checking means for dividing a temperature code input from the comparator into units of a predetermined size and inspecting a bubble region in which codes of '0' and '1' are mixed; Encoding means for performing encoding in response to the output of the code checking means; Switching means for switching the temperature code to a bus of a predetermined bit size in units of a predetermined size in response to an output of the code checking means; Counting means connected to the bus to count a code of '1' on the bus; And adding means for adding an encoding result of the encoding means and an output of the counting means to produce a final output of the encoder.
    公开号:KR20020058423A
    申请号:KR1020000086528
    申请日:2000-12-30
    公开日:2002-07-12
    发明作者:윤광호
    申请人:박종섭；주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Encoder in analog-digital converter with wide range error correction}
    [7] The present invention relates to an analog-to-digital converter, and more particularly, to an encoder inside an analog-to-digital converter having enhanced error correction.
    [8] In general, an analog-digital converter (hereinafter, referred to as ADC) is a circuit for converting an analog input signal into a digital code, and is provided between an analog system and a digital system to serve as an interfacing role. In addition, an encoder provided in the ADC plays a role of converting a temperature code into a binary code in a flash ADC or a multi-step ADC.
    [9] 1A and 1B show a conventional encoder circuit constructed of a ROM type. Specifically, FIG. 1A illustrates a case in which there is no bubble in the comparator output, that is, normal operation. FIG. 1B illustrates an encoder malfunction when a bubble occurs due to a random offset voltage of the comparator. This figure shows a case where an incorrect result is output.
    [10] Referring to FIGS. 1A and 1B, the ROM-type conventional encoder may normally convert a temperature code to a binary code '0111' as shown in FIG. 1A in the case of normal operation without bubbles in the comparator output, but the random offset voltage of the comparator. If bubble is generated due to the error of the encoder as shown in Figure 1b it can be seen that the wrong result is output.
    [11] As a result, in the conventional encoder, encoding errors due to bubbles in the temperature code, which may be caused by the problem of the comparator, are generated without being corrected.
    [12] The present invention has been made to solve the above problems, and an object thereof is to provide an encoder of an analog-to-digital conversion that can correct an encoding error caused by a bubble of a temperature code caused by a problem of a comparator.
    [1] 1A and 1B are conventional encoder circuit diagrams of a ROM type.
    [2] 2 is a 4-bit encoder circuit diagram of an ADC in accordance with an embodiment of the present invention.
    [3] * Description of the main parts of the drawing
    [4] 200: code inspection unit 210: MSB encoding unit
    [5] 220: switching unit 230: counting unit
    [6] 240: addition unit
    [13] The present invention for achieving the above object, in the encoder of the analog-to-digital converter for converting an analog input signal into a digital code having a comparator, the temperature code input from the comparator divided by a unit of a predetermined size '0' Code checking means for checking a bubble zone in which the code of '1' and the code are mixed; Encoding means for performing encoding in response to the output of the code checking means; Switching means for switching the temperature code to a bus of a predetermined bit size in units of a predetermined size in response to an output of the code checking means; Counting means connected to the bus to count a code of '1' on the bus; And adding means for adding an encoding result of the encoding means and an output of the counting means to produce a final output of the encoder.
    [14] In addition, the present invention is a 4-bit encoder of the analog-to-digital converter for converting an analog input signal into a digital code having a comparator, the temperature code input from the comparator divided by 4 bits unit '0' and '1' Code inspection means for inspecting a bubble zone in which the code of the mixture is mixed; Encoding means for performing encoding in response to the output of the code checking means; Switching means for switching the temperature code to a 4-bit bus in units of 4 bits in response to the output of the code checking means; Counting means connected to the bus to count a code of '1' on the bus; And adding means for adding an encoding result of the encoding means and an output of the counting means to produce a final output of the encoder.
    [15] DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
    [16] FIG. 2 is a circuit diagram of a 4-bit encoder inside an ADC according to an embodiment of the present invention. The least significant bit (hereinafter referred to as LSB) and the most significant bit (hereinafter referred to as MSB) are shown in FIG. Each is configured to handle via a different path.
    [17] As shown in the drawing, the 4-bit encoder of the present invention divides an input temperature code into units of a predetermined size (4 bits in the drawing) to check whether a code of '0' and '1' is mixed ( 200), the MSB encoder 210 which performs encoding on the MSB according to the output result of the code checker 200, and switches the temperature code to the LSB bus in units of a predetermined size in response to the output result of the code checker 200. The switching unit 220, the counting unit 230 connected to the LSB bus and counting the code of '1' loaded on the bus, and the result of the MSB encoder 210 and the output of the counting unit 230 are added to the encoder. Is made up of an adder 240 which exports the final output.
    [18] Specifically, the code checker 200 includes four OR gates 201 to 204 for receiving a four-bit temperature code, and have one input terminal connected to a ground power source, and a type force terminal connected to an output terminal of the OR gate 201. Logical gate 205, an inverted input of the OR gate 201 to one input terminal, and an AND gate 206 to receive the output of the OR gate 202 as a type force stage, and an OR gate 202 to one input terminal The OR gate 207 receiving the output of the OR and receiving the output of the OR gate 203 to the type force stage, and the OR of the OR gate 203 to the type force stage and inverting the output of the OR gate 203 to the one input stage. It consists of an AND gate 208 that receives an output.
    [19] In addition, the switching unit 220 respectively switches the 4-bit temperature codes to the 4-bit LSB buses in response to the output signals sw4 to sw1 output from the AND gates 205 to 208 of the code inspecting unit 200, respectively. It consists of four switching blocks 221 to 224.
    [20] Next, a 4-bit encoding operation performed by the encoder configured as described above with reference to FIG. 2 will be described below.
    [21] As shown in the figure, when a temperature code such as '0000 0101 1111 1111' is input to the encoder from the comparator, three OR gates 202-204 of the OR gates 201 to 204 of the code checker 200 are set to '1'. 'And the rest of the OR gate 201 outputs' 0'. Subsequently, only one AND gate 206 of the AND gates 205 to 208 outputs '1' by the output of the OR gates 201 to 204, and in response, the MSB encoding unit 210 encodes it. The operation exports the code of '1000'.
    [22] On the other hand, only the switching block 222 of each of the switching blocks 221 to 224 in the switching unit 220 is turned on by the output signals sw4 to sw1 of the AND gates 205 to 208 so that the temperature code '0101' is turned on. It will switch to the LSB bus. Next, the counting unit 230 counts the number of '1's among the temperature codes' 0101' on the LSB bus and outputs a binary code of '10' to the adder 240. Finally, the adder 240 adds the encoding result code '1000' of the MSB encoder 210 and '10' from the counting unit 230 to output '1010' to the final output of the encoder.
    [23] For reference, for convenience of description, an encoder of 4 bits is used as an embodiment of the present invention. The encoder of the present invention is not limited to 4 bits and can be extended regardless of the number of bits.
    [24] Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
    [25] According to the present invention made as described above, the MSB code is obtained by searching the area with bubbles in the temperature code, and the MSB and LSB are added after obtaining the LSB by connecting the bubble area to logic counting the number of '1's. By obtaining the final encoding result, it is possible to compensate for encoding errors due to bubbles in the temperature code that may be a problem in the comparator.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] In the encoder of the analog-to-digital conversion device having a comparator to convert the analog input signal into a digital code,
    Code inspection means for dividing a temperature code input from the comparator into units having a predetermined size and inspecting a bubble region in which codes of '0' and '1' are mixed;
    Encoding means for performing encoding in response to the output of the code checking means;
    Switching means for switching the temperature code to a bus of a predetermined bit size in units of a predetermined size in response to an output of the code checking means;
    Counting means connected to the bus to count a code of '1' on the bus; And
    Addition means for adding an encoding result of the encoding means and an output of the counting means to produce a final output of the encoder
    Encoder of the analog-to-digital conversion device comprising a.
    [2" claim-type="Currently amended] The method of claim 1, wherein the code checking means,
    A plurality of logical sum means for receiving each of the temperature codes by the predetermined size and performing logical OR; And
    A plurality of logical multiplication means for receiving and outputting the output signal output from each of the plurality of logical sum means to two input terminals
    The encoder of the analog-to-digital converter characterized in that comprises a.
    [3" claim-type="Currently amended] The method of claim 2, wherein the switching means,
    A plurality of switching circuits for respectively switching the temperature code of the predetermined size to the bus in response to the output signal output from the logical product means of the code check means
    The encoder of the analog-to-digital converter characterized in that comprises a.
    [4" claim-type="Currently amended] In the 4-bit encoder of the analog-to-digital conversion device having a comparator to convert the analog input signal into a digital code,
    Code inspection means for dividing a temperature code input from the comparator into units of 4 bits and inspecting a bubble region where codes of '0' and '1' are mixed;
    Encoding means for performing encoding in response to the output of the code checking means;
    Switching means for switching the temperature code to a 4-bit bus in units of 4 bits in response to the output of the code checking means;
    Counting means connected to the bus to count a code of '1' on the bus; And
    Addition means for adding an encoding result of the encoding means and an output of the counting means to produce a final output of the encoder
    4-bit encoder of the analog-to-digital conversion device comprising a.
    [5" claim-type="Currently amended] The method of claim 4, wherein the code checking means,
    First to fourth logical sum means for ORing the temperature codes inputted by dividing into four bit units, respectively; And
    First AND product connected to one input terminal to a ground power source and a type force terminal connected to an output terminal of the first AND logic means;
    Second logical AND means for receiving an inverted input of the output of the first AND, and receiving and outputting the output of the second OR in a type force stage;
    Third logical AND means for receiving an inverted input of the output of the second AND, and receiving and outputting the output of the third OR in a type force stage; And
    Fourth logical AND means for receiving the output of the third logical sum means to the one input terminal inverted and receiving the output of the fourth logical sum means to the type force stage
    4-bit encoder of the analog-to-digital converter, characterized in that comprises a.
    [6" claim-type="Currently amended] The method of claim 5, wherein the switching means,
    First to fourth switching circuit sections for respectively switching the 4-bit temperature codes to the bus in response to output signals output from the first to fourth logical product means;
    4-bit encoder of the analog-to-digital converter, characterized in that comprises a.
    类似技术:
    公开号 | 公开日 | 专利标题
    US8390501B2|2013-03-05|Successive approximation register ADC with a window predictive function
    US7439898B1|2008-10-21|Parallel digital processing for reducing delay in SAR ADC logic
    EP0221238B1|1992-09-09|Error tolerant thermometer-to binary encoder
    US7038609B1|2006-05-02|Successive approximation analog-to-digital converter with pre-loaded SAR registers
    US5043732A|1991-08-27|Analog-to-digital converter employing a pipeline multi-stage architecture
    US5459465A|1995-10-17|Sub-ranging analog-to-digital converter
    US6784814B1|2004-08-31|Correction for pipelined analog to digital | converter
    US5675340A|1997-10-07|Charge-redistribution analog-to-digital converter with reduced comparator-hysteresis effects
    EP0259566B1|1994-06-01|Networks used in A/D and D/A converters with correction for differential errors
    JP3281621B2|2002-05-13|High precision DA conversion circuit
    US6897794B2|2005-05-24|All-analog calibration of sting-DAC linearity: application to high voltage processes
    USRE42878E1|2011-11-01|Analog-to-digital converting system
    EP1393447B1|2010-07-21|Capacitive folding circuit for use in a folding/interpolating analog-to-digital converter
    KR20170069140A|2017-06-20|Redundancy scheme for flash assisted successive approximation register| analog-to-digital converter|
    KR970005828B1|1997-04-21|Multiple analog/digital converter for pipeline structure
    US8624764B2|2014-01-07|Test circuits and methods for redundant electronic systems
    JP4836670B2|2011-12-14|Pipeline type A / D converter
    US6778122B2|2004-08-17|Resistor string digital to analog converter with differential outputs and reduced switch count
    US7986253B2|2011-07-26|Method and apparatus for digital error correction for binary successive approximation ADC
    Hong et al.2013|An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement
    CN101098144B|2011-04-06|Coding circuit and a/d convertor
    US4635036A|1987-01-06|Analog-to-digital converter
    WO2011133193A1|2011-10-27|Successive approximation register analog-to-digital converter with integral non-linearity correction
    CN103227642A|2013-07-31|Successive approximation register analog to digital converter
    US6608580B2|2003-08-19|Differential analog-to-digital converter
    同族专利:
    公开号 | 公开日
    KR100399900B1|2003-09-29|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-12-30|Application filed by 박종섭, 주식회사 하이닉스반도체
    2000-12-30|Priority to KR10-2000-0086528A
    2002-07-12|Publication of KR20020058423A
    2003-09-29|Application granted
    2003-09-29|Publication of KR100399900B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-2000-0086528A|KR100399900B1|2000-12-30|2000-12-30|Encoder in analog-digital converter with wide range error correction|
    [返回顶部]