Method for fabricating fine conducting lines of semiconductor memory device

专利摘要:
The present invention provides a method for forming a fine wiring of a semiconductor memory device, comprising: forming a thermal oxide film on a silicon substrate; Forming a nitride film on the thermal oxide film; Patterning the nitride film in a predetermined pattern such that a predetermined portion of the substrate is exposed; Forming a CVD oxide film spacer on a side surface of the nitride film pattern; Implanting ion into the exposed substrate to form a buried bit line; And removing the oxide film and the nitride film.
公开号:KR20020052739A
申请号:KR1020000082176
申请日:2000-12-26
公开日:2002-07-04
发明作者:최성곤
申请人:박종섭；주식회사 하이닉스반도체；
IPC主号:

专利说明:

Method for fabricating fine conducting lines of semiconductor memory device
[8] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine wiring of a semiconductor memory device, and more particularly to a method of forming a wiring of a memory cell transistor capable of minimizing the chip size of a semiconductor memory.
[9] In manufacturing a memory cell transistor according to the prior art, since the wiring size used for the bit line and the ground line is large, the larger the memory density, the larger the chip size.
[10] In addition, since the limits of the width and spacing of the wiring depend on the resolution of the stepper, a high level stepper must be used to manufacture the fine line width.
[11] SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a method for forming a fine wiring of a semiconductor memory device, which can reduce the gap between wirings using CVD oxide sidewalls and minimize the chip size by using a silicon junction as the wiring. There is a purpose.
[1] 1 to 5 are process flowcharts showing a bit line forming method of a semiconductor memory device according to the present invention;
[2] * Explanation of symbols for main parts of the drawings
[3] 1 silicon substrate 2 thermal oxide film
[4] 3: nitride film 4: photoresist pattern
[5] 5: CVD oxide film spacer 8: bit line
[6] 9 oxide film 10 gate oxide film
[7] 11: polysilicon for gate formation
[12] According to an aspect of the present invention, there is provided a method for forming a fine wiring of a semiconductor memory device, comprising: forming a thermal oxide film on a silicon substrate; Forming a nitride film on the thermal oxide film; Patterning the nitride film in a predetermined pattern such that a predetermined portion of the substrate is exposed; Forming a CVD oxide film spacer on a side surface of the nitride film pattern; Performing ion implantation on the exposed substrate to form a buried bit line; And removing the oxide film and the nitride film.
[13] DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
[14] 1 to 5 illustrate a method for forming a bit line and a ground line of a memory cell transistor of a semiconductor memory device according to an embodiment of the present invention in cross-sectional views according to a process sequence.
[15] First, referring to FIG. 1, a thermal oxide film 2 is formed on the silicon substrate 1 with a thickness of about 130 microseconds, and a nitride film 3 is formed thereon at about 1000 microseconds, and then a bit line pattern is formed thereon. Masking is performed to form a predetermined photoresist pattern 4.
[16] Next, as shown in FIG. 2, the nitride film 3 is etched using the photoresist pattern as a mask to form a nitride film pattern exposing a substrate portion where a bit line is to be formed, and then HLD as a CVD oxide film on the side of the nitride film pattern. A spacer 5 made of an oxide film is formed. Subsequently, ion implantation 6 is performed to form bit lines and ground lines in the substrate, and 75As + ions are implanted at an injection amount of 2.0E15 at an acceleration energy of 30KeV, and the bit lines and ground embedded in the substrate as shown in FIG. Line 8 is formed. Subsequently, after removing the HLD oxide spacer, the buried bit line is annealed and oxidized.
[17] Subsequently, as shown in FIG. 4, the oxide film and the nitride film are removed by a wet method, and then, as shown in FIG. 5, a gate oxide film 10 is formed on the substrate on which the buried bit line 8 and the ground line are formed, and a gate is formed thereon. Polysilicon 11 is deposited.
[18] In the above process, when the width / spacing of the nitride film pattern is processed to 0.35 µm / 0.30 µm, and the spacer 5 on the sidewall is formed to have a width of 0.12 µm, the width / spacing of the bit line formed accordingly is 0.23 µm. Since it becomes /0.42㎛, it is possible to form a bit line having a fine line width without raising the resolution of the exposure equipment to a high level.
[19] In addition, the interval between the bit lines corresponds to the channel length of the cell transistor. In this case, if the thickness of the oxide spacer is adjusted, the interval between the bit lines is adjusted, and thus the channel length of the cell transistor can be adjusted. Therefore, the thickness of the oxide spacer can be used to independently maintain the cell transistor channel characteristics with respect to the gap between the bit lines.
[20] Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
[21] According to the present invention, it is possible to form a bit line having a fine line width without increasing the resolution of the exposure apparatus, thereby reducing the chip size, thereby securing price competitiveness and process competitiveness. In addition, the thickness of the oxide spacer may be used to independently maintain the cell transistor channel characteristics with respect to the interval between the bit lines.

权利要求:
Claims (2)
[1" claim-type="Currently amended] In the method of forming fine wirings of a semiconductor memory device,
Forming a thermal oxide film on the silicon substrate;
Forming a nitride film on the thermal oxide film;
Patterning the nitride film in a predetermined pattern such that a predetermined portion of the substrate is exposed;
Forming a CVD oxide film spacer on a side surface of the nitride film pattern;
Implanting ion into the exposed substrate to form a buried bit line; And
Removing the oxide film and the nitride film
Forming a fine wiring of the semiconductor memory device comprising a.
[2" claim-type="Currently amended] The method of claim 1,
And forming a line width of the bit line by a thickness of a CVD oxide spacer formed on sidewalls of the nitride film pattern.

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同族专利:

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公开号 | 公开日

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KR100486755B1|2005-05-03|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2000-12-26|Application filed by 박종섭, 주식회사 하이닉스반도체

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2000-12-26|Priority to KR10-2000-0082176A

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2002-07-04|Publication of KR20020052739A

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2005-05-03|Application granted

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2005-05-03|Publication of KR100486755B1

优先权:

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申请号 | 申请日 | 专利标题

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KR10-2000-0082176A|KR100486755B1|2000-12-26|2000-12-26|Method for fabricating fine conducting lines of semiconductor memory device|