• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A test of semiconductor integrated circuits capable of performing a high-accuracy test at high speed with respect to a mixed signal type semiconductor integrated circuit having an A / D converter circuit and a D / A converter circuit. Suggest a device. A test assistant is provided near the test circuit board on which the semiconductor integrated circuit under test is mounted, and the test auxiliary device is configured to convert an analog test signal into an A / D conversion circuit of the semiconductor integrated circuit under test. A data circuit for giving a test signal, a measurement data memory for storing the test output from the semiconductor integrated circuit under test, and an analysis section for analyzing the storage data of the measurement data memory were provided.
    公开号:KR20020040545A
    申请号:KR1020010056086
    申请日:2001-09-12
    公开日:2002-05-30
    发明作者:모리히사야；야마다신지；후나쿠라테루히코
    申请人:다니구찌 이찌로오, 기타오카 다카시；미쓰비시덴키 가부시키가이샤；요시토미 마사오；료덴 세미컨덕터 시스템 엔지니어링 (주)；
    IPC主号:
    专利说明:

    TEST FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUITS}
    [18] The present invention relates to a test apparatus for a semiconductor integrated circuit and a test method for a semiconductor integrated circuit, and more particularly, to an A / D conversion circuit for converting an analog signal into a digital signal, and a D / A conversion circuit for converting a digital signal into an analog signal. It relates to a test apparatus and a test method of a semiconductor integrated circuit including.
    [19] The test apparatus for this semiconductor integrated circuit is called a tester. Recently, high performance and high precision in a system LSI composed of a single chip semiconductor integrated circuit (one chip LSI) composed of a functionally systemized multiple circuit module or a hybrid integrated circuit (chip set LSI) configured by combining each chip of a plurality of circuits. Mixing (mixed signalization) combining the digital circuit and the analog circuit of FIG. Is rapidly progressing, and the test apparatus for these semiconductor integrated circuits is also coped with, and from the test apparatus manufacturer Testers corresponding to mixed signaling semiconductor integrated circuits are provided.
    [20] However, testers corresponding to this mixed-signaling semiconductor integrated circuit tend to be expensive due to their high performance specifications, and in such a situation, they are used in existing low-speed, low-precision, for example, logic LSI and the like. There is also a move to avoid the high price of testers by reusing old testers.
    [21] The big problem in such a test apparatus is the test of the D / A conversion circuit which converts a digital signal into an analog signal, and the A / D conversion circuit which converts an analog signal into a digital signal, and these conversions are made according to the high precision of these. The problem is how to implement a test apparatus for a semiconductor integrated circuit including a circuit at low cost.
    [22] In a test environment of a general tester, there are a plurality of connection jigs between a tester such as a DUT circuit board (DUT board), a cable, and the DUT in a measurement path from a measuring device inside the tester to a semiconductor integrated circuit under test (called a DUT). Since the measurement path is also long, it may cause noise, deterioration of measurement accuracy, and it may be difficult to simultaneously test a plurality of DUTs. In addition, as a low speed tester, the test at the actual use speed is impossible due to the limitation of the speed, and there is a concern that the test time in the mass production test is increased.
    [23] Japanese Patent Application Laid-Open No. 1-316024 provides a storage element for storing conversion data at an address designated by input data to a D / A conversion section of a test circuit, and converts the analog signal obtained by D / A conversion to A / D. After inputting to the converter, this output is stored in the storage device sequentially.When the conversion is completed for all input data, the conversion data stored in the storage device is sequentially input to the tester, and the input data and the conversion data are sequentially compared with the tester. Judging is proposed.
    [24] However, the input data to the D / A converter, the address for the memory element storing the converted data, and the control signal must be supplied from the tester, and the memory data of the memory element must be supplied to the tester, There is a fear that the measurement accuracy is lowered by the noise in the long measuring path. In addition, simultaneous measurement of a plurality of DUTs from the occupation of the number of tester pin electronics is difficult. Moreover, since the communication of sending the converted data to the tester takes time, the determination of the test result is performed after the completion of the previous test, which makes it difficult to shorten the test time.
    [25] The present invention has been made to improve such a problem, and to propose a test apparatus and a test method for a semiconductor integrated circuit, which make it possible to realize high-speed and high-precision measurement at a lower cost.
    [26] Further, the present invention proposes a test apparatus and test method for a semiconductor integrated circuit which realizes high-speed and high-precision measurement, and can simultaneously test a plurality of semiconductor integrated circuits.
    [1] 1 shows a test apparatus for a semiconductor integrated circuit and a test method using the same according to the present invention, in which FIG. 1A is a plan view of a DUT portion, FIG. 1B is a side view thereof, and FIG. 1C is a configuration diagram of a tester.
    [2] 2 is a block diagram showing the circuit configuration of the first embodiment;
    [3] 3 is a side view of a DUT portion of Embodiment 2 of a test apparatus for a semiconductor integrated circuit according to the present invention;
    [4] 4A shows a third embodiment of a test apparatus and a test method using the same according to the present invention, FIG. 4A is a plan view of a BOST board, FIG. 4B is a plan view of a BOST IF board, and FIG. 4C is a plan view of a DUT board. 4d is a side view of them,
    [5] FIG. 5 shows a DUT portion of Embodiment 4 of a test apparatus for a semiconductor integrated circuit and a test method using the same according to the present invention, FIG. 5A is a side view thereof, and FIG. 5B is a plan view thereof;
    [6] Fig. 6 is a block diagram showing the circuit arrangement of Embodiment 5 of a test apparatus for a semiconductor integrated circuit and a test method using the same according to the present invention;
    [7] Explanation of symbols on the main parts of the drawings
    [8] 10, 10A: Test Circuit Board (DUT Board)
    [9] 11, 11A: semiconductor integrated circuit under test (DUT)
    [10] 20: Test Aid (BOST Device)
    [11] 21, 21A: Test Auxiliary Board (BOST Board)
    [12] 40: tester (tester)
    [13] 51: A / D conversion circuit of semiconductor integrated circuit under test
    [14] 52: D / A conversion circuit of semiconductor integrated circuit under test
    [15] 61: test D / A conversion circuit 62: test A / D conversion circuit
    [16] 63: data circuit 66: measurement data memory
    [17] 69: DSP analysis unit
    [27] The test apparatus for a semiconductor integrated circuit according to the present invention exchanges signals with a semiconductor integrated circuit under test including an A / D conversion circuit for converting an analog signal into a digital signal and a D / A conversion circuit for converting a digital signal into an analog signal. A test circuit board configured to perform a test circuit, a test auxiliary device disposed in the vicinity of the test circuit board and connected thereto and a test device connected to the test auxiliary device, wherein the test auxiliary device generates a digital test signal to perform the test under test. Data circuit to be supplied to the D / A conversion circuit of the semiconductor integrated circuit, and test D / A to convert the digital test signal from the data circuit into an analog test signal and to supply it to the A / D conversion circuit of the semiconductor integrated circuit under test. Digitally test the analog test output from the conversion circuit and the D / A conversion circuit of the semiconductor integrated circuit under test A test A / D conversion circuit for converting the data into a test circuit, a measurement data memory for storing the digital test output from the A / D conversion circuit of the semiconductor integrated circuit under test and the digital test output of the test A / D conversion circuit, and the measurement An analysis section for analyzing the respective digital test outputs stored in the data memory, and supplying the digital test signal and the analog test signal to the semiconductor integrated circuit under test according to the instruction from the tester and stored in the measurement data memory. It is comprised so that the analysis result which analyzed each digital test output by the said analysis part is supplied to the said tester.
    [28] In addition, the test apparatus for a semiconductor integrated circuit according to the present invention is characterized in that the semiconductor integrated circuit comprises a mold type IC which covers the semiconductor integrated circuit chip with a mold resin and draws out a plurality of terminals from the mold resin. It has a socket for mounting a molded IC.
    [29] In the test apparatus for a semiconductor integrated circuit according to the present invention, the semiconductor integrated circuit is included in a semiconductor wafer, and a plurality of probes contacting the semiconductor integrated circuit are set in the test circuit board.
    [30] In addition, a test apparatus for a semiconductor integrated circuit according to the present invention has the test auxiliary apparatus having a test auxiliary substrate having the test D / A conversion circuit, the test A / D conversion circuit, the measurement data memory and the analysis circuit. will be.
    [31] Further, a test apparatus for a semiconductor integrated circuit according to the present invention is given such that the test auxiliary substrate is inserted into a socket on the test circuit board.
    [32] In the test apparatus for a semiconductor integrated circuit according to the present invention, the test auxiliary substrate is mounted on the test circuit board.
    [33] In addition, in the test apparatus of a semiconductor integrated circuit according to the present invention, the test assistant is directly assembled on the test circuit board.
    [34] Further, the test apparatus of the semiconductor integrated circuit according to the present invention outputs a progress signal whenever the test A / D conversion circuit and the A / D conversion circuit of the semiconductor integrated circuit under test output a digital test output. On the basis of this, the digital test signal from the data circuit proceeds and the address of the measurement data memory proceeds.
    [35] In addition, the test apparatus of the semiconductor integrated circuit according to the present invention, the tester outputs a progress signal each time the A / D conversion circuit of the semiconductor integrated circuit under test outputs a digital test output, based on the progress signal The digital test signal from the data circuit proceeds and the address of the measurement data memory proceeds.
    [36] In addition, the test method of the semiconductor integrated circuit according to the present invention is to test the semiconductor integrated circuit under test including an A / D conversion circuit for converting an analog signal into a digital signal and a D / A conversion circuit for converting a digital signal into an analog signal A method for testing a semiconductor integrated circuit, comprising: a data circuit for generating a digital test signal in the vicinity of a test circuit board for exchanging a signal with the semiconductor integrated circuit under test and supplying it to a D / A conversion circuit of the semiconductor integrated circuit under test And a test D / A conversion circuit for converting the digital test signal from the data circuit into an analog test signal and supplying the same to the A / D conversion circuit of the semiconductor integrated circuit under test, and the D / A of the semiconductor integrated circuit under test. A / D conversion circuit for converting the analog test output of the conversion circuit into a digital test output, and A / D of the semiconductor integrated circuit under test A test auxiliary device having a measurement data memory for storing the digital test output from the conversion circuit and the digital test output of the test A / D conversion circuit, and an analysis unit for analyzing the respective digital test outputs stored in the measurement data memory. An analysis in which the digital test signal and the analog test signal are supplied to the semiconductor integrated circuit under test according to an instruction from a tester, and each digital test output stored in the measurement data memory is analyzed by the analysis unit. The result is supplied to the tester and the test semiconductor integrated circuit is tested.
    [37] The test method for a semiconductor integrated circuit according to the present invention is a mold IC in which the semiconductor IC under test covers a semiconductor integrated circuit chip with a mold resin and derives a plurality of terminals from the mold resin. It is mounted and tested in the socket of the circuit board.
    [38] In the test method for a semiconductor integrated circuit according to the present invention, the semiconductor integrated circuit under test is included in a semiconductor wafer, and a plurality of probes set on the test circuit board are in contact with the semiconductor integrated circuit under test to perform a test.
    [39] In addition, the test method of a semiconductor integrated circuit according to the present invention has a test auxiliary device having the test auxiliary device mounted with the test D / A conversion circuit, the test A / D conversion circuit, the measurement data memory and the analysis circuit. The test auxiliary substrate is placed in the vicinity of the test substrate to perform the test.
    [40] In the test method of a semiconductor integrated circuit according to the present invention, the test auxiliary substrate is inserted into a socket on the test circuit board to perform a test.
    [41] In the test method of a semiconductor integrated circuit according to the present invention, the test auxiliary substrate is mounted on the test circuit board to perform a test.
    [42] Further, in the test method of a semiconductor integrated circuit according to the present invention, the test assistant is directly assembled on the test circuit board and tested.
    [43] Further, the test method of the semiconductor integrated circuit according to the present invention outputs a progress signal whenever the test A / D conversion circuit and the A / D conversion circuit of the semiconductor integrated circuit under test output a digital test output. On the basis of this, the digital test signal from the data circuit proceeds and the address of the measurement data memory proceeds to perform the test.
    [44] In addition, the test method of the semiconductor integrated circuit according to the present invention, the tester outputs a progress signal each time the A / D conversion circuit of the semiconductor integrated circuit under test outputs a digital test output, based on the progress signal The digital test signal from the data circuit proceeds and the address of the measurement data memory proceeds to perform the test.
    [45] Example 1
    [46] BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of Example 1 of the test apparatus of the semiconductor integrated circuit which concerns on this invention, and the test method using the same. FIG. 1A is a plan view of a test circuit board (DUT board) part, FIG. 1B is a side view thereof, and FIG. 1C is a configuration diagram of a tester (tester) part.
    [47] The test apparatus of the first embodiment is provided with a test circuit board (DUT board) 10, a test auxiliary apparatus (BOST apparatus) 20, and a tester (tester 40).
    [48] The test circuit board 10 is a semiconductor IC under test (DUT) 11 in the first embodiment, which is a mold IC. Molded ICs cover a semiconductor integrated circuit (IC) chip with a mold resin and pull out a plurality of terminals from the mold resin. The IC chip of the DUT 11 is, for example, a mixed signal type system LSI of one chip, and has a D / A converter for converting a digital signal into an analog signal and an A / D converter for converting an analog signal into a digital signal in one chip. It is to include. The DUT 11 can also use a mixed signal type hybrid integrated circuit (hybrid IC) in which a plurality of chips are integrated on a common circuit board.
    [49] The test circuit board 10 includes a DUT socket 12 into which a terminal of the semiconductor integrated circuit (DUT) 11 to be inserted is inserted, and a plurality of connection terminals 13 and a relay capacitor group for a test ( 14) is placed.
    [50] The test head 15 is disposed under the test circuit board 10. The test head 15 includes a plurality of connection pins 16 connected to the test circuit board 10, and exchanges signals required for a test with the DUT 11 through the connection pins 16.
    [51] The test assistant 20 (BOST device) 20 is arranged near the test circuit board 10. In the first embodiment, the test assistant 20 is configured on a test assistant board (BOST board) 21, which is mounted on the DUT board 10. Therefore, the socket 17 is fixed on the DUT board 10, and the BOST board 21 is provided with the connector 22 inserted into this socket 17 on the lower surface, and this connector 22 is a socket. Inserted into (17) and supported on the DUT board 10, the signal is exchanged with the test head 15 through this socket 17.
    [52] The BOST board 21 is an abbreviation for BUILT-OFF-SELF-TEST, which does not depend on the tester 40 and assists the test circuit carrying a self test (BIST: BUILT-IN-SELF-TEST) inside the DUT. It is a substrate of an external DUT test apparatus, and has an AD / DA measuring unit 23, a control unit 24, a DSP analyzing unit 25, a memory unit 26, and a power supply unit 27.
    [53] The tester 40 includes a test pattern generator (TPG) 41, a power supply unit 42, and a pin electronics unit 43. The tester 40 supplies the power supply voltage V d to the BOST board 21 to supply the BOST board 21. The BOST control signal 44 is exchanged with (). The control signal 44 includes not only the command signals from the tester 40 to the BOST board 21 and the DUT board 10 but also the test analysis result signal from the BOST board 21 to the tester 40. The control signal 44 including the test analysis No., code, etc. input to the BOST board 21 from the tester 40 is based on the test signal conditions described in the test program, and the test pattern embedded in the tester 40. The BOST board 21 and the DUT board through the pin electronics section 43 of the tester 40 having a plurality of signal input / output pins generated by the generator 41 as a test pattern signal like the test of the other DUT 11. (Supplied to 10. On the other hand, the test analysis result (Pass / Fail information) output from the BOST board 21 is sent to the pin electronics unit 43 of the tester 40, the pin electronics unit 43 of the The determination unit accepts only the result based on the comparison determination with the test pattern signal.
    [54] Fig. 2 is a block diagram showing the configuration of the electric circuit in the first embodiment. The DUT 11 includes an A / D conversion circuit 51 for converting an analog signal into a digital signal, and a D / A conversion circuit 52 for converting a digital signal into an analog signal.
    [55] The BOST board 21 includes a test D / A converter circuit 61 for supplying an analog test signal to the A / D converter circuit 51 of the DUT 11, and a D / A converter circuit of the DUT 11 ( A test A / D conversion circuit 62 for converting the analog test output from the digital test output 52 into a digital test output, further comprising a DAC input data circuit (DAC counter) 63, a data recording control circuit 64, and measurement data. The memory address counter 65, the measurement data memory 66, the reference clock circuit 67, the clock generation circuit 68, and the DSP analyzer 69 are provided. The DSP analyzer 69 has a DSP program ROM 70.
    [56] The test D / A conversion circuit 61, the test A / D conversion circuit 62, the DAC input data circuit 63, the data write control circuit 64, and the measurement data memory address counter 65 are shown in FIG. It is included in the A and A / D measuring units 23, the measurement data memory 66 is included in the memory unit 26, and the DSP analyzing unit 69 is included in the DSP analyzing unit 25.
    [57] The test digital test signal (test data) is stored in the DAC input data circuit 63, and the test data from the DAC input data circuit 63 is stored in the DUT 11 according to an instruction from the tester 40. It is supplied to the / A conversion circuit 52 and the test D / A conversion circuit 61 of the BOST board 21.
    [58] The digital test signal (test data) supplied to the D / A conversion circuit 61 is converted into an analog test signal, supplied to the A / D conversion circuit 51 of the DUT 11, and then A of the DUT 11. The digital test output is converted by the / D conversion circuit 51 and supplied to the measurement data memory 66.
    [59] On the other hand, the digital test signal supplied to the D / A conversion circuit 52 of the DUT 11 directly from the DAC input data circuit 63 is converted into an analog test output by the D / A conversion circuit 52, which is a BOST board. The test A / D conversion circuit 62 of Fig. 21 converts the digital test output into a digital test output and supplies it to the measurement data memory 66.
    [60] The measurement data memory 66 supplies the digital test output supplied from the A / D conversion circuit 51 of these DUTs 11 and the A / D conversion circuit 62 from the D / A conversion circuit 52. The digital test outputs are stored in sequentially determined addresses.
    [61] The A / D conversion circuit 51 of the DUT 11 and the A / D conversion circuit 62 of the BOST board 21 sequentially convert analog signals into digital signals, but each time one digital signal is generated, a BUSY signal is generated. Output each of them. These BUSY signals are supplied together to the data write control circuit 64 on the BOST board 21. The data write control circuit 64 advances the digital test data of the DAC input data circuit 63 sequentially to the next digital test data for each data unit based on the supplied BUSY signal, and with respect to the measurement data memory address counter 65 It serves to advance the address of the measurement data memory 66 sequentially.
    [62] As described above, the digital test data code converted into the DUT 11 is advanced in the DAC input data circuit 63 by the BUSY signal, and the digital test output converted in the DUT 11 is stored in the measurement data memory 66. As a result of the addresses to be sequentially processed, the DUT 11 performs the conversion necessary for the sequential test in the A / D conversion circuit 51 and the D / A conversion circuit 52, and the converted measurement data is stored in the measurement data memory. It is memorized sequentially at 66. After that, the conversion test is performed until the final code set by the DSP analysis section 69 of the BOST board 21 is reached, and all the results are stored in the measurement data memory 66.
    [63] After completion of the conversion test by the A / D conversion circuit 51 and the D / A conversion circuit 52 of the DUT 11, the DSP analysis section 69 on the BOST board 21 is executed by the DSP program ROM 70. The data stored in the measurement data memory 66 is read out sequentially and the conversion characteristics are analyzed using the program stored in the program. This analysis includes calculation of A / D conversion characteristic parameter, D / A conversion characteristic parameter, differential linearity, integral nonlinearity error, etc., and the analysis result (Pass / Fail information) is obtained from the BOST board 21. 40, the test result processing is performed by the tester 40.
    [64] In Example 1, the BOST board 21 is arrange | positioned near the DUT board 10, and the conversion test of the A / D conversion circuit 51 and the D / A conversion circuit 52 of the DUT 11 is performed. Since it is equipped with a function, this conversion test can be executed on the BOST board 21. As a result, the analog measuring system line between the DUT board 10 and the BOST board 21 can be shortened, the generation of measurement errors due to noise can be suppressed sufficiently, and a high-precision test is realized, and the DUT board ( 10) and the highway test can be conducted based on the exchange of signals between the BOST boards 21 in the vicinity thereof. The analog measuring system line can be eliminated between the BOST board 21 and the tester 40, and the test accuracy is also improved. In addition, since the necessary conversion test is completed on the BOST board 21 and the result is transmitted to the tester 40, the test speed can be improved as compared with the transmission of the conversion data to the tester 40. FIG.
    [65] In Example 1, since the conversion test function of the A / D conversion circuit 51 and the D / A conversion circuit 52 of the DUT 11 is arranged on the BOST board 21, Therefore, it is not necessary to add a large function, and therefore, it is possible to prevent the high cost of the tester 40 and to use a conventional low speed tester. In addition, when manufacturing the tester 40 having a special measurement function, there is a restriction on the expansion of the function by the hardware configuration of the tester, there is a fear that the development cost is equally increased because the original modification of the tester occurs at the same time. According to Example 1, since the test pattern generator and pin electronics, which are equipped as a standard for a general tester, are used, the BOST board can be configured and controlled without being affected by various tester specifications and limitations. It becomes possible.
    [66] Example 2
    [67] Fig. 3 is a side view showing a DUT portion of Embodiment 2 of a test apparatus for a semiconductor integrated circuit and a test method using the same according to the present invention. As Example 2, the BOST board 21 of Example 1 is mounted on the upper surface of the DUT board 10. In this embodiment 2 also, the mold semiconductor integrated circuit is inserted into the socket 12 on the DUT board 10, and the A / D converter 41 and the D / A converter 42 are tested.
    [68] In Fig. 3, the BOST board 21 is loaded on the upper right side of the DUT board 10, and the connection between both boards is performed at this loading portion, and the signal is exchanged with the test head 15. All. In addition, the configuration on the BOST board 20 is the same as in FIG. 1, and the circuit configuration is the same as in FIG. 2.
    [69] Example 3
    [70] Fig. 4 shows the structure of the DUT portion of Example 3 of the test apparatus and the test method using the same of the semiconductor integrated circuit according to the present invention. 4A is a plan view of the BOST board 21A, FIG. 4B is a plan view of the BOST IF board, FIG. 4C is a plan view of the DUT board 10A, and FIG. 4D is a side view thereof. In the third embodiment, a semiconductor integrated circuit in a wafer state is used as the test object (DUT). The DUT board 10A is a probe card, which is circular in shape, and has a plurality of probes 30 for the wafer 11A on the lower surface of its central portion. The BOST IF board 32 is arrange | positioned on this DUT board 10A via the connection structure 31, and the connector 33 is attached to this BOST IF board 32. As shown in FIG. The BOST board 21A constituting the BOST device 20 is also formed in a circular shape, and the AD / DA measuring unit 23, the control unit 24, and the memory unit (the same as in the first embodiment) are formed on the upper surface of the BOST board 21A. 26), the DSP analyzer 25 and the power supply unit 27 are arranged.
    [71] The structure of the electric circuit of Example 3 is the same as that of FIG. 2 of Example 1, and the test similar to Example 1 is performed by bringing the probe 30 into contact with the many terminal of the chip equivalent part of the wafer 11A. A substantial portion of the chip of the wafer 11A is removed sequentially, and a substantial portion of the chip adjacent to each other is sequentially tested.
    [72] Example 4
    [73] FIG. 5 shows a DUT portion of Embodiment 4 of a test apparatus for a semiconductor integrated circuit and a test method using the same according to the present invention, FIG. 5A is a side view, and FIG. 5B is a plan view. In the fourth embodiment, the BOST board 20A is omitted in the third embodiment, so that the BOST IF board 17 and the connector 16 are also omitted, and the AD / DA measuring unit 21 constituting the BOST device 20 is provided. The control unit 22, the memory unit 24, the DSP analysis unit 23, and the power supply unit 25 are all disposed on the upper surface of the DUT board 10A having the probe 30, thereby making necessary connections.
    [74] The circuit configuration of the fourth embodiment is the same as that in Fig. 2 of the first embodiment, and similarly, the A / D conversion circuit 51 and the D / A conversion circuit 52 of the DUT 11A are tested.
    [75] Also in Examples 2, 3, and 4, since the BOST apparatus 20 or the BOST boards 21 and 21A are arranged near the DUT boards 10 and 10A, and the test is performed as in Example 1, Example 1 As described above, the precision of the test can be increased, the speed can be increased, and the cost of the device can be reduced.
    [76] Example 5
    [77] Fig. 6 is a block diagram showing the circuit arrangement of Embodiment 5 of a test apparatus for a semiconductor integrated circuit and a test method using the same according to the present invention. In the fifth embodiment, the A / D conversion circuit 51 of the DUT 11 is a type that does not generate a BUSY signal. Therefore, the trigger signal 74 is supplied from the tester 40 to supply the data circuit 63. Operation of advancing in digital units and advancing the address of the measurement data memory 66. In addition, since the A / D conversion circuit 62 of the BOST board can be configured to generate a BUSY signal, this BUSY signal can be used in combination with the trigger signal 74. The other structure is the same as that of FIG.
    [78] Also in this Embodiment 5, the trigger signal 74 transmitted from the tester 40 to the BOST apparatus 20 is a digital signal, and the analog signal system which is susceptible to the noise between the tester 40 and the BOST apparatus 20 is easy. It is not enough to add, and the precision of the test can be increased and the speed can be increased as in Example 1.
    [79] As described above, the present invention is provided with a data circuit, a test D / A conversion circuit, a test A / D conversion circuit, a measurement data memory, and a DSP analysis unit in a test auxiliary device arranged near the test circuit board, To test the A / D converter and the D / A converter of the semiconductor integrated circuit under test, and to test the mixed signal type semiconductor integrated circuit including the A / D converter and the D / A converter. Can be performed with high accuracy and high speed, and the test apparatus can be reduced in price.
    [80] In addition, by equipping the test circuit board with a socket for mounting the mold IC, the A / D conversion circuit and the D / A conversion circuit of the mold-type semiconductor integrated circuit can be easily tested, and the test equipped with the probe By using a circuit board, the same test can be easily performed in a wafer state.
    [81] In addition, if the test assistant has a test assistant board equipped with a data circuit, a test D / A converter circuit, a test A / D converter circuit, a measurement data memory, and a DSP analyzer, the test assistant is concentrated on the test assistant board. The configuration of the test auxiliary board can be simplified by inserting the test auxiliary board into the socket of the test circuit board. The device can be simplified by loading the test auxiliary board on the test circuit board. Can be mad.
    [82] Also, by directly attaching the test assistant on the test circuit board, the configuration of the device can be further simplified.
    [83] Further, for generating the progress signal in the test A / D conversion circuit and the A / D conversion circuit in the semiconductor integrated circuit under test and generating the progress signal from the tester, the digital test signal is advanced and measured by the progress signal. An effective test can be performed while advancing the address of the data memory.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] A test circuit board configured to exchange signals with a semiconductor integrated circuit under test including an A / D conversion circuit for converting an analog signal into a digital signal and a D / A conversion circuit for converting a digital signal into an analog signal;
    A test aid disposed near and connected to the test circuit board,
    And a tester connected to the test assistant,
    The test aid,
    A data circuit for generating a digital test signal and supplying the digital test signal to a D / A conversion circuit of the semiconductor integrated circuit under test;
    A test D / A conversion circuit for converting the digital test signal from the data circuit into an analog test signal and supplying it to the A / D conversion circuit of the semiconductor integrated circuit under test;
    A test A / D conversion circuit for converting an analog test output of the D / A conversion circuit of the semiconductor integrated circuit under test into a digital test output;
    A measurement data memory for storing the digital test output from the A / D conversion circuit of the semiconductor integrated circuit under test and the digital test output of the test A / D conversion circuit;
    An analysis section for analyzing the respective digital test outputs stored in the measurement data memory;
    According to the instruction from the tester, the digital test signal and the analog test signal are applied to the semiconductor integrated circuit under test, and each analysis result of the digital test output stored in the measurement data memory is analyzed by the analysis unit. And testing apparatus for semiconductor integrated circuits.
    [2" claim-type="Currently amended] According to claim 1,
    And the test auxiliary device includes a test auxiliary substrate on which the test D / A conversion circuit, the test A / D conversion circuit, the measurement data memory, and the analysis circuit are mounted.
    [3" claim-type="Currently amended] In a test method of a semiconductor integrated circuit for testing a semiconductor integrated circuit under test including an A / D conversion circuit for converting an analog signal into a digital signal and a D / A conversion circuit for converting a digital signal into an analog signal,
    A data circuit for generating a digital test signal in the vicinity of a test circuit board for exchanging signals with the semiconductor integrated circuit under test and supplying it to a D / A conversion circuit of the semiconductor integrated circuit under test, and a digital test from the data circuit Digital test of the test D / A conversion circuit for converting the signal into an analog test signal and supplying it to the A / D conversion circuit of the semiconductor integrated circuit under test, and the analog test output of the D / A conversion circuit of the semiconductor integrated circuit under test. A test A / D conversion circuit for converting to an output, a measurement data memory for storing a digital test output from an A / D conversion circuit of the semiconductor integrated circuit under test and a digital test output of the test A / D conversion circuit, and Arranging a test aid having an analysis section for analyzing the respective digital test outputs stored in the measurement data memory,
    According to the instruction from the tester, the digital test signal and the analog test signal are supplied to the semiconductor integrated circuit under test, and each analysis result of the digital test output stored in the measurement data memory is analyzed by the analysis unit. A test method for a semiconductor integrated circuit, characterized by being supplied to a tester to test the semiconductor integrated circuit under test.
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    TW518644B|2003-01-21|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-11-22|Priority to JP2000356724A
    2000-11-22|Priority to JPJP-P-2000-00356724
    2001-09-12|Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤, 요시토미 마사오, 료덴 세미컨덕터 시스템 엔지니어링 (주)
    2002-05-30|Publication of KR20020040545A
    优先权:
    申请号 | 申请日 | 专利标题
    JP2000356724A|JP2002162450A|2000-11-22|2000-11-22|Testing device of semiconductor integrated circuit, and test method of the semiconductor integrated circuit|
    JPJP-P-2000-00356724|2000-11-22|
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