• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method for forming a capacitor of a semiconductor device is provided to form stably a pattern layer by using simultaneously an OBARC(Organic Bottom Anti-Rectifier Coating) layer and a dip out mask. CONSTITUTION: A contact stoper layer(24) and a sacrificial oxide layer(23) are formed on an insulating layer(22) including a contact layer(21). A trench for forming a capacitor is formed by etching selectively the sacrificial oxide layer(23). A conductive layer(25) is formed on a whole surface including the trench. An OBARC layer(27) are formed thereon. A dip out mask(26) is formed thereon. The OBARC layer(27) is etched as much as its thickness in dry isotropic etching or dry anisotropic etching. A target etch method or an etch method using an EOP(End Of Point) are used in the etch process. The OBARC layer(27) and the conductive layer(25) are etched. The sacrificial oxide layer(23) is removed by using a wet chemical.
    公开号:KR20020017096A
    申请号:KR1020000050188
    申请日:2000-08-28
    公开日:2002-03-07
    发明作者:서일석
    申请人:박종섭；주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    METHODO FOR FORMING CAPACITOR OF SEMICONDUCTOR DEVICE
    [8] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device in which a pattern layer can be stably formed by using an organic bottom anti-rectifier coating (OBARC) layer and a deep-out mask simultaneously.
    [9] Hereinafter, a capacitor forming method of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
    [10] 1A to 1E are cross-sectional views of a process for forming a capacitor of a semiconductor device of the prior art.
    [11] First, as shown in FIG. 1A, in order to form an inner cylinder type capacitor, the contact stopper layer 4 and the sacrificial oxide layer 4 may be formed on the insulating layer 2 including the lower ground contact layer 1. 3) and selectively etching the sacrificial oxide layer 3 to expose the lower ground contact layer 1 to form a trench for forming a capacitor.
    [12] Then, the capacitor forming conductive layer 5 is deposited on the entire surface including the trench, and the photosensitive film 6 is deposited.
    [13] Subsequently, as illustrated in FIG. 1B, the photosensitive film 6 is removed by a chemical mechanical polishing (CMP) process to expose the top surface of the sacrificial oxide layer 3.
    [14] In the process of removing the sacrificial oxide layer 3, each conductive layer 5 for capacitor formation is separated in units of cells.
    [15] 1C and 1D, the remaining photoresist film 6 is removed and the sacrificial oxide layer 3 is removed using a wet chemical using a deep out mask 7.
    [16] After the process is performed as shown in FIG. 1E, the deep-out mask 7 is removed to complete the inner cylinder type capacitor electrode.
    [17] In such a capacitor formation process of the prior art, a poor contact etch may occur when the photoresist pattern is defective in some regions, particularly in the wafer edge region.
    [18] This results in a poor pattern profile of the capacitor electrode during dip out using a wet chemical.
    [19] To solve this problem, a dip out mask is used to cover the defective part of the pattern profile. In this case, after wet dip out, the drying process must be performed to remove the solution from the equipment. do.
    [20] In the drying process, a spin dryer is used, and in this case, a shape in which the photoresist film becomes cracked due to the rotational property is generated. When a general IPA dryer is used, a shape in which the photoresist film is melted by the IPA is generated. In order to suppress this, the room temperature (Room Temperature) IPA dryer is used to prevent this shape.
    [21] In forming such a capacitor of a semiconductor device of the prior art, there are the following problems.
    [22] In order to solve the problem of poor contact at the wafer edge part, drying is required when using a deep-out mask, and purchase of new equipment is required when using a room temperature IPA dryer.
    [23] In addition, the adoption of the CMP process is likely to cause scratch problems that are a cause of defect generation.
    [24] In the process of removing the deep-out mask, particles in the wafer edge region are pushed to the center of the wafer to affect the operation characteristics of the device.
    [25] The present invention is to solve the problem of the formation of the capacitor of the semiconductor device of the prior art, a semiconductor that can form a stable pattern layer by using an organic bottom anti-rectifier coating (OBARC) layer and a deep out mask at the same time It is an object to provide a method of forming a capacitor of the device.
    [1] 1A to 1E are cross-sectional views of a process for forming a capacitor of a semiconductor device of the prior art.
    [2] 2A to 2F are cross-sectional views of a process for forming a capacitor of a semiconductor device according to the present invention.
    [3] -Explanation of symbols for the main parts of the drawing-
    [4] 21. Bottom ground contact 22. Insulation layer
    [5] 23. Sacrificial oxide layer 24. Contact stopper layer
    [6] 25. Conductive Layer for Capacitor Formation 26. Deep Out Mask
    [7] 27.OBARC layer
    [26] According to another aspect of the present invention, there is provided a method of forming a capacitor of a semiconductor device, the method including: forming a contact stopper layer and a sacrificial oxide layer on an insulating layer including a lower ground contact layer; Selectively etching the sacrificial oxide layer; depositing a conductive layer for forming a capacitor on the front surface and forming an organic bottom ARC layer; forming a deep out mask and removing the OBARC layer by the thickness; Etching the OBARC layer and the conductive layer for forming a capacitor at a certain thickness simultaneously to separate the conductive layer for forming a capacitor in units of cells; removing the deep-out mask and the OBARC layer and removing the sacrificial oxide layer. It features.
    [27] Hereinafter, a method of forming a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
    [28] 2A to 2F are cross-sectional views of a process for forming a capacitor of a semiconductor device according to the present invention.
    [29] The present invention is a process for forming a capacitor using an organic bottom ARC (OBARC) and a dip out mask (Dip Out Mask) at the same time 0.18㎛ Tech. In order to form a cylindrical inner cylindrical capacitor in the process below.
    [30] In other words, in order to deposit the conductive layer for the capacitor in the contact hole and remove the top conductive layer, the OBARC deposition and etch back processes are adopted to prevent pattern defects in the wafer edge region.
    [31] First, as shown in FIG. 2A, in order to form an inner cylinder type capacitor, the contact stopper layer 24 and the sacrificial oxide layer may be formed on the insulating layer 22 including the lower ground contact layer 21. 23 is formed, and the sacrificial oxide layer 23 is selectively etched to expose the lower ground contact layer 21 to form a trench for forming a capacitor.
    [32] In addition, the conductive layer 25 for forming a capacitor is deposited on the entire surface including the trench, and an organic bottom ARC layer 27 is deposited on the entire surface.
    [33] Subsequently, as shown in FIG. 2B, a deep out mask 26 is formed to prevent a portion where the pattern defect of the capacitor may occur, that is, a wafer edge region.
    [34] As shown in FIG. 2C, the dry anisotropic or isotropic etching of the OBARC layer 27 is performed by the thickness thereof.
    [35] Here, the target etch as much as the thickness of the OBARC layer 27 or the etching using the end of point (EOP) may be used.
    [36] Subsequently, as shown in FIG. 2D, the dry isotropic or anisotropic etching is performed on the OBARC layer 27 and the capacitor forming conductive layer 25 at a 1: 1 etching ratio.
    [37] As shown in FIG. 2E, the deep out mask 26 and the OBARC layer 27 are removed.
    [38] Subsequently, as illustrated in FIG. 2F, the sacrificial oxide layer 23 is removed using a wet chemical.
    [39] In this process, the portion protected by the deep-out mask 26 is blocked by the conductive layer 25 for capacitor formation, so that only the portion to form the capacitor pattern is removed without removing the sacrificial oxide layer 23.
    [40] In this process, the OBARC etchback process is used instead of the CMP process, so that the CMP does not generate scratches, and simultaneously, the OBARC layer and the dip out mask are used to simultaneously etch back while blocking the defective part of the pattern. There is a characteristic.
    [41] Of course, there is no need for a drying process.
    [42] In addition, the selectivity adjustment for etching the OBARC layer 27 and the capacitor forming conductive layer 25 adjusts the selectivity to 1: 1 by appropriately adjusting the RF power and the bias power.
    [43] In addition, the etching gas can satisfy the optimum conditions by adjusting the ratio of fluorine-based gas of CF 4 , CHF 3 and O 2 gas and inert gas such as Ar, N 2 , and ICP (Inner Coupled Plasma) currently used. ), MERIE (Magnetic Enhanced Reactive Ion Etch), RIE (Reactive Ion Etch), and TCP (Transformer Coupled Plasma) types can be used.
    [44] Such a method of forming a capacitor of a semiconductor device according to the present invention has the following effects.
    [45] First, in the process of forming inner cylinder type capacitors using contact etching in 0.18Tech or lower process, the etchback process using OBARC layer instead of CMP process can be used to prevent the defects caused by scratching, thereby stabilizing and simplifying the process.
    [46] Second, since the capacitor conductive layer not etched by the deep-out mask during the etch back process can be used instead of the wet deep-out, the drying process does not need to be carried out, thereby reducing manufacturing costs.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] Forming a contact stopper layer and a sacrificial oxide layer on an insulating layer including a lower ground contact layer;
    Selectively etching the sacrificial oxide layer to expose the lower ground contact layer;
    Depositing a conductive layer for forming a capacitor on the front surface and forming an organic bottom ARC layer;
    Forming a deep out mask and removing the OBARC layer by its thickness;
    Separating the OBARC layer and the capacitor forming conductive layer simultaneously by a predetermined thickness to separate the capacitor forming conductive layer in units of cells;
    Removing the deep out mask and the OBARC layer and removing the sacrificial oxide layer.
    [2" claim-type="Currently amended] The method of claim 1, wherein the OBARC layer is removed by a target anisotropic or anisotropic etching process by a thickness thereof or by an etching process using an end of point (EOP). .
    [3" claim-type="Currently amended] The method of claim 1, wherein the etching of the OBARC layer and the conductive layer for forming the capacitor by a predetermined thickness is performed by a dry isotropic or anisotropic etching process at a 1: 1 etching ratio.
    [4" claim-type="Currently amended] The method of claim 1, wherein the portion that was protected by the deep-out mask during the process of removing the sacrificial oxide layer is blocked by the conductive layer for forming a capacitor so that only the portion where the sacrificial oxide layer is to be formed and the capacitor pattern is not removed. A method of forming a capacitor of a semiconductor device.
    [5" claim-type="Currently amended] The etch gas of the OBARC layer and the capacitor-forming conductive layer is a fluorine-based gas of CF 4 , CHF 3 , O 2 gas and an inert gas such as Ar, N 2, and the like. , Using the equipment of TCP proceeding capacitor formation method of a semiconductor device.
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    同族专利:
    公开号 | 公开日
    KR100653981B1|2006-12-05|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-08-28|Application filed by 박종섭, 주식회사 하이닉스반도체
    2000-08-28|Priority to KR1020000050188A
    2002-03-07|Publication of KR20020017096A
    2006-12-05|Application granted
    2006-12-05|Publication of KR100653981B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000050188A|KR100653981B1|2000-08-28|2000-08-28|Method for forming capacitor of semiconductor device|
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