• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An electronic circuit for a capacitive flash analog-to-digital converter for converting a ratio of first and second analog signals into a digital code representation using an array of parallel capacitive comparator branches is disclosed. Each branch simultaneously calculates one bit of the digital code according to its array index. The first analog signal is applied as a voltage difference between first signal nodes including a first positive signal node and a first negative signal node. The second analog signal is applied as a voltage difference between second signal nodes including a second positive signal node and a second negative signal node.
    公开号:KR20010108035A
    申请号:KR1020017007852
    申请日:1999-12-01
    公开日:2001-12-07
    发明作者:하임파스칼；모르타라알렉산드로；마사페터；하이트거프리드리히
    申请人:클라우스 로우스케；비숍 이노베이션 리미티드；추후보정；체에스에엠 센트레 스위쎄 데 엘렉트로니크 에트 데 미크로 테크니크 에스 아；
    IPC主号:
    专利说明:

    Capacitive Flash Analog-to-Digital Converters {CAPACITIVE FLASH ANALOG TO DIGITAL CONVERTER}
    [2] Capacitors are the most sophisticated devices in most ultra high density integrated circuit (VLSI) processes. This is one of the reasons why most ADCs use the capacitor and charge redistribution principle. The most compact structure in the prior art performs the conversion in a number of steps rather than performing the conversion in parallel to save hardware (eg, US Pat. No. 4,831,381, US Pat. No. 4,517,549, US Pat. No. 4,129,863 and US Pat. 4,922,252). These ADCs are efficient from a hardware point of view, but cannot be used at very high speeds because they require multiple steps for conversion.
    [3] Most flash converters perform conversions in parallel on one clock. Most n-bit structures in the prior art use a resistive ladder with 2 n resistors to generate a series of 2 n reference voltages and 2 n comparators to compare the input voltage with a plurality of reference voltages in parallel. In these structures, the resistance of the switch connecting the resistive ladder to the reference voltage should be considered.
    [4] US Pat. No. 4,742,330 discloses a capacitive flash ADC. The ADC performs 2n bit conversion using 2 n parallel branches in three phases. In the first phase, an offset cancellation occurs. In the second and third phases, n-bit most significant bits (MSBs) and n-bit least significant bits (LSBs) are obtained, respectively. The operation of the second phase is closely related to the operation of the conventional flash ADC structure with the resistive ladder described above. The MSBs determine the coarse range {V i ..V i + 1 } in which the input signal is maintained. In the third phase, the LSBs are divided into 2 n precision voltage levels over the rough voltage range {V i ..Vi + 1} using 2 n parallel branches, each containing a log 2 n binary weighted converter. By dividing, it is determined. Some of these converters are connected to V i and other V i + 1 for interpolation between the two extremes. The 2 n comparators compare the input voltage in parallel with the generated 2 n precision reference voltages.
    [5] A common feature of prior art ADC implementations is that the structure is not symmetrical with respect to two input voltages, the signal voltage being converted and the reference voltage. In general, it is assumed that the reference voltage does not vary with time. The principle that overcomes these limitations is described in the following description.
    [6] It is an object of the present invention to provide an electronic circuit for a capacitive flash ADC that mitigates or overcomes one or more disadvantages of known capacitive flash ADC circuits.
    [7] The circuit structure is symmetrical with respect to the two input voltages, and thus the signal and reference voltages to be converted are interchanged during operation,
    [8] The reference voltage may vary over time and may further have a high frequency component equal to the signal voltage being converted,
    [9] Benefit from computation by the most sophisticated elements of the VLSI process-capacitor,
    [10] Converting analog to digital in one clock cycle, and
    [11] It is desirable that the structure is simple to control.
    [1] TECHNICAL FIELD The present invention relates to analog-to-digital converters (ADCs) for converting analog to digital. Specifically, the present invention relates to precise capacitive weighting, one clock cycle conversion, simple control, interchangeable input and linear. Or electronics for flash ADCs with nonlinear conversion.
    [30] 1 shows an electronic circuit showing the basic principle for capacitive comparison of two analog signals.
    [31] 2 shows a corresponding differential of the electronic circuit shown in FIG.
    [32] 3 illustrates an electronic circuit for a capacitive flash ADC in accordance with the present invention.
    [33] 4 is a detail view of one capacitive comparator branch from FIG.
    [34] Figure 5 illustrates two phases of one clock for analog to digital conversion, performed by an electronic circuit in accordance with the present invention.
    [12] Summary of the Invention
    [13] The present invention is an electronic circuit for a capacitive flash analog-to-digital converter that converts the ratio of first and second analog signals to a digital code representation using an array of parallel capacitive comparator branches, wherein the first analog signal is a first analog signal. Is applied as a voltage difference between first signal nodes comprising a first positive signal node and a first negative signal node, and a second analog signal is between the second signal nodes comprising a second positive signal node and a second negative signal node. Applied as a voltage difference,
    [14] Each branch simultaneously computes one bit of the digital code according to its array index, and each branch
    [15] (i) a comparator having a positive input node, a negative input node, a positive output node and a negative output node,
    [16] (ii) first and second positive capacitors having a positive common plate connected to the positive input node of the comparator,
    [17] (iii) first and second negative capacitors having negative common plates connected to the negative input node of the comparator, and
    [18] (iv) a first and a second feedback switch,
    [19] Wherein the first and second positive capacitors also have first and second positive counter plates, respectively, switchably connected to the first and second signal nodes, respectively, the first and second negative capacitors being respectively It also has first and second negative counter plates switchably connected to the first and second signal nodes, respectively.
    [20] Preferably, the conversion from analog to digital is performed in one clock cycle including the first and second phases.
    [21] Preferably, the digital code is a digital thermometer code.
    [22] Preferably, in the first phase of the clock cycle, the first positive counter plate is connected to the first positive signal node and the second positive counter plate is connected to the second negative signal node, and the first negative counter plate is the first negative signal. The second negative counter plate is connected to the second positive signal node, the first feedback switch connects the negative output node to the positive input node of the comparator and the second feedback switch connects the positive output node of the comparator negative input node. Connect to; In the second phase of the clock cycle, the first positive counter plate is connected to the first negative signal node, the second positive counter plate is connected to the second positive signal node, and the first negative counter plate is connected to the first positive signal node. And the second negative counter plate is connected to the second negative signal node, the first and second feedback switches are opened, thereby outputting one bit of the digital code by the polarity of the voltage difference between the positive and negative output nodes of the comparator do.
    [23] Preferably, the capacitance of each first positive, first negative, second positive and second negative capacitor is different for each branch depending on the array index of that branch.
    [24] Preferably, in any one branch, the capacitance of the first positive capacitor is substantially the same as the capacitance of the first negative capacitor, and the capacitance of the second positive capacitor is substantially the same as the capacitance of the second negative capacitor.
    [25] Preferably, in any one branch, the ratio of the capacitance of the first positive to the second positive capacitor is a linear function of the array index of that branch, thus linearly converting between the ratio of the first and second analog signals and the digital code. To provide.
    [26] Alternatively, in any one branch, the ratio of the capacitance of the first positive to the second positive capacitor is a nonlinear function of the array index of that branch, thus nonlinear conversion between the ratio of the first and second analog signals and the digital code. To provide.
    [27] Preferably the ratio of the capacitances of each capacitor of different branches is linear as a function of the array index.
    [28] Alternatively, the ratio of the capacitances of each capacitor of different branches is nonlinear as a function of the array index.
    [29] Preferably the first analog signal corresponds to a sine function of the phase angle of the periodic signal, and the second analog signal corresponds to a cosine function of the phase angle of the periodic signal, and in any one branch, the first positive and second positive capacitor The ratio of capacitances of is the tangent of the linear function of the array index of the branch, thus providing a linear transformation between the phase angle and the digital code representation of this phase angle.
    [35] Figure 1 illustrates the basic principle of the electronic circuit of the capacitive flash ADC according to the present invention. The analog input signals ΔV x , ΔV r and output signals ΔV out are voltage variations, not corresponding voltages V x , V r, and V out . In a conventional discussion of an ADC, the input signal V x may be a signal voltage that is compared with a predetermined ratio of the reference voltage V r . However, in an embodiment of the invention, the circuit must be symmetrical about two input signals, so there is no fixed reference and in fact V x and V r can be interchanged.
    [36] In the following description, if a plate of a capacitor is shared with a plate of another capacitor, the plate is referred to as a "common plate", and if not shared, it is referred to as a "counter plate". The basic principle of capacitive comparison is that two input voltage variations are applied to the opposite plate as shown in FIG. These variations have opposite signs, so one variation reduces the common plate voltage of the capacitor while the other increases it. The larger the capacitor, the greater the influence of each input.
    [37] Using the charge preservation principle, the output voltage variation applied to the input of the comparator of FIG. 1 can be calculated as follows.
    [38]
    [39] Where ΔV x and ΔV r are the input voltage variations, C x and C r are the respective capacitance values and C 0 is the parasitic capacitance between the common plate and ground. Before the input voltage shift is applied, it is assumed that V out = 0, so after the input voltage shift, the comparator output depends on the sign of the input voltage shift. The comparator output "Bit" becomes 1 when V out increases and -1 when V out decreases. The following comparator output can be obtained from Equation 1.
    [40]
    [41] As a result, the capacitive comparator circuit compares the variation of the input voltage against a predetermined ratio (C x / C r ) of the capacitors.
    [42] FIG. 2 shows a corresponding differential of the electronic circuit shown in FIG. 1. The advantage of the differential arrangement is that positive and negative voltage variations can be generated simply by inverting the polarity of the differential signal.
    [43] Figure 3 shows one embodiment of a capacitive flash ADC according to the invention for converting the ratio of first and second analog signals into digital codes using an array of parallel branches of the capacitive comparator. In this embodiment, the digital code shown is a digital thermometer code. Thus, for example, the 8-bit representation for decimal number "5" is 00011111 and the 8-bit representation for decimal number "6" is 00111111. It should be appreciated that digital codes other than thermometer codes may be applied in accordance with the present invention. The conversion from analog to digital is performed in one clock cycle 33 which includes a first phase 31 and a second phase 32 as shown in FIG. Offset cancellation occurs in the first phase 31 while actual conversion from analog to digital is performed during the second phase 31. 4 shows a detailed view of one capacitive comparator branch of FIG. 3.
    [44] In the first phase, as shown in FIGS. 3 and 4 where all switches are in position " 1 ", switch sets 11 and 12 show that the first analog signal (V x ) has a positive polarity, The second analog signal V r is in the first configuration so that it effectively has a negative polarity. Thus, the first positive counter plate 20a of the first positive capacitor 20 is connected to the first positive signal node 11a of the switch set 11, and the second positive counter plate of the second positive capacitor 20 ( 18a) is connected to the second negative signal node 12b of the switch set 12. The first negative counter plate 21a of the first negative capacitor 21 is connected to the first negative signal node 11b of the switch set 11 and the second negative counter plate 19a of the second negative capacitor 19. Is connected to the second positive signal node 12a of the switch set 12. The first feedback switch 13 connects the negative output node 16 to the positive input node 22 of the comparator 15, and the second feedback switch 14 connects the positive output node 17 of the comparator 15. To negative input node 23. Negative feedback through the closed feedback switches 13 and 14 results in a differential voltage between the positive input node 22 and the negative input node 23, the negative output node 16 and the positive output node 17 of the comparator 15. ) Make all differential voltages between zero become zero.
    [45] In the second phase, as shown in FIGS. 3 and 4, although not shown except that all switches are in position " 2 ", switch sets 11 and 12 may have a first negative analog signal (V x ) in order to be negative. It is in the second configuration such that it has polarity while the second analog signal V r is effectively positive polarity. Thus, the first positive counter plate 20a of the first positive capacitor 20 is connected to the first negative signal node 11b of the switch set 11, and the second positive counter plate of the second positive capacitor 18 ( 18a is connected to the second positive signal node 12a of the switch set 12. The first negative counter plate 21a of the first negative capacitor 21 is connected to the first positive signal node 11a of the switch set 11 and the second negative counter plate 19a of the second negative capacitor 19. Is connected to the second negative signal node 12b of the switch set 12. The feedback switches 13 and 14 are open and thus output one bit of the thermometer code by the polarity of the voltage difference between the negative output node 16 and the positive output node 17 of the comparator 15.
    [46] The ratio of capacitance in the array of parallel capacitive comparator branches defines the reference level for converting analog to digital. This technique is now described with reference to capacitive comparator branch 10, as shown in detail in FIG. 4. It should be noted that all parallel branches have the same electronic circuit, except for the actual capacitance values of the capacitors 18, 19, 20, and 21.
    [47] The total number of parallel branches (n) determines the resolution (i.e. number of bits) of the digital thermometer code, e.g. if eight parallel branches (n = 8) of the capacitive comparator are used, the output of the ADC Has a resolution that is 8 bits. In this regard, 8-bit resolution in the case of thermometer codes encodes only eight different levels, not 256 levels in the case of non-redundant 8-bit binary codes. The n parallel capacitive comparator branches (eg, branch 10) both receive the same voltage variations corresponding to the first and second analog signals, and compare the ratio of these voltage variations in parallel through n predetermined capacitance ratios. The predetermined ratio is the ratio of weighted capacitances 20 and 18, or 21 and 19, ie C x / C r .
    [48] The common plates 20b / 18b of the first and second positive capacitors 18 and 20 are connected to the positive input node 22 of the comparator 15, and the common of the first and second negative capacitors 21 and 19. The plates 21b / 19b are connected to the negative input node 23 of the comparator 15. During the second phase of the clock cycle, the first positive counter plate 20a of the first positive capacitor 20 and the first negative counter plate 21a of the first negative capacitor 21 are each the first negative signal node 11b. (V x− ) and the first positive signal node 11a (V x + ). Similarly, the second positive counter plate 19a of the second positive capacitor 18 and the second negative counter plate 19a of the second negative capacitor 19 are the second positive signal node 12a (V r + ) and the second. The negative signal nodes V r- are respectively connected. The capacitances of the first positive and negative capacitors 20 and 21 are exactly matched (ie have the same capacitance) and the capacitances of the second positive and negative capacitors 18 and 19 are likewise matched. Therefore, during the second phase of the clock cycle, the voltage variation at the positive input node 22 and the negative input node 23 of the comparator 5 can be obtained from Equation 1, respectively.
    [49]
    [50]
    [51] Where V r + and V r− are respectively the second positive signal node 12a and 12 of the switch set 12 due to the second analog (differential voltage) signal V r (ie, V r = V r + -V r− ). Each voltage at the second negative signal node 12b, where V x + and V x− are the switches due to the first analog (differential voltage) signal V x (ie, V x = V x + -V x− ), respectively. Is the voltage at each of the first positive signal node 11a and the first negative signal node 11b of the set 11, C x is a weighted capacitance of V x , and C 0 is between each common plate and ground. Parasitic capacitance.
    [52] Therefore, the differential voltage shift between the positive input node 22 and the negative input node 23 of the comparator 15 is given by the following subtraction.
    [53]
    [54] In general, the n-th bit of the thermometer code, corresponding to the differential voltage shift between the positive output node 16 and the negative output node 17 of the comparator 15, can be obtained as in equation (2).
    [55]
    [56] The binary string (bit, 1; bit, 2; bit, 3; ... bit, n) is thus a digital n-bit thermo to the ratio V r / V x of the first and second analog (differential voltage) signals. Contains a meter code representation.
    [57] To obtain a linear ADC that converts the first analog signal V x from analog to digital, the second analog signal V r is applied as a reference and the weighted capacitance ratio is arranged to be a linear function of the array index. therefore:
    [58] C x, 1 / C r, 1 = n
    [59] C x, 2 / C r, 2 = n-1
    [60] C x, 3 / C r, 3 = n-2
    [61] .
    [62] .
    [63] .
    [64] C x, n / C r, n = 1
    [65] In this embodiment, it should be noted that the weighted capacitance of the large analog signal (i.e., the reference voltage) is smaller than the weighted capacitance of the small analog signal (i.e., the voltage signal from which the analog to digital conversion is to be performed). As a result, in this arrangement, the input signals are not interchangeable after fixing the capacitance ratio.
    [66] In another possible embodiment of the electronic circuit according to the invention, the set of capacitance ratios is not limited to vectors arranged linearly. No change is actually needed.
    [67] One such possible embodiment is the electronic circuit of a particular nonlinear ADC. The phase angle α of the periodic signal must be encoded, but the phase angle α cannot be accessed directly. The direct information available for the phase angle α is only two analog signals, one of which is proportional to the sine function of the phase angle and the other to the cosine function of the phase angle. In other words:
    [68] V r = c. Sin (α)
    [69] V x = c. Cos (α)
    [70] To obtain a linear transformation from the phase angle α to the n-bit thermometer code representation for α, the weighted capacitance ratio is designed to be the tangent of the phase angle, i.e. the tangent of the linear function of the array index. That is, for a phase angle α that fluctuates in the range 0 <α <π / 4:
    [71] C xi / C ri = tan (α i ), α = iπ / 4n, i = 1 ..... n
    [72] It will be appreciated that the above description serves only as an example, and that many other embodiments are possible within the scope and spirit of the invention.
    权利要求:
    Claims (11)
    [1" claim-type="Currently amended] An electronic circuit for a capacitive flash analog-to-digital converter that converts the speed of the first and second analog signals into a digital code representation using an array of parallel capacitive comparator branches, each branch having a digital code according to its array index. Computing one bit of at a time, the first analog signal is applied as a voltage difference between a first signal node comprising a first positive signal node and a first negative signal node, and the second analog signal is connected with a second positive signal node. An electronic circuit for the capacitive flash analog-to-digital converter, applied as a voltage difference between second signal nodes including a second negative signal node, wherein each branch is:
    (i) a comparator having a positive input node, a negative input node, a positive output node and a negative output node,
    (ii) first and second positive capacitors having a positive common plate connected to the positive input node of the comparator,
    (iii) first and second negative capacitors having negative common plates connected to the negative input node of the comparator, and
    (iv) a first and a second feedback switch,
    Each of the first and second positive capacitors has first and second positive counterplates switchably connected to first and second signal nodes, respectively, wherein each of the first and second negative capacitors is a first and second positive capacitor. And first and second negative counterplates switchably connected to the two signal nodes, respectively.
    [2" claim-type="Currently amended] The electronic circuit of claim 1 wherein the conversion from analog to digital is performed in one clock cycle comprising the first and second phases.
    [3" claim-type="Currently amended] The electronic circuit of claim 1 wherein the digital code is a digital thermometer code.
    [4" claim-type="Currently amended] 3. The method of claim 2, wherein in the first phase of the clock cycle, the first positive counter plate is connected to the first positive signal node and the second positive counter plate is connected to the second negative signal node and the first negative counter plate is connected to the first negative counter plate. The first negative switch connects the negative output node to the positive input node of the comparator and the second feedback switch connects the positive output node of the comparator To a negative input node; In the second phase of the clock cycle, the first positive counter plate is connected to the first negative signal node, the second positive counter plate is connected to the second positive signal node, and the first negative counter plate is connected to the first positive signal node. And the second negative counter plate is connected to the second negative signal node, the first and second feedback switches are opened, thereby outputting one bit of the digital code by the polarity of the voltage difference between the positive and negative output nodes of the comparator An electronic circuit, characterized in that.
    [5" claim-type="Currently amended] The electronic circuit of claim 1 wherein the capacitance of each of the first positive, first negative, second positive and second negative capacitors is different for each branch according to the array index of that branch.
    [6" claim-type="Currently amended] The method of claim 1, wherein in any one branch, the capacitance of the first positive capacitor is substantially the same as the capacitance of the first negative capacitor, and the capacitance of the second positive capacitor is substantially the same as the capacitance of the second negative capacitor. Electronic circuit.
    [7" claim-type="Currently amended] 7. The method of claim 6, wherein in any one branch, the ratio of the capacitances of the first positive and second positive capacitors is a linear function of the array index of that branch, thus between the ratio of the first and second analog signals and the digital code. Providing a linear transformation to the electronic circuit.
    [8" claim-type="Currently amended] 7. The method of claim 6, wherein in any one branch, the ratio of capacitances of the first positive and second positive capacitors is a non-linear function of the array index of that branch, thus between the ratio of the first and second analog signals and the digital code. Providing a non-linear conversion to the electronic circuit.
    [9" claim-type="Currently amended] The electronic circuit of claim 1 wherein the ratio of capacitances of each capacitor of different branches is linear as a function of array index.
    [10" claim-type="Currently amended] 2. The electronic circuit of claim 1, wherein the ratio of capacitances of each capacitor of different branches is nonlinear as a function of array index.
    [11" claim-type="Currently amended] 9. The method of claim 8, wherein the first analog signal corresponds to a sine function of the phase angle of the periodic signal, and the second analog signal corresponds to a cosine function of the phase angle of the periodic signal, and in any one branch, Wherein the ratio of capacitance of the second positive capacitor is a tangent function of the linear function of the array index of the branch, thereby providing a linear transformation between the phase angle and the digital code representation of the phase angle.
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    同族专利:
    公开号 | 公开日
    DE69924013D1|2005-04-07|
    ES2237185T3|2005-07-16|
    JP2002533973A|2002-10-08|
    AU1644700A|2000-07-12|
    CA2356341A1|2000-06-29|
    DE69924013T2|2006-04-13|
    EP1142126A4|2004-03-31|
    CN1348628A|2002-05-08|
    CN1146113C|2004-04-14|
    EP1142126A1|2001-10-10|
    AT290267T|2005-03-15|
    BR9917065A|2001-09-25|
    EP1142126B1|2005-03-02|
    MXPA01006423A|2002-06-04|
    AU752073B2|2002-09-05|
    WO2000038326A1|2000-06-29|
    US6617994B1|2003-09-09|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-12-22|Priority to AUPP7828A
    1998-12-22|Priority to AUPP7828
    1999-06-22|Priority to AUPQ1097
    1999-06-22|Priority to AUPQ1097A
    1999-12-01|Application filed by 클라우스 로우스케, 비숍 이노베이션 리미티드, 추후보정, 체에스에엠 센트레 스위쎄 데 엘렉트로니크 에트 데 미크로 테크니크 에스 아
    1999-12-01|Priority to PCT/AU1999/001063
    2001-12-07|Publication of KR20010108035A
    优先权:
    申请号 | 申请日 | 专利标题
    AUPP7828A|AUPP782898A0|1998-12-22|1998-12-22|Capacitive flash analog to digital converter|
    AUPP7828|1998-12-22|
    AUPQ1097|1999-06-22|
    AUPQ1097A|AUPQ109799A0|1999-06-22|1999-06-22|Capacitive flash analog to digital converter|
    PCT/AU1999/001063|WO2000038326A1|1998-12-22|1999-12-01|Capacitive flash analog to digital converter|
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