• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    Pre-crystallizing the surface layers of crystalline silicon to extremely shallow (401 and 402) depths (ie, less than 100 nm) presents a solution to the following fabrication problems. Problems in the fabrication process include (1) high thermal conductivity of crystalline silicon and (2) shading and diffraction-interfering effects on incident laser irradiation by field effect transistors already manufactured. Conventionally, due to such problems, the prior art projection gas immersion laser doping (P-GILD) has not been effectively used in the manufacture of integrated circuits having MOS field effect transistors in which shallow junction techniques of 100 nm or less are used.
    公开号:KR20000070658A
    申请号:KR1019997006907
    申请日:1998-01-29
    公开日:2000-11-25
    发明作者:탈워소밋；크래이머칼-조셉；버마과라브；웨이너커트
    申请人:마클 데이빗 에이.；울트라테크 스테퍼 인코포레이티드；
    IPC主号:
    专利说明:

    Manufacturing method of small integrated circuit {FABRICATION MEHTOD FOR REDUCED-DIMENSION INTEGRATED CIRCUITS}
    CMOS field effect transistors (FETs) with gate lengths of 0.25 mm will be commercially available soon. Typically, in the fabrication of such 0.25 mm FETs, ion implantation is used for silicon doping. However, MOSFETs are currently being developed with reduced gate lengths of less than 0.18 mm. Source-drain junction depth scaling is needed to reduce the gate length. For such 0.18 mm CMOS technology, a junction depth of less than 80 nm is proposed, according to "The National Technical Roadmap for Semiconductors" (1995) of the Semiconductor Industry Association. Such junctions are difficult to form using ion implantation because of ion-channeling and transiently enhanced diffusion.
    For related references, see Jpn. J. Appl. Phys. Vol. 31 (Dec. 1992) Pt. 1, No. 12B, pages 4437-4440, T. Akane et al., "Two-Step Doping Using Excimer Laser in Boron Doping of Silicon," and other methods for silicon doping are disclosed. See also IEEE Electron Device Letters, Vol. 9, No. 10, (Oct. 1988), P. G. Carey et al., "A Shallow Junction Submicrometer PMOS Process Without High-Temperature Anneals", described in pages 542-544.
    In addition, as related references, J. ElectroChem. Soc., Vol. 137, No. 6 (June. 1990), S. Prussin et al., "Role of Ion Mass, Implant Dose, and Wafer Temperature on End-of-Range Defects", IEEE Transactions on Electron Devices, Vol. 17. No. 10 (Oct. 1990), "Damage Removal / Dopant Diffusion Tradeoffs in Ultra-Shallow Implanted p + -n Junctions" of the RB Fair described in pages 2237-2241 and Materials Science and Engineering, B34, (1995) pp 168-174. S. Acco et al., “Avoiding End-of-Range Dislocations in Ion-Implanted Silicon” and the like, all of which relate to ion implantation for amorphousization of silicon.
    If the thermal conductivity of crystalline silicon is not high, due to absorption near the surface of the laser light and short laser pulse width, it is extremely shallow using conventional projection gas immersion laser doping (P-GILD). The formation of a junction (eg less than 100 nm) will be possible. In this case, the geometry of the MOSFET device to be produced causes shadowing and diffraction of the laser light shining on the surface of the device, which greatly affects the thermal loading. However, the high thermal conductivity of crystalline silicon serves to reduce the junction depth at the edge. This thermal conduction effect is evident as the dimension of the doped region approaches the thermal diffusion length. Thus, the properties of the doped regions are a function of their dimensions and external shape. In the case of source / drain doping in a CMOS device, this results in that the doped region does not extend to a gate (negative gate overlap) or isolation. Because of the short parasitic resistance between the junction and the well and the high parasitic resistance, the performance of the device is degraded, which causes a fatal problem.
    TECHNICAL FIELD The present invention relates to the manufacture of integrated circuits (ICs), and more particularly to the manufacture of ICs having metal oxide semiconductor field effect transistors (MOSFETs) employing shallow junctions of 100 nm or less.
    1 schematically illustrates the structure of two FETs fabricated in accordance with existing silicon CMOS technology.
    FIG. 2A schematically illustrates the pattern of thermal diffusion from the heated upper region of a MOSFET, which occurs when using P-GILD in manufacturing.
    FIG. 2B schematically illustrates the shadowing and diffraction-interference effects due to the gate polycrystalline (poly) structure of the MOSFET, which occurs when using P-GILD in manufacturing.
    FIG. 3 schematically illustrates the structure of one of the MOSFETs of FIG. 1 in the stage of fabrication of the MOSFET in the stage of doping of the extension or the stage of doping of the source or drain, and the stage of well following the doping of the source according to the present invention.
    4 schematically illustrates a fabrication step in accordance with the present invention, comprising the step of amorphizing the surface by ion implantation of silicon forming the upper region of the MOSFET of FIG. 3.
    FIG. 5 is a doping step according to the manufacturing method of the present invention in which a doping comprising an extension of a FET and both gate polys is performed with a pre-deposited dopant thin film using irradiation from a second laser (surface amorphous of FIG. 4). And a step after another intermediate step including irradiation from a first laser operation used to predepositively deposit the dopant thin film.
    The manufacturing method of the present invention makes it possible to use P-GILD in the formation of extremely shallow (eg less than 80 nm) junctions by presenting a solution to the above-mentioned problems of thermal diffusion.
    More specifically, according to the manufacturing method of the present invention, first, a predetermined surface layer of crystalline silicon is amorphous to a predetermined depth. Thereafter, a predetermined amount of the dopant is deposited in a thin film on the surface of the predetermined amorphous silicon surface layer. Thereafter, at least a portion of the predetermined amorphous silicon surface layer is applied for a predetermined time at a temperature sufficient to melt the amorphous silicon but insufficient to melt the crystalline silicon (since the melting point of the amorphous silicon is substantially lower than the melting point of the crystalline silicon). Heat temporarily After the heating for a predetermined time is completed, the molten silicon of the heated portion is cooled to perform silicon recrystallization of the heat treated portion of the predetermined surface layer.
    Referring to FIG. 1, a CMOS structure is shown that includes a silicon substrate 100, an isolation 102, and complementary complementary FETs 104a and 104b. The structure of the complementary FETs 104a and 104b is that the FET 104a consists of an n well 106a, a p + source 108a and a p + drain 110a, whereas the FET 104b is a p well 106b, It differs only in that it consists of n + source 108b and n + drain 110b. In all other respects, the structure of complementary FETs 104a and 104b is similar. Specifically, both complementary FETs 104a and 104b are (1) gate poly 112, (2) sidewall spacers 116, (3) each insulated from the wells of the FET by SiO 2 thin film layer 114. (4) source and drain of each complementary FETs 102a, 104b located on top of the gate poly, source and drain of the complementary FETs 102a, 104b, and (4) It has a shallowly doped extension 118 that engages the area.
    It can be seen from FIG. 1 that the shallowest junction is the extension 118, which connects the deep source and drain to the channel. The extension 118 needs to prevent drain induced barrier lowering (DIBL) and punchthrough. The extension is formed by shallow low energy injection and annealing, then forms sidewall spacers and implants deep source / drain.
    At this time, the minimum gate dimension that can be immediately employed in commercial manufacture of the MOSFET structure is 0.25 mm. In this case, after the extension portion 118 is formed by relatively shallow low energy implantation, p + and n + sources 108a and 108b and drains 110a and 110b are formed by relatively deep high energy ion implantation. However, in the manufacture of MOSFET structures, scaling down to a gate length of 0.18 mm results in a shallow junction depth of the existing extension 118 being reduced to less than 80 nm. The shallow junction depth to this extension 118 is difficult to form using ion implantation due to ion channeling and temporarily enhanced diffusion.
    As described in the background section of the present invention, because of the problems arising due to the high thermal conductivity of crystalline silicon, in order to form a junction of less than 80 nm for each extension 118, instead of ion implantation, P-GILD technology is not available.
    FIG. 2A shows only the thermal diffusion pattern of a portion of the silicon of the MOSFET relatively closer to the gate 202 than the IC isolation. Using the prior art P-GILD during the manufacture of an IC MOSFET device will heat up the entire single crystal silicon top surface layer 200 between adjacent IC isolations. As indicated by the solid arrows 204 in FIG. 2, at a distance from the gate 202, heating can be modeled using one-dimensional thermal diffusion. However, the area under the gate 202 shielded from the laser light remains cooler than the area away from the gate 202. Thus, around the gate 202, there is a thermal gradient in both vertical and horizontal directions. This is two-dimensional thermal diffusion around the gate 202, as shown by the dashed arrow 206 in FIG. 2A. Therefore, when employing the prior art P-GILD laser irradiation for the manufacture of the FET, cooling in the vicinity of the gate is promoted, so that melting becomes shallower or does not occur.
    In addition, although not shown in Fig. 2A, when the conventional P-GILD laser irradiation is used for the manufacture of the FET, during the manufacture of each CMOS FETs in Fig. 1, the junction between the source and drain regions of the FET and the isolation portion 2 It is clear that there is a dimensional thermal diffusion pattern.
    2B schematically illustrates the light blocking effect 208 and the diffraction-interfering effect 210 due to the presence of the gate 202. More specifically, the light blocking effect in the region of the top of the silicon surface defined by each inclined dotted line 212 and the vertical sidewall of the gate 202 is schematically represented by the box 214. The interference effect is shown graphically by box 216.
    2B shows the illumination effect near the gate edge. Because of the large numerical aperture of the P-GILD projection system, the angle of incidence varies from 90 degrees to 50 degrees. Due to the increase in the angle of the irradiated laser light, the shading by the gate can be reduced by 50% of the light in the adjacent region. A portion of the fluence loss can be compensated for by additional light reflected at the silicon sidewall of the gate 202. However, it can be seen that silicon exhibits a low reflectance of TM polarized light near the grazing angle. Because of this low reflectance of the TM polarized light, a large amount of light is actually absorbed in the light shelves incident on the gate sidewalls. Thus, reflections at the gate 202 may not fully compensate for fluence losses due to shading. Further, the diffraction from the edge of the gate 202 and the interference between the reflection of the gate 202 and the incident light reduce the incident intensity near the edge of the gate 202. For this reason, the region near the gate is cooled more than the remaining source and drain regions.
    Thus, by combining increased cooling and shading at the gate edge, it is possible to prevent the melt from extending to the edge of the gate 202. It is also possible to bring the melt to the gate 202 by sufficiently high laser energy, but it is not desirable to use such high laser energy. Also, because of the large thermal gradient under the gate 202, the negative overlap between the gate 202 and the melt increases as the length of the gate increases. This circuit may consist of devices with varying gate lengths. Therefore, the negative overlap will change depending on the type of device. Negative overlap causes high series resistance and large leakage to the substrate. In modern CMOS technology, such a junction is not allowed, and it is necessary to devise a method to ensure that the junction extends to the gate for all gate lengths.
    Moreover, when silicidation is carried out, two-dimensional cooling inhibits melting near the edge of the isolation, causing short between the junction and the well. As a result, the drain cannot be biased with respect to the well. Therefore, it is very important to melt the isolation 102.
    Hereinafter, a relatively simple process performed by the method of the present invention shown in FIGS. 3 to 6 will be described. This method avoids the above problems of the reduction of laser fluence due to shading and diffraction-negative and negative overlay due to two-dimensional cooling when the prior art P-GILD laser irradiation is used for the manufacture of the MOSFETs of FIG. have.
    FIG. 3 illustrates a MOSFET manufacturing step of one of the MOSFETs of FIG. 1 immediately before execution of the manufacturing step including the manufacturing step of the present invention shown in FIGS. 4 and 5. In the fabrication step shown in FIG. 3, the gate poly 112 located on the well 106 and the SiO 2 thin film layer 114 has already been fabricated.
    The first fabrication step of the present invention, shown in FIG. 4, comprises regions of the MOSFET of FIG. 1 including an upper polycrystalline silicon layer 400 of the gate poly 112 and an upper monocrystalline silicon layer 402 of the well 106. Amorphizing to the desired extremely shallow depth. Amorphization may be accomplished by ion implantation of heavy elements such as argon, silicon and germanium, as indicated by arrow 404 in FIG. However, germanium is preferred because it requires a low dose to amorphous silicon, is a heavy atom that creates a sudden amorphous-crystal chamber interface, and is isoelectronic in the silicon lattice.
    More specifically, as shown in FIG. 4, the layers 402 on both sides of the gate poly 112 to be amorphous extend to the isolation. For example, if the depth of the extremely shallow layers 400 and 402 to be amorphous is substantially 300 mW (less than 80 nm), in order to obtain a desired 300 mW amorphous depth, 2 x 10 14 atoms / cm 2 Need help. By injecting germanium with a dose of 20 KeV and 2 x 10 14 atoms / cm 2 , the layers 400 and 402 having the desired crystallinity depth of 300 kPa can be obtained. This injection condition can be easily obtained using existing injectors.
    As known (see the paper of RB Fair described above), amorphous depth is a function of injection dose and injection energy. Depending on the desired amorphous depth, the injection dose ranges between 1 × 10 13 atoms / cm 2 and 1 × 10 16 atoms / cm 2 , and the injection energy ranges between 5 KeV and 400 KeV.
    After completion of the silicon amorphous manufacturing step of FIG. 4, by (1) removing the SiO 2 thin film layer 300, and (2) decomposing the dopant compound in a predetermined gas form using an ArF excimer laser (l = 193 nm). The first step of a known P-GILD operation (eg, the operation is T), by depositing a thin film of a dopant in solid form (by photolytic decomposition) on the upper surface of the MOSFET to be produced. Two steps consisting of "Two-Step Doping Using Excimer Laser in Boron Doping of Silicon," by Akane et al., Which are not shown in the figure. The amount of dose introduced into the amorphous layers 400, 402 during the second phase of the known P-GILD operation depends on the amount of predetermined dopant compound deposited in advance during the first phase of the known P-GILD operation.
    FIG. 5 illustrates a second stage of the P-GILD operation, which is performed after completion of the two not shown manufacturing steps described above. As shown in FIG. 5, the dopant thin film 500 previously deposited on the upper surface layers 400 and 402 of the MOSFET to be manufactured is irradiated with an excimer laser irradiation 502. The excimer laser irradiation may be derived from an ArF excimer laser irradiating at a wavelength of 193 nm (see T. Akan et al.), But other types of lasers (eg 248 nm KrF laser, 351 nm XeF laser, Or 308 nm XeCl laser). Applicant performed the second step of the above-described P-GILD operation using a pulsed XeCl excimer laser irradiating at a wavelength of 308 nm.
    More specifically, amorphous silicon has a lower thermal conductivity, a lower melting point of 300 ° C., and a lower reflectance of 30% than crystalline silicon. By combining these effects, the melt threshold of amorphous silicon is reduced compared to crystalline silicon.
    Referring again to FIG. 1, in the process of forming the extension 118, the depth of the amorphous layer is limited to the extent necessary for the area to be occupied by each of the extensions. Thus, because the second step of the P-GILD operation used to lightly dope the region of the extension 118 significantly reduces the thermal conductivity and melting temperature of these amorphous layers, the amorphous silicon layer becomes a gate poly ( Melt to the edge of 112). More specifically, the second step of the P-GILD operation involves a continuous pulse of laser irradiation. The irradiation energy of each of these successive pulses is sufficient to melt the amorphous silicon spot but insufficient to melt the crystalline silicon spot. After completing the first irradiation of a particular spot with a laser pulse, the molten silicon just doped is immediately cooled and recrystallized. Irradiating with a first pulse a predetermined amorphous silicon spot that overlaps the recrystallized silicon of the already irradiated spot will not melt the recrystallized silicon, but will only melt the predetermined amorphous silicon spot. will be. In addition, since the liquid silicon is very insufficiently cooled and the silicon can no longer be melted, there is a large energy window in the place where the melting does not extend beyond the amorphous region. Thus, amorphous can be used to define the melt depth.
    The fluence range for laser irradiation ranges from 0.05 Joules / cm 2 to 1.0 Joules / cm 2, but is closest to the irradiation fluence, which is sufficient to heat amorphous silicon to melting temperature and insufficient to heat crystalline silicon to melting temperature. The pitch is 0.4 Joules / cm 2 .
    As shown in FIGS. 4 and 5, layer 400 of gate poly 112 is amorphous and doped. If doping of the gate poly 112 is not required, by employing a mask layer on the gate poly 112 during the amorphous implantation of FIG. 4, the gate melting of the gate poly 112 is a second step of the P-GILD operation. It can also be suppressed from occurring.
    As mentioned above, the use of two-step P-GILD followed by pre-amorphization of silicon is particularly suitable for the manufacture of extremely shallow junctions (ie, depths of less than 100 nm) of extension 118, and the deep source of the MOSFET to be fabricated. And two-step P-GILD followed by pre-amorphization of silicon also for doping the drain region. In detail, after fabrication of the junction of the extremely shallow extension 118, the sidewall spacer 116 is fabricated. Thereafter, each deep source and drain region located between each sidewall spacer 116 and isolation 102 is amorphous again to a desired depth deeper than the original amorphous depth described above. This may be done with higher energy (eg 40 KeV) and doses (eg 6 × 10 14 atoms / cm 2 germanium implantation). Following such remorphization, using two stages of P-GILD, (1) the appropriate deposition concentration of the dopant thin film during the first of these two stages and (2) the second of these two stages Proper pulse laser energy is provided that can only melt the amorphous source and drain during the step.
    One reason to use the two steps of the present invention described in the preceding paragraph, instead of conventional ion implantation doping, for deep source and drain doping is that the doping depth can be controlled more precisely. Another reason is that the above method is cheaper.
    In the method of the preferred embodiment of the present invention described above, because the prefabricated extremely shallow junction extends to the sidewall spacer 116, the preparation of deep source and drain is a prefabricated extremely shallow (ie, less than 100 nm) junction. Entails recrystallization of. However, it is to be understood that the range of the extremely shallow junction is limited only by the location of the extension and therefore does not include the location of the deep source and drain. In this case, since the amorphous to the source and drain positions is independent of the amorphous to the extended position, the amorphous to the source and drain positions may occur before or after the amorphous to the extended position. Further, the present invention may be used for the manufacture of only the extension of the MOSFET or the manufacture of only the deep source and the drain of the MOSFET, in addition to the manufacture of both the extension of the MOSFET and the deep source and drain of the MOSFET.
    As is known, amorphous injection results in supersaturated caustic defects. When performing annealing, the injection of point defects causes nucleation of a wide range of defects. Conventional critical annealing temperatures should be able to anneal such a wide range of defects. The typical annealing required for the first amorphous injection shown in FIG. 4 and described above is 10 seconds at 1050 ° C. However, laser melting of amorphous silicon by a two-step P-GILD operation inherently provides some degree of annealing. In addition, since a small number of point defects exist after the laser process, the bonding does not move much as a result of this thermal cycling. Thus, in this case, for the laser annealed junction, no additional annealing may be necessary. In some cases, however, in order to determine whether further annealing is necessary, it is necessary to experimentally determine the exact range of diffusion after laser annealing.
    权利要求:
    Claims (17)
    [1" claim-type="Currently amended] A method of fabricating a source drain junction of a MOSFET on a substrate having a predetermined crystalline silicon surface layer,
    (a) amorphizing silicon of the predetermined crystalline silicon surface layer of the substrate to a predetermined amorphous depth,
    (b) depositing a predetermined amount of dopant into a film on the surface of the predetermined amorphous silicon surface layer, and
    (c) at least a portion of the predetermined amorphous surface layer of the silicon is temporarily heated for a period of time to a temperature sufficient to melt the amorphous silicon, but insufficient to melt the crystalline silicon, for the deposited dopant Diffusing to the predetermined molten amorphous silicon surface layer,
    Cooling said portion of molten silicon after said predetermined time to recrystallize said portion of silicon of said predetermined surface layer.
    [2" claim-type="Currently amended] The method of claim 1,
    And wherein the silicon having the predetermined amorphous depth is located on the crystalline silicon.
    [3" claim-type="Currently amended] The method of claim 1, wherein step (a)
    (d) implanting a predetermined heavy element ionized and accelerated to a predetermined energy by an ion implanter at a concentration per predetermined unit area to a predetermined amorphous depth, thereby amorphizing the predetermined surface layer of silicon. How to feature.
    [4" claim-type="Currently amended] The method of claim 3, wherein
    The predetermined heavy element is germanium.
    [5" claim-type="Currently amended] The method of claim 3, wherein
    Wherein said predetermined concentration per unit area is substantially 2 x 10 14 atoms / cm 2 , and said predetermined energy is substantially 20 Kev.
    [6" claim-type="Currently amended] The method of claim 3, wherein
    Wherein said predetermined concentration per unit area is substantially 6 x 10 14 atoms / cm 2 , and said predetermined energy is substantially 40 Kev.
    [7" claim-type="Currently amended] The process of claim 1 wherein step (b) comprises:
    (d) decomposing a predetermined dopant compound into gaseous form using irradiation from a laser, and depositing the predetermined amount of dopant in a solid form thin film on the surface of the predetermined amorphous silicon surface layer. And a step of forming the same.
    [8" claim-type="Currently amended] The method of claim 1, wherein step (c) comprises:
    (d) temporarily heating at least the portion of the predetermined amorphous surface layer of silicon using a predetermined amount of radial fluence from a laser.
    [9" claim-type="Currently amended] The method of claim 8,
    The predetermined amount of radial fluence from the laser is substantially 0.4 Joules / cm 2 .
    [10" claim-type="Currently amended] The method of claim 8, wherein step (d)
    (e) applying a single pulse of successive pulses of radiant energy from a pulsed laser to the irradiated area of the predetermined amorphous surface layer of the silicon, thereby reducing the area during the duration of a single pulse of the continuous pulses. Heating;
    Wherein the energy of a single pulse of the successive pulses is sufficient to heat amorphous silicon in the irradiated region to its melting temperature, but insufficient to heat crystalline silicon to its melting temperature.
    [11" claim-type="Currently amended] In a method of manufacturing an integrated circuit for fabricating MOSFETs on a silicon substrate, adjacent FETs are separated from each other by isolation, and each manufactured FET is formed on (1) an appropriately doped single crystal silicon well surface (2). ) A polycrystalline silicon gate, (3) first and second sidewall spacers respectively located on one side of said polycrystalline silicon gate, (4) extending longitudinally from a first isolation near the distal edge of said first sidewall spacer A relatively deep and suitably doped single crystal silicon source, (5) extending longitudinally from the second isolation near the distal edge of the second sidewall spacer, and relatively deep and properly doped single crystal silicon drain, (6) the source A lightly doped ultra shallow first single crystal silicon extension located below the first sidewall spacer for connecting to an adjacent gate edge, and (7) the A lightly doped, extremely shallow second single crystal silicon extension located below said second sidewall spacer for connecting a drain to an adjacent gate edge,
    The method comprises, for the fabrication of each of the extremely shallowly doped first and second single crystal silicon extensions after fabrication of the well and the polycrystalline silicon gate and prior to fabrication of the first and second sidewall spacers.
    (a) An ion is implanted into each of the first and second surface layers of the single crystal silicon well extending longitudinally from the gate edge of the polycrystalline silicon to the isolation portion at a predetermined concentration and a predetermined energy per unit area, thereby providing the first and second Amorphizing the layer to a predetermined depth of less than 100 nm,
    (b) in order to dope the extension, a predetermined dopant compound is decomposed into a gaseous form by irradiation from a laser, and a predetermined amount of the dopant is formed into a solid thin film on the first and second amorphous surface layers. Depositing,
    (c) applying a first one of two consecutive pulses of radiant energy from a pulsed laser to a first one of two overlapping irradiated areas of said predetermined amorphous surface layer of said silicon, said continuous pulse Heating the first region for the duration of the first pulse of and thereafter performing a second one of the two consecutive pulses of radiation energy from the pulsed laser to the surface of the predetermined amorphous surface layer of silicon. Applying to a second one of the two irradiated areas that overlap, heating the second area for the duration of the second pulse of the continuous pulse, wherein each of the separated first and second consecutive The irradiation energy of the pulse is sufficient to heat the amorphous silicon in the irradiated region to its melting temperature, but not to heat the crystalline silicon to its melting temperature. Insufficient steps, and
    (d) between the application of the first one of the two consecutive pulses and the application of the second one of the two consecutive pulses, the second one of the two consecutive pulses overlapping the two; Prior to being applied to the amorphous silicon of the second one of the regions, providing a long time interval sufficient for molten and amorphous silicon of the first region of the two overlapping regions to cool and recrystallize. The integrated circuit manufacturing method characterized in that it comprises.
    [12" claim-type="Currently amended] The method of claim 11,
    And the concentration per said predetermined unit area of said ion implanted atoms is substantially 2 x 10 14 atoms / cm 2 and said predetermined energy is substantially 20 KeV.
    [13" claim-type="Currently amended] The method of claim 11,
    The ion implanted atom is characterized in that the germanium.
    [14" claim-type="Currently amended] The method of claim 12,
    The concentration per ion area of the ion implanted germanium atom is substantially 2 x 10 14 atoms / cm 2 and the predetermined energy is substantially 20 KeV,
    And wherein the amorphous depth of said first and second layers is substantially 300 GPa.
    [15" claim-type="Currently amended] The method of claim 11, wherein step (a) comprises:
    And implanting germanium atoms into the upper surface layer of the polycrystalline silicon gate at a concentration per predetermined unit area and a predetermined energy to amorphize the upper surface layer of the polycrystalline silicon gate to a predetermined depth of about 300 GPa. How to.
    [16" claim-type="Currently amended] The method of claim 11,
    After fabrication of the first and second sidewall spacers, a method of fabricating the relatively deep and suitably doped single crystal silicon source and drain, respectively,
    (a) a source layer of the single crystal silicon extending longitudinally from the edge of the first sidewall spacer to the isolation and (2) a drain layer of the single crystal silicon extending longitudinally from the edge of the second sidewall spacer to the isolation. Respectively implanting atoms at a concentration of 6 × 10 14 atoms / cm 2 and an energy of 40 KeV to amorphousize the source and drain layers to a relatively deep depth required for the source and drain,
    (b) in order to properly dope the source and drain layers, a predetermined amount of dopant is photolysed in gaseous form by irradiation from a laser to form a predetermined amount of dopant on the surface of the amorphous source and drain layer. Depositing a solid thin film,
    (c) applying a first pulse of two consecutive pulses of radiant energy from a pulsed laser to a first irradiation region of either of said source and drain amorphous layers of said silicon, thereby producing said first pulse of said continuous pulse; After heating the first region for one pulse duration, the second of the two consecutive pulses of radiation energy from the pulsed laser overlaps the silicon of the silicon at least partially overlapping the first irradiation region. Applying to the second irradiated region of any one of the source and drain amorphous layers to heat the second region for the duration of the second pulse of the continuous pulses, each of the separated first and The irradiation energy of the second continuous pulse is sufficient to heat the amorphous silicon in the irradiation zone to its melting temperature, but the crystalline silicon Insufficient step hagieneun heated to the melting temperature, and
    (d) between the application of the first one of the two consecutive pulses and the application of the second one of the two consecutive pulses, the second one of the two consecutive pulses of the second region; And before applying to amorphous silicon, providing a time interval long enough to cool and recrystallize the molten amorphous silicon in the first region.
    [17" claim-type="Currently amended] The method of claim 16,
    (e) repeating steps (c) and (d) for the other layer of the source and drain amorphous layers of the silicon of any one layer.
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    JP2001509316A|2001-07-10|
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    WO1998034268A3|1999-02-18|
    DE69807718T2|2003-07-31|
    US5908307A|1999-06-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-01-31|Priority to US08/792,107
    1997-01-31|Priority to US08/792,107
    1997-01-31|Priority to US8/792,107
    1998-01-29|Application filed by 마클 데이빗 에이., 울트라테크 스테퍼 인코포레이티드
    1998-01-29|Priority to PCT/US1998/001942
    2000-11-25|Publication of KR20000070658A
    2005-09-05|Application granted
    2005-09-05|Publication of KR100511765B1
    优先权:
    申请号 | 申请日 | 专利标题
    US08/792,107|US5908307A|1997-01-31|1997-01-31|Fabrication method for reduced-dimension FET devices|
    US08/792,107|1997-01-31|
    US8/792,107|1997-01-31|
    PCT/US1998/001942|WO1998034268A2|1997-01-31|1998-01-29|Fabrication method for reduced-dimension integrated circuits|
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