square device

专利摘要:
The squarer is to reduce the number of gates used in the calculation, and multiplies the absolute value operator that takes an absolute value with the input data, and multiplies its own value for each bit output from the absolute value operator and calculates the result. A multi-part calculating unit for multiplying different bits output from the absolute value calculating unit and calculating a result value, and adding a value output from the square calculating unit and a value output from the multi-part calculating unit; And a selector for outputting a value output from the adder or a preset value according to the signal output from the absolute value calculator.
公开号:KR20000060086A
申请号:KR1019990008134
申请日:1999-03-11
公开日:2000-10-16
发明作者:박민영
申请人:구자홍；엘지전자 주식회사；
IPC主号:

专利说明:

Square device
TECHNICAL FIELD The present invention relates to a squarer, and more particularly, to a squarer having a gate count of at least 50% less than that of conventional methods.
The easiest way to do this is to use a common multiplier.
In general, when the multiplier is used, a circuit is synthesized with a size of about 1000 gate information when 10 bits x 10 bits are multiplied.
Also, as the number of bits to be multiplied increases, the size increases exponentially.
Hereinafter, a squarer according to the prior art will be described with reference to the accompanying drawings.
1 is a diagram illustrating a squarer using a multiplier according to the prior art, and is composed of a multiplier 1 that multiplies input data by itself and outputs squared data.
FIG. 2 is a diagram illustrating a correlation between the number of bits and a gate of the multiplier of FIG. 1.
The operation of the squarer according to the prior art configured as described above will be described in detail with reference to the accompanying drawings.
First, the multiplier 1 multiplies the input data with itself and outputs squared data.
In the conventional multiplier, the multiplier occupies a very large part of the overall design, even though it is a simple function when squares are to be performed several times in the entire ASIC design, as shown in FIG. Even if there are only 10, the size of the multiplier becomes 10,000 gates, which causes a problem in design.
In addition, in the squarer according to the prior art, there is a method of dividing the multiplication by several cycles in order to reduce the number of gates and multiply the same number of bits. This method can be used if the result of multiplication in one clock cycle is desired in an ASIC design There is also a problem.
Accordingly, an object of the present invention is to provide a squarer designed to reduce the number of gates used in an operation.
1 is a view showing a squarer according to the prior art
FIG. 2 is a diagram illustrating a correlation between the number of bits and a gate of the multiplier of FIG. 1. FIG.
Figure 3 is an embodiment showing the configuration of a squarer according to the present invention
4 is a diagram illustrating a detailed configuration of a square calculation unit of FIG. 3;
5 is a diagram illustrating a detailed configuration of the multi-part calculation unit of FIG. 3.
6 is a view showing the operating principle of FIG.
7 is a diagram illustrating an embodiment of an operating state of an adder of FIG. 3;
8 is a view showing another embodiment of an operating state of the adder of FIG.
Explanation of symbols for main parts of the drawings
101: absolute value calculation unit 102: square calculation unit
103: multi-part calculation unit 104: adder
105: selector
A feature of the squarer according to the present invention for achieving the above object is, the result value after multiplying the absolute value calculator taking an absolute value to the input data and its own value for each bit output from the absolute value calculator A multi-part calculation unit for multiplying different bits output from the absolute value operation unit and calculating a result value, a value output from the square calculation unit and a value output from the multi-part calculation unit And an adder for adding a signal and a selector for outputting a value output from the adder or a preset value according to the signal output from the absolute value calculator.
Hereinafter, a preferred embodiment of a squarer according to the present invention will be described with reference to the accompanying drawings.
3 is an embodiment showing the configuration of a squarer according to the present invention. The absolute value calculating unit 101 takes an absolute value on input data and its own value for each bit output from the absolute value calculating unit 101. The multiplier calculation unit 102 calculates by multiplying by the multi-part calculation unit 103 and multiplying the different bits output from the absolute value calculation unit 101, and the value output from the square calculation unit 102 and An adder 104 that adds a value output from the multi-part calculator 103 and a value output from the adder 104 according to a signal output from the absolute value calculator 101, or outputs a preset value. It consists of the selection part 105 which outputs.
4 is a diagram illustrating a detailed configuration of the square calculation unit of FIG. 3, FIG. 5 is a diagram illustrating a detailed configuration of the multi-part calculation unit of FIG. 3, and FIG. 6 is a diagram illustrating an operation principle of FIG. 5.
7 is a diagram illustrating an embodiment of an operating state of the adder of FIG. 3, and FIG. 8 is a diagram illustrating another embodiment of an operating state of the adder of FIG. 3.
The operation of the squarer according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.
First, the absolute value calculator 101 takes an absolute value into the input data a [n-1: 0] and outputs the resultant data b [n-1: 0].
That is, the absolute value calculating section 101 takes an absolute value to the input data a [n-1: 0], and converts the result data b [n-1: 0] into the selection section 105, resulting in the result data ( b [n-2: 0]) is output to the square calculation unit 102 and the multi-part calculation unit 103.
Then, the square calculating unit 102 multiplies its own value for each bit of the data b [n-2: 0] output from the absolute value calculating unit 101, and as a result, the data (sq [(n-2)). * 2: 0]).
That is, as shown in FIG. 4, the square calculation unit 102 performs n = 6 on each bit of five input bits if the data b [n-2: 0] output from the absolute value calculation unit 101 is n = 6. Since b4 is sq8 bits, b3 is sq6 bits, b2 is sq4 bits, b1 is sq2, and b0 is sq0.
In addition, the multi-part calculating unit 103 multiplies different bits of the data b [n-2: 0] output from the absolute value calculating unit 101, and as a result, the data m [(n-1) * 2- 1: 2]).
Accordingly, the adder 104 outputs the data (sq [(n-2) * 2: 0]) output from the square calculation unit 102 and the data (m [(n) output from the multi-part calculation unit 103. -1) * 2-1: 2]) is added to output the result signal.
Then, the selector 105 outputs a value output from the adder 104 or a preset value according to the signal output from the absolute value calculator 101.
That is, if the most significant bit for the absolute value is "1" in the absolute value calculator 101, the selector 105 may know that data having the largest absolute value has been input, and thus the output data c [( Only the c [(n-1) * 2] bits of n-1) * 2: 0] are set to "1" and output.
For example, if the input data value is "-128", the absolute value calculating unit 101 takes an absolute value of the "-128" and outputs "128". If "-128" is an 8-bit input, If the most significant bit is "1" and this is squared, the eighth bit is shifted seven times to the left, so if only the 15th bit of the output data is set to 1 and outputted, this is 128 * 128 = 16384.
The selector 105 selects and outputs the data output from the adder 104 when the most significant bit for the absolute value is 0 in the absolute value calculator 101.
For example, if the input data has 10 bits as shown in Equation 1 below, the data is squared to obtain a result as shown in Equation 2 below.

Then, the square calculation unit 102 multiplies its own value for each bit of Equation 1 and outputs a value as shown in Equation 3 below.
Here, when data of b [n-2: 0] and n = 6 is input from the absolute value calculating unit 101 to the square calculating unit 102, the square calculating unit 102 is a self for each bit of Equation 1 above. Is multiplied as shown in FIG. 4 to output a value shown in Equation 3 below.
In addition, the multi-part calculator 103 multiplies the different bits of Equation 1 as shown in FIGS. 5 and 6 to output a value shown in Equation 4 below.

Here, when data of b [n-2: 0] and n = 6 is input from the absolute value calculator 101 to the multi-part calculator 103, the multi-part calculator 103 may use different bits of Equation 1 above. Is multiplied as shown in FIGS. 5 and 6 to output a value as shown in Equation 4 below.
That is, as shown in Figures 5 and 6, the multi-part calculation unit 103 multiplies b4, b3, b2, b1 input in the first step, such as Equation 4 by 2 to m5, m4, m3, m2 Calculate
Next, multiply b4, b3, and b2 input in the second step by 2 ² to calculate m6, m5, and m4, add m7 for overflow, and add the inputs 0, b4, b3, and b2 through the adder 103a. In addition, the resulting signals m7, m6, m5, and m4 are output.
After adding m8 to m7 and m6 output from the adder 103a, the resultant signals m8, m7 and m6 are output in addition to 0, b4 and b3 input through the adder 103b.
Subsequently, m9 is added to m8 output from the adder 103b, and 0 and b4 input through the adder 103c are added to output the resultant signals m [(n-1) * 2] and n = 6. .
Accordingly, the adder 104 outputs the data output as shown in Equation 3 from the square calculation unit 102 and the data output as shown in Equation 4 described above in the multi-part calculation unit 103 as shown in FIG. 6. In addition, the resultant signal is output.
That is, as shown in Figure 6, the adder 104 is 0, sq8, sq6, sq4, sq2, sq0 and the multi-part calculation unit 103 output as in Equation 3 from the square calculation unit 102 M9, m8, m7, m6, m5, m4, m3, m2, 0, 0 and c9, c8, c7, c6, c5, c5, c4, c3, c2, Outputs c1 and c0.
In addition, according to this, the adder 104 outputs the data output as shown in Equation 3 from the square calculation unit 102 and the last two pieces of data output as shown in Equation 4 described above in the multi-part calculation unit 103. Since it is not necessary to add bits, the result signal is added as shown in FIG. 6 even though the result signal is added as shown in FIG.
That is, as shown in FIG. 7, the adder 104 is configured to output the 0, sq8, sq6, sq4, sq2 and the multi-part calculator 103 output as in Equation 3 from the square calculator 102. Calculate the square after calculating c9, c8, c7, c6, c5, c5, c4, c3, c2 by adding m9, m8, m7, m6, m5, m4, m3, and m2 output as shown in Equation 4 above. The unit 102 outputs c9, c8, c7, c6, c5, c5, c4, c3, c2, 0, sq0 as shown in FIG. 6 by adding 0 and sq0 output as shown in Equation 3 above.
Since the operation state in the selector 105 is the same as the above-described process, description thereof will be omitted.
As described above, in the squarer according to the present invention, there is an effect of reducing the gate number of at least 50 to 60% than simply squared using a multiplier.

权利要求:
Claims (1)
[1" claim-type="Currently amended] An absolute value calculating section which takes an absolute value in the input data;
A square calculator which multiplies its own value for each bit output from the absolute value calculator and calculates a result value;
A multi-part calculator for multiplying different bits output from the absolute value calculator and calculating a result value;
An adder for adding a value output from the square calculator and a value output from the multi-part calculator;
And a selector for outputting a value output from the adder or a preset value according to the signal output from the absolute value calculator.

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同族专利:

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公开号 | 公开日

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KR100525378B1|2005-11-02|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1999-03-11|Application filed by 구자홍, 엘지전자 주식회사

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1999-03-11|Priority to KR10-1999-0008134A

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2000-10-16|Publication of KR20000060086A

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2005-11-02|Application granted

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2005-11-02|Publication of KR100525378B1

优先权:

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申请号 | 申请日 | 专利标题

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KR10-1999-0008134A|KR100525378B1|1999-03-11|1999-03-11|square device|