• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A device for a multi-protocol function of an exchange is provided to simultaneously receive a V5.2 protocol, an integrated services digital network(ISDN) primary rate access(PRI) protocol and a frame protocol in the exchange to process the multi-protocol in one hardware system. CONSTITUTION: An exchange has a mutual connector, a multi-protocol processor and a subscriber interface. The multi-protocol processor is comprised as follows. An address translator(24) approaches each block without errors by translating addresses of blocks selected by the CPU. An internal time sharing switch(25) switches a channel processing a protocol of each E1 frame to the CPU, and transceives a voice channel to/from the external time sharing switch interface, by switching each E1 frame of the first/fourth E1 framer and line interface. A multi-channel HDLC processor(26) extracts or mixes a channel processing a HDLC protocol in each E1 frame, to transmit to the CPU. An external time sharing switch interface(27) supplies a clock and a frame synchronous signal to the internal time sharing switch, the first/fourth E1 framer and line interface by receiving the signal from the external time sharing switch, and interfaces the external time sharing switch, each E1 trunk and the voice channel. A first/fourth E1 framer and line interface(28,31) generate an E1 frame, divide a received frame, and transmit into a dipole signal level for remote transmission with an E1 link. The multi-protocol processor is further comprised of a CPU(21), a clock generating circuit(22) and a memory(23).
    公开号:KR20000059397A
    申请号:KR1019990006961
    申请日:1999-03-03
    公开日:2000-10-05
    发明作者:백현수；김길용；노재웅
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Apparatus for capability of multi protocol in exchange}
    The present invention relates to a protocol function device of an exchange, and more particularly, to a V5.2 protocol, an ISDN (Integrated Services Digital Network) PRI (Primary Rate Access Interface, Primary Group Speed Interface, 2.048Mbps) protocol, It relates to a multi-protocol functional device of an exchange that simultaneously accepts 7 protocols, frame relay protocols.
    Fig. 1 is a schematic configuration diagram of a conventional exchange, and conventionally, there was hardware for each protocol to process the V5.2 protocol, ISDN PRI protocol, No.7 protocol, and frame relay protocol.
    Here, the protocol is largely composed of three layers, where layer 1 means a relay line, layer 2 is a data link based on HDLC (High-level Data Link Control), and layer 3 Means network.
    So to handle each protocol, the interconnect subsystem (1), No.7 protocol function subsystem (2), ISDN PRI protocol function subsystem (3), V5.2 protocol function subsystem (4), frame relay protocol A functional subsystem 5, an E1 physical layer functional subsystem 6, and a subscriber matching function subsystem 7 were needed.
    However, there is no conventional embodiment of the V5.2 protocol and the frame relay protocol, and the No.7 protocol receives the signal message from the relay line and processes only the No.7 signal message via the time switch, the space switch, and the time switch inside the exchange. In order to transmit a signal message to the exchange of power, the device performs an operation in the opposite direction to the reception.
    In the ISDN primary group speed protocol processing, layer 1 is received through a relay line hardware device and delivered to different hardware devices. In hardware that processes only layer 2 protocol, layer 1 is transferred to layer 3 after protocol processing. To send an ISDN primary group speed protocol message, send in the opposite direction of the above path.
    As such, the conventional exchanger has a disadvantage in that it cannot handle No. 7, ISDN, V5.2, and frame relay protocols in one hardware system.
    Therefore, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is a switch that can simultaneously accommodate the V5.2 protocol, ISDN PRI protocol, No.7 protocol, frame relay protocol in the exchange. To provide a multi-protocol functional device.
    In order to achieve the above object, a multi-protocol functional device of an exchange according to the present invention,
    An interconnecting unit connected to the multiprotocol processing unit and the subscriber matching unit to match the subscriber to the multiprotocol; A multi-protocol processor connected to the interconnect to perform an E1 physical layer, No. 7, V5.2, ISDN PRI, and frame relay functions; It is characterized in that the technical configuration consists of a subscriber matching unit that performs an interface between the interconnection and the subscriber to match the subscriber to use a multi-protocol function.
    1 is a schematic configuration diagram of a conventional exchanger,
    Figure 2 is a table showing the functions of No. 7, ISDN, V5.2, frame relay protocol in the general physical layer,
    3 is a schematic structural diagram of a multi-protocol functional apparatus of an exchange according to the present invention;
    4 is a block diagram illustrating a multi-protocol processor of the exchange in FIG.
    <Explanation of symbols for main parts of drawing>
    10: interconnection unit 20: multi-protocol processing unit
    21: central processing unit 22: clock generation circuit
    23: memory unit 24: address translation unit
    25: internal time division switching unit 26: multi-channel HDLC processing unit
    27: external time division switch matching unit 28 to 31: E1 framer and line matching unit
    40: subscriber matching unit
    Hereinafter, with reference to the accompanying drawings an embodiment according to the technical idea of the multi-protocol functional device of the present invention as described above in detail as follows.
    The present invention implements the software to implement the hardware that can support all the hardware that can be slightly different when implementing the hardware that can support the four protocols, and then to implement the software to selectively use only the hardware resources required to perform each protocol do.
    FIG. 2 is a table illustrating the functions of No. 7, ISDN, V5.2, and frame relay protocols in a general physical layer, and the four protocols are described below.
    In case of No.7 protocol, 16 channels are basically used and the 1st to 31st can be selected.In case of ISDN PRI protocol, only the 16th channel of each E1 physical layer is used.In case of V5.2 protocol, The 15th, 16th, and 31st channels of each E1 physical layer can be used.In the case of the frame relay protocol, 31 64Kbps can be used for each channel of each E1, or 6 channels can be bundled into one unit. It is possible to combine the channels into one unit.
    3 is a schematic structural diagram of a multi-protocol functional apparatus of an exchange according to the present invention.
    As shown therein, the interconnection unit 10 is connected to the multi-protocol processing unit 20 and the subscriber matching unit 40 so as to match the subscriber to the multi-protocol; A multi-protocol processor 20 connected to the interconnect 10 to perform an E1 physical layer, No. 7, V5.2, ISDN PRI, and frame relay functions; It consists of a subscriber matching unit 40 which performs an interface between the interconnection unit 10 and the subscriber so that the subscriber can use the multi-protocol function.
    4 is a block diagram illustrating a multi-protocol processor of the exchange in FIG.
    As shown therein, a central processing unit 21 for controlling program execution of the multi-protocol processor 20 and controlling interrupts when accessing each block therein or when an interrupt occurs in each block; A clock generation circuit section 22 for supplying a clock to the central processing unit section 21; A memory unit 23 for storing data of the multi-protocol processor 20; An address translation unit 24 for translating the addresses of the blocks to be accessed by the CPU 21 to access each block without errors; Each E1 frame of the first to fourth E1 framers and circuit matching units 28 to 31 is switched to switch the channel to process the protocol of each E1 frame to the CPU 21, and external to the voice channel. An internal time division switch unit 25 for transmitting / receiving the time division switch matching unit; A multi-channel HDLC processor 26 which extracts or synthesizes a channel to process the HDLC protocol in each E1 frame of the internal time division switch unit 25 and transmits the channel to the central processing unit 21; Receiving a frame synchronizing signal from an external time division switch and supplying a clock and frame synchronizing signal to the internal time division switch unit 25 and the first to fourth E1 framers and line matching units 28 to 31; An external time division switch matching section 27 matching for each E1 relay line and voice channel; And first to fourth E1 framers and line matching units 28 to 31 for generating an E1 frame, dividing the received frame, and transmitting at a bipolar signal level to enable long distance transmission over the E1 link.
    Thus, the central processing unit 21 may use Motorola's 32-bit MC68MH360, which is used to control the interrupt when the program is executed and each resource is accessed or when an interrupt occurs at each resource.
    In addition, the clock generation circuit 22 supplies a clock of 32.384Mhz to the central processing unit 21 so that the central processing unit 21 can access each resource. The time division switch may be used when the central processing unit unit 21 approaches the internal time division switch unit 25 by supplying to (25), or the internal time division switch may be used during internal operation, and the external time division switch may be used in the external time division switch matching unit 27. It receives the clock of 4.096Mhz and frame synchronization of 8Khz received from the E1 framer and circuit matching unit (28 to 31). With this clock and frame synchronization signal, the E1 framer and line matching units 28 to 31 are used to transmit and receive the E1 frame.
    In addition, the memory unit 23 is largely divided into four types. The first is ROM (Read Only Memory), which is 256Kbytes in size, contains codes of various programs to be executed, and the second is local memory, which is a debug program data that can check whether there are any hardware resources. Can be located, and the third one has a dual port memory. The dual port memory has a dual port memory as a method for communication since the communication is performed in the same hardware as the layer 1 and the layer 2 when the protocol is executed, and the communication between the layer 2 and the layer 3 is performed in different hardware. Fourth, shared memory is the area of buffer memory and memory for program and data of actual protocol for communication between layer 1 and layer 2.
    In addition, the address translation unit 24 when the central processing unit 21 tries to access each memory unit 23 or when the internal time division switch 25 is approached or when the first to fourth E1 framers and line matching units ( 28 ~ 31) When you want to access the translation of the corresponding address by translating each resource without error.
    In addition, the internal time division switch section 25 switches each of the E1 frames of the E1 framers and the line matching sections 28 to 31 and the highways of the external time division switch matching sections 27, and processes the HDLC protocol within each E1 frame. Extract or synthesize the function. The channel to process the protocol of each E1 frame is switched to the time division multiple (TDM) port of the MC68MH360, which is the central processing unit, through the internal time division switch 25, and is transmitted / received to the external time division switch for the voice channel.
    In addition, the external time division switch matching unit 27 plays two roles. Firstly, the clock and frame synchronization signals are supplied to the internal time division switch unit 25, the E1 framer and the circuit matching unit 28 to 31 by receiving the clock signal of 4.096Mhz and the frame synchronization signal of 8Khz from the external time division switch and the external. It is responsible for time division switch and matching for each E1 relay line and voice channel.
    In addition, the first to fourth E1 framers and line matching units 28 to 31 are used to generate an E1 frame or to divide the received frame, and transmit the E1 link at a bipolar signal level so as to transmit a long distance.
    The difference between the MC68MH360 and the MC67360 here depends on whether the HDLC controller in the central processing unit 21 can be used based on time division. The MC68MH360 has 64 HDLC controllers in total, and there are 32 channels in the E1 physical layer. Therefore, to use HDLC controller for each channel, MC68MH360 should be used. With the MC68360, there are only four HDLC controllers, so the HDLC controller functionality for 32 of the E1s cannot be fully provided.
    Therefore, to support the ISDN PRI protocol first, an HDLC controller that supports up to four E1s in hardware and supports only 16 channels of each E1 is required on the protocol. Four E1s are input / output to the internal time division switch section 25, and the MC68MH360 requires transmission and reception lines. Therefore, to transmit ISDN PRI protocol data on the E1 line, first control the internal time division switch unit 25 so that the first channel output from the MC68MH360 is the 16th channel of the first E1 and the second channel is the 16th channel of the second E1. The internal time division switch unit 25 is initialized to switch to. On the contrary, inputting the 16th channel of each E1 into the MC68MH360 is the opposite of transmitting to the above E1.
    In this case, when the MC68MH360 is initialized so that the actual data at the time of transmission and reception is written to the shared memory, the address of the shared memory is stored in a register called a buffer descriptor of the HDLC controller of the MC68MH360 so that the actual protocol data can be transmitted and received. .
    Secondly, the V5.2 protocol is very similar to the ISDN PRI protocol, but there are more channels available than the ISDN PRI protocol. Therefore, to use as V5.2 protocol, each E1 16th channel is the same as ISDN PRI, and protocol data of 15th and 31st channel additionally used in V5.2 protocol are as follows.
    First, the fifth channel of the time division port of the MC68MH360 is switched to the 15th channel of the first E1 in the internal time division switch unit 25, the sixth channel is the 15th channel of the second E1, and the seventh channel is the third The MC68MH360 allows the MC68MH360 to switch to the 15th channel, the 8th channel to the 15th channel of the fourth E1, the 9th channel to the 31st channel of the first E1, and the 10th channel to the 31st channel of the second channel. The internal time division switch unit 25 is controlled when it is initialized.
    Using three channels for each E1 is characteristic of the physical layer of the V5.2 protocol. Therefore, since there are four E1s per board, the MC68MH360's time-sharing port uses up to 12 multichannel HDLC processors 26. do. The data received by E1 of the V5.2 protocol has the opposite effect of the case of transmission.
    Third, the No.7 protocol requires higher performance to use many channels, so only four channels per board are used to handle the number of processes that the 32-bit MC68MH360 can handle. In ISDN PRI or V5.2 protocol, fixed channel is used. In case of No.7 protocol, it is required by software to receive E1 and channel number from software and control the internal time division switch for maximum 4 It is possible to provide No.7 protocol by allowing only two channels to be used.
    Finally, in the case of the frame relay protocol, each channel of each E1 can be used as a data channel, and data can be transmitted in one unit or six channels in one unit. In the case of the frame relay protocol, the MC68MH360 is merely used to execute a program, and in practice, protocol data is transmitted and received by the multichannel HDLC processor 26 to communicate with the shared memory.
    As such, the present invention is to simultaneously accommodate the V5.2 protocol, ISDN PRI protocol, No.7 protocol, frame relay protocol in the exchange.
    Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.
    As described above, the multi-protocol functional device of the exchange according to the present invention can be equipped with four protocols of the V5.2 protocol, the ISDN PRI protocol, the No.7 protocol, and the frame relay protocol in the same hardware. By implementing the hardware, in the system aspect, each different hardware is installed in the subsystem for each protocol. For example, to support the No.7 protocol, a dedicated subsystem that processes only the No.7 protocol is required, and only the E1 physical layer is used. You need a subsystem to process. The ISDN PRI protocol also requires a separate subsystem to handle only another ISDN PRI protocol. In this way, the E1 physical layer can be accommodated in one hardware and four protocols can be accommodated. Therefore, the cost of the system is superior in terms of competitiveness because only one subsystem can handle the functions required by the five subsystems. do. In addition, since four hardware protocols can be supported in one hardware, it requires less R & D manpower and lower development cost than when implemented in different hardware. In addition, in terms of productivity, when implementing different hardware, at least four types of hardware should be produced when producing, but in the case of the present invention, it is possible to produce only one, which is inexpensive and lowers the production cost.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] In the exchanger,
    An interconnecting unit connected to the multiprotocol processing unit and the subscriber matching unit to match the subscriber to the multiprotocol;
    Multiple protocols connected to the interconnection unit to perform E1 physical layer, No.7, V5.2, Integrated Services Digital Network (ISDN), Primary Rate Access Interface (PRI), Frame Relay function A processing unit;
    And a subscriber matching unit configured to perform an interface between the interconnection unit and the subscriber so as to match the subscriber so as to use the multi-protocol function.
    [2" claim-type="Currently amended] The method of claim 1, wherein the multi-protocol processor,
    A central processing unit that controls program execution of the multi-protocol processing unit and controls an interrupt when an internal block is accessed or an interrupt occurs in each block;
    A clock generation circuit unit for supplying a clock to the central processing unit;
    A memory unit for storing data of the multi-protocol processor;
    An address translation unit for translating the addresses of blocks to be accessed by the central processing unit to access each block without error;
    Switching each E1 frame of the first to fourth E1 framer and line matching unit to switch the channel to process the protocol of each E1 frame to the central processing unit, and transmits / receives with the external time division switch matching unit for the voice channel. An internal time division switch unit;
    A multi-channel HDLC processor which extracts or synthesizes a channel to process the HDLC protocol in each E1 frame of the internal time division switch unit and transmits the channel to the central processing unit;
    Receives a frame synchronization signal from an external time division switch, and supplies a clock and frame synchronization signal to the internal time division switch unit, the first to fourth E1 framers, and a line matching unit, and provides an external time division switch, each E1 relay line, and a voice channel. An external time division switch matching unit for matching;
    And a first to fourth E1 framers and a circuit matcher for generating an E1 frame, dividing a received frame, and transmitting at a bipolar signal level to enable long-distance transmission over the E1 link.
    [3" claim-type="Currently amended] The method of claim 2, wherein the central processing unit unit,
    In order to perform the ISDN PRI protocol, an HDLC controller supporting up to four E1s and supporting 16 channels of each E1 on the protocol is provided, and the four E1s are provided to be input / output to the internal time division switch unit and then E1 times. In order to transmit ISDN PRI protocol data on the line, the internal time division switch unit is controlled so that the first channel output from the central processing unit unit is the 16th channel of the first E1, and the second channel is the 16th channel of the second E1. Initializing the internal time division switch unit to switch, and controlling the actual data at the time of transmission and reception to be written to the shared memory area of the memory unit (23).
    [4" claim-type="Currently amended] The method of claim 2, wherein the central processing unit unit,
    In order to execute the V5.2 protocol, the internal time division switch unit is controlled so that the first channel output from the CPU unit is the 16th channel of the first E1, and the second channel is the 16th channel of the second E1. , The fifth channel is the fifteenth of the first E1, the sixth channel is the fifteenth channel of the second E1, the seventh channel is the third fifteenth channel, and the eighth channel is the fifteenth of the fourth E1. And the ninth channel is the 31st channel of the first E1 and the 10th channel is controlled to switch the internal time division switching unit to the 31st channel of the second channel.
    [5" claim-type="Currently amended] The method of claim 2, wherein the central processing unit unit,
    In order to execute the No.7 protocol, the multi-protocol protocol of the switch is controlled to use the maximum of four channels by controlling the internal time-division switch by receiving the E1 and the channel number to be used at the request of the software from the software. Function device.
    [6" claim-type="Currently amended] The method of claim 2, wherein the central processing unit unit,
    In order to perform the frame relay protocol, each channel of each E1 is used as a data channel, and the multi-protocol functional apparatus of the exchange, characterized in that the control is performed so that data transmission and reception are performed in one unit of 6 or 31 channels.
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    同族专利:
    公开号 | 公开日
    JP2000261519A|2000-09-22|
    KR100300843B1|2001-09-26|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-03-03|Application filed by 김영환, 현대전자산업 주식회사
    1999-03-03|Priority to KR1019990006961A
    2000-10-05|Publication of KR20000059397A
    2001-09-26|Application granted
    2001-09-26|Publication of KR100300843B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019990006961A|KR100300843B1|1999-03-03|1999-03-03|Apparatus for capability of multi protocol in exchanger|
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