• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The output drive circuitry provides logic level control and waveforms for high speed data communication in synchronous memory, such as dynamic random access memory (DRAM). Level adjustment is obtained by resistance distribution between the termination resistor and the adjustable impedance between the output node and the VDD and VSS power supplies. The waveform function includes changing the slew rate of the signal at the output node by sequentially turning on or off the output transistor in response to a change in the input signal. The weighting of the different configurations of the output transistors results in different waveform characteristics of the output signal.
    公开号:KR20000057264A
    申请号:KR1019990704654
    申请日:1997-11-26
    公开日:2000-09-15
    发明作者:키이쓰브렌트
    申请人:린치 마이클 엘.；마이크론 테크놀로지 인코포레이티드；
    IPC主号:
    专利说明:

    Adjustable output driver circuit
    Integrated circuits typically include a plurality of input / output pins used with additional circuitry for communication. For example, integrated memory devices, such as dynamic random access memory (DRAM), include control inputs that receive memory operation control signals and data pins for bidirectional data communication with external systems or processors.
    Data transfer rates in modern integrated circuits are primarily limited by the internal circuit operating speed. Communication networks transmit signals between circuits at speeds faster than the capacity of any integrated circuit. To address the need for faster circuits, a group of integrated circuits may be combined on a common bus. In this configuration, each integrated circuit operates in a coordinated manner with other integrated circuits to share data transmitted at high speed. For example, a group of memory devices, such as DRAM, static RAM, or read only memory (ROM), may be connected to a common data bus. The data rate of the bus is substantially faster than the executable speed of the individual memory. Therefore, each memory is operated so that one memory processes the received data, while the other memory receives new data. By providing an adequate number of memory devices and an efficient control system, very high speed data transfer can be achieved.
    As the transmission rate of data communication signals continues to increase, new circuits and methods are required to transmit data accurately from each integrated circuit. One proposed solution is the bus driver disclosed in US Pat. No. 5,254,883. This bus driver circuit is a parallel output transistor that couples the bus to a power supply. Output transistors are manufactured in different sizes and are selectively operated to control bus current. This method relates to accurate bus current control for forming the bus voltage at the correct logic voltage level. However, this method lacks control during the change of bus voltage between logic voltage levels.
    For this reason, there is a need for a high speed output driver that is fully adjustable and provides control of changes in bus voltage between logic voltage levels.
    BACKGROUND OF THE INVENTION The present invention generally relates to integrated circuits, and more particularly to data output drivers for high speed data transfer.
    1 is a schematic diagram illustrating one embodiment of the invention and the environment used;
    FIG. 2 is a schematic diagram illustrating one embodiment of the output driving circuit of FIG. 1 in detail. FIG.
    FIG. 3 is a schematic diagram illustrating the waveform control circuit of FIG. 2 in detail. FIG.
    4 is a schematic diagram illustrating an embodiment of each sequence circuit of FIG. 3 in detail.
    FIG. 5 is a schematic diagram illustrating another embodiment of each sequence circuit of FIG. 3 in detail. FIG.
    6 is a graph showing the voltage versus time waveform relationship of the output driving circuit of FIG.
    7 is a graph showing the voltage versus time waveform relationship of voltage DQ at the output node of the output drive circuit of FIG. 2 to voltage DQ 'at the output node of a typical output drive circuit.
    8 is a graph of a waveform similar to FIG. 7 resulting in a first non-uniform weight of the output transistor.
    9 is a graph of a waveform similar to FIG. 7 resulting in a second non-uniform weight of the output transistor.
    10 is a schematic diagram illustrating another embodiment of an output driving circuit in which the first and second impedances are not included.
    11 is a graph illustrating another embodiment of an output drive circuit for setting single-ended waveforms and binary high logic voltage levels.
    12 is a schematic diagram illustrating another embodiment of an output drive circuit for setting single-ended waveforms and binary low logic voltage levels.
    The present invention provides an output drive circuit capable of adjusting the waveform and level of the output voltage signal. The first plurality of output transistors electrically couple and disconnect the output mode to the first power supply. The control circuit is coupled to the control terminal of each output transistor in the first plurality of output transistors. The control circuit turns on and off output transistors in the first plurality of output transistors in response to the change in the first input signal received by the control circuit.
    In one embodiment, the output drive circuit includes a first impedance provided between the first plurality of output transistors and the first power supply. The second plurality of output transistors electrically couples or disconnects the output nodes to the second power supply. The control circuit is coupled to the control terminal of each output transistor in the second plurality of output transistors. The control circuit turns each of the second plurality of output transistors on or off in response to a change in the second input signal received by the control circuit. The output drive circuit includes a second impedance provided between the first plurality of output transistors and the first power supply.
    The present invention includes a method and apparatus for forming a waveform of a signal comprising a logic voltage level and a slew rate of voltage change therebetween. The present invention is particularly useful for high speed data transfers such as in synchronous memory including dynamic random access memory (DRAM).
    In the description of the preferred embodiments, reference is made to the accompanying drawings, which form a part thereof, and are shown by the description of certain preferred embodiments, which practice the invention. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention, and it will be understood that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made without departing from the spirit and scope of the invention. . The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
    1 is a view for explaining an embodiment of the present invention and the environment in which the embodiment is used. In Fig. 1, the memory array 90 includes a memory cell and a readout circuit for reading data stored in the memory cell. The output drive circuit 100 receives the data read from the memory array 90 as a first input signal D at node 110 and its binary complement as a second input signal at node 120 and at output signal DQ at node 130. Provide in response. The output node 130 is electrically coupled to the receiving node 140 via the data communication line 150 and includes distributed interconnects, pads, and other resistors and capacitances that turn the integrated circuit chip on and off. Output node 130 is electrically coupled to termination supply voltage V term at termination node 160 via resistor 170. First and second power supply voltages, such as V DD at node 180 and V SS at node 190, are provided to output drive circuit 100. V term is the voltage approximately midway between V DD and V SS .
    2 is a schematic diagram illustrating one embodiment of an output driving circuit 100 in detail. In FIG. 2, a first plurality of output transistors 200, such as PFETs 200A-C, have drain terminals coupled together to output node 130. The waveform control circuit 202 supplies a separate control terminal signal to each gate terminal of the PFETs 200A-C at nodes 205A-C. The source terminals of PFETs 200A-C are coupled together to V DD through a first impedance 210.
    In one embodiment, the first impedance 210 is an active device such as PFETs 200A-C having a drain terminal coupled together to a source terminal at each node 220 of the PFETs 200A-C in the first plurality of output transistors 200. It includes. PFETs 200A-C have a source terminal coupled together to V DD at node 180. V OH level control circuit 212 is node 215A-C at each gate terminal of PFETs 200A-C to programmatically control first impedance 210 depending on how much change and which of PFETs 200A-C is turned on. Supplies a separate control terminal signal. PFETs 200A-C that are turned on contribute to the effective value of the impedance between V DD at nodes 220 and 180. PFETs 200A-C include a plurality of other examples of paralleled PFETs having the same width / length aspect ratio, or by varying which of the PFETs 200A-C is turned on to change the impedance between V DD at node 180 and node 220. It may be designed to optimize the effective value.
    Impedance 210 forms a resistor divider with termination resistor 170, the impedance value of which determines the binary high logic voltage level V OH at output node 130. The V OH level control circuit 212 controls the value of the impedance 210 and then the value of V OH by controlling which of the PFETs 200A-C is turned on.
    The second plurality of output transistors 250, such as NFETs 250A-C, have drain terminals coupled together to output node 130. The waveform control circuit 202 supplies a separate control terminal signal to each gate terminal of the NFETs 250A-C at nodes 255A-C. The source terminals of the NFETs 250A-C are coupled together to V SS through a second impedance 260.
    In one embodiment, the second impedance 260 is active, such as NFETs 260A-C, having a drain terminal coupled together to a source terminal at each node 270 of the NFETs 250A-C of the second plurality of output transistors 250. Device. NFETs 260A-C have a source terminal coupled together to V SS at node 190. V OL level control circuitry 272 is separate at each gate terminal of NFETs 260A-C at node 275A-C to programmatically control impedance 260 depending on how much change and which of NFETs 260A-C is turned on. Supply the control terminal signal. PEFTs 260A-C that are turned on contribute to the effective impedance between V SS at node 190 and node 270. PFETs 260A-C include a number of other examples of paralleled PFETs having the same width / length aspect ratio, or by changing the turned on of PFETs 260A-C, the impedance of V DD at node 190 and node 270 It may be designed to optimize the effective value.
    Impedance 260 forms a resistor divider with termination resistor 170, the impedance value of which determines the binary high logic voltage level V OL at output node 130. The V OL level control circuit 272 controls the value of the impedance 260 and then controls the value of V OL by controlling which of the PFETs 260A-C is turned on.
    In the above description, the first plurality of output transistors 200, the second plurality of output transistors 250, the first impedance 210, and the second impedance 260 are three field effect transistors for clarity of explanation. Each has been described as including. However, the exact number of transistors can be selected according to individual configuration limitations without departing from the spirit and scope of the present invention.
    3 is a schematic diagram illustrating the waveform control circuit 202 in detail. The waveform control circuit 202 includes a sequence circuit 300A-B that receives the first and second input signals D and DN at an input terminal 305 electrically coupled to nodes 110 and 120, respectively. The sequence circuits 300A-B respectively provide sequentially time-delayed control terminal signals at the output terminals 310A-C that are electrically coupled to each node 205A-C and 255A-C. This sequentially time-delayed control terminal signal couples the output node 130 to V SS at node 190 and V DD at node 180 through the output transistors of first plurality 200 and second plurality 250. As described below, by providing the control transistor signals with time delays sequentially to the output transistors, the sequence circuits 300A-B provide control according to the slew rate of the voltage at the output node 130, where the slew rate control is respectively controlled. It is independent of the V OH and V OL level control provided by the first and second impedances 210, 216.
    4 is a schematic diagram illustrating one embodiment of each of the sequence circuits 300A-B. 4 includes a series of series cascaded inverters 400A-F for receiving an input signal at input terminal 305 and providing a plurality of sequentially delayed signals at output terminals 310A-C in response thereto. . In this embodiment, the delay between the change in the signal at the input terminal 305 and the change in the signal at each output terminal 310A-C corresponds to the corresponding number, including the wiring capacitance and the load capacitance of the inverter and the output transistor. Is determined by the delay of the inverter.
    5 is a schematic diagram illustrating in detail each other embodiment of the sequence circuit 300A-B. 5 includes a series cascaded inverter 500A-F pair. Each pair of inverters such as 500A-B, 500C-D and 500E-F receives an input signal at input terminal 305 and supplies a sequentially delayed signal in response to it at each output terminal 310A-C. Each pair of inverters such as 500A-B, 500C-D, 500E-F has a capacitance equal to each capacitance 505A-C provided between them. Capacitance 505A-C is used, such as by a fuse or other programmable element, to tailor the delay between the change in signal at input terminal 305 and the change in signal at each output terminal 310A-C. It can be adjusted in order.
    6 is a graph illustrating the voltage versus time waveform relationship of the output drive circuit 100. In Figure 6, signal A represents the voltage waveforms at nodes 205A and 255A, signal B represents the voltage waveforms at nodes 205B and 255B, signal C represents the voltage waveforms at nodes 205 and 255C, and signal DQ represents the node. The voltage waveform at 130 is shown. Therefore, FIG. 6 illustrates slew rate tailoring of the change in the DQ signal in response to the sequentially delayed control terminal signal provided by the waveform control circuit 202. 6 also illustrates the reduced signal swing provided by impedances 210 and 260, i.e., V OH and V OL voltage levels in combination with termination resistor 170. FIG. Providing an odd number of output transistors in each of the first plurality 200 and the second plurality 250 output transistors can avoid the congestion of the signal DQ at the V term voltage.
    FIG. 7 is a graph illustrating the voltage versus time waveform of voltage DQ at output node 130 of output drive circuit 100 relative to voltage DQ 'of a conventional output drive circuit without the slew rate waveform provided by the present invention. As can be seen in FIG. 7, the slew rate of the voltage change of the voltage DQ according to the output drive circuit 100 of the present invention is more precisely controlled than the slew rate of the voltage change of the voltage DQ 'according to the conventional output drive circuit. Can be.
    7 illustrates a case where each output transistor in the first plurality 200 and the second plurality 250 is equally weighted, and the effective width / length aspect ratio is substantially the same. As can be seen in Figure 7, this results in a nearly linear slew rate waveform.
    FIG. 8 is a graph similar to that of FIG. 7, in which output transistors in the output transistors of the first plurality 200 and the second plurality 250 are not equally weighted. 8 illustrates a case where an intermediate transistor such as 200B and 250B has an effective width / length aspect ratio that is greater than the effective width / length aspect ratio of the termination transistors such as 200A, 200C, 250A and 250C. In this embodiment, the slew rate of voltage DQ at output node 130 is faster than near the midpoint between V OH and V OL levels.
    FIG. 9 is a graph similar to FIG. 7, in which the transistors in the first plurality 200 and the second plurality of output transistors are not equally weighted. 9 illustrates a case where an intermediate transistor such as 200B and 250B has an effective width / length aspect ratio smaller than the effective width / length aspect ratio of the termination transistors such as 200A, 200C, 250A and 250C. In this embodiment, the slew rate of voltage DQ at output node 130 is faster than near the midpoint between V OH and V OL levels.
    7-9 illustrate different methods of weighting each output transistor of the first plurality 200 and the second plurality 250 output transistors. The first plurality of output transistors 200 may be weighted differently from the second plurality of output transistors 250. Many combinations are possible to obtain the desired waveform of voltage DQ at output node 130.
    10 is a schematic diagram illustrating another embodiment of the output drive circuit 100. In FIG. 8, the first and second impedances 210, 260 and corresponding V OH and V OL level control circuits 212, 272 are not shown. This embodiment provides another waveform of slew rate and change in voltage DQ at output node 130 but does not adjust the V OH and V OL output levels by controlling the impedance.
    11 is a schematic diagram illustrating another single ended embodiment of the output drive circuit 100. In FIG. 11, the second plurality of output transistors 250 and the second impedance 260 are not shown. This embodiment provides slew rate and V OH level control of the voltage DQ at the output node 130, wherein the V OL level is formed at the V term by a resistor connection through the termination resistor 170 to the termination voltage at node 160. .
    12 is a schematic diagram illustrating another single end embodiment of the output drive circuit 100. In FIG. 12, the first plurality of output transistors 200 and the first impedance 210 are not shown. This embodiment provides slew rate and V OL level control of voltage DQ at output node 130, where the V OH level is formed at V term by a resistor connection through termination resistor 170 to the termination voltage at node 160. .
    The present invention therefore encompasses a signal waveform method and apparatus comprising a logic voltage level and a slew rate of voltage change between two levels. The present invention is particularly useful for high speed data communications such as in synchronous memory including dynamic random access memory (DRAM).
    While particular embodiments have been shown and described, it will be appreciated by those skilled in the art that any device calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any combinations, applications, or variations of the present invention. Therefore, it will be apparent that the invention is limited only by the claims.
    权利要求:
    Claims (18)
    [1" claim-type="Currently amended] A first plurality of output transistors electrically coupling the output node to the first power source, each having a control terminal;
    A control terminal of each output transistor in the first plurality of output transistors for sequentially turning on or off the output transistors in the first plurality of output transistors in response to a change in the first input signal received by the control circuit An output drive circuit comprising a control circuit coupled to.
    [2" claim-type="Currently amended] The method of claim 1,
    And a first impedance provided between the first plurality of output transistors and the first power supply.
    [3" claim-type="Currently amended] The method of claim 1,
    Further comprising a second plurality of output transistors electrically coupling the output node to a second power source,
    The control circuit may be configured to sequentially turn on or turn off each output transistor in the second plurality of output transistors in response to a change in the second input signal received by the control circuit. An output drive circuit coupled to the control terminal of each output transistor.
    [4" claim-type="Currently amended] The method of claim 3, wherein
    And a second impedance provided between the first plurality of output transistors and the first power supply.
    [5" claim-type="Currently amended] A first plurality of output transistors electrically coupling an output node resistively terminated to an end node (the voltage is constant at the end node) to a first power source;
    A second plurality of output transistors electrically coupling the output node to a second power source;
    The first and second plurality to sequentially turn on or turn off each output transistor in the first and second plurality of output transistors in response to each change in the first and second input signals received by the control circuit. And a control circuit coupled to a control terminal of each output transistor in the output transistor of the integrated circuit output driving circuit.
    [6" claim-type="Currently amended] The method of claim 5,
    A first impedance provided between said first plurality of output transistors and a first power source,
    And a second impedance provided between the second plurality of output transistors and a second power supply.
    [7" claim-type="Currently amended] The method of claim 6,
    Each of the first and second impedances comprises a plurality of transistors providing an adjustable impedance.
    [8" claim-type="Currently amended] The method of claim 6,
    Each of the first and second impedances comprises a plurality of transistors providing a programmable adjustable impedance.
    [9" claim-type="Currently amended] The method of claim 5,
    And said control circuit comprises a series of first series connected inverters for providing a sequence signal at each control terminal of said first plurality of output transistors in response to said first input signal.
    [10" claim-type="Currently amended] The method of claim 5,
    And said control circuit comprises a series of second series connected inverters for providing a sequence signal at each control terminal of said second plurality of output transistors in response to said second input signal.
    [11" claim-type="Currently amended] The method of claim 5,
    And the control circuit comprises a delay element circuit for providing a sequence signal at each control terminal of the first plurality of output transistors in response to the first input signal.
    [12" claim-type="Currently amended] The method of claim 11,
    And the delay element circuit provides an adjustable delayed sequence signal.
    [13" claim-type="Currently amended] The method of claim 5,
    And the control circuit comprises a delay element circuit for providing a sequence signal at each control terminal of the second plurality of output transistors in response to the second input signal.
    [14" claim-type="Currently amended] The method of claim 13,
    And the delay element circuit provides an adjustable delayed sequence signal.
    [15" claim-type="Currently amended] A method of providing an output data signal at an output node, the method comprising:
    Receiving a first input signal at a control circuit;
    Electrically coupling or disconnecting the output node to a first power source sequentially through a first plurality of output transistors in response to the first input signal.
    [16" claim-type="Currently amended] The method of claim 15,
    Receiving a second input signal at a control circuit;
    Electrically coupling or disconnecting the output node to a second power source sequentially through a second plurality of output transistors in response to the second input signal.
    [17" claim-type="Currently amended] The method of claim 16,
    Forming a first impedance provided between said output node and a first power source to obtain a first steady state output voltage level;
    Forming a second impedance provided between the output node and a second power source to obtain a second steady state output voltage level.
    [18" claim-type="Currently amended] A memory cell array for storing data received on a data communication line;
    18. A synchronous memory device having an output node electrically coupled to the data communication line and including an output drive circuit for providing data read from the memory cell array.
    The output drive circuit,
    A first plurality of output transistors electrically coupling an output node resistively terminated to an end node at a constant termination voltage to a first power source;
    A second plurality of output transistors electrically coupling the output node to a second power source;
    The first and second plurality to sequentially turn on or turn off each output transistor in the first and second plurality of output transistors in response to each change in the first and second input signals received by the control circuit. And a control circuit coupled to the control terminal of each output transistor in the output transistor of the transistor.
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    同族专利:
    公开号 | 公开日
    AU5515998A|1998-06-22|
    US5949254A|1999-09-07|
    JP2001506821A|2001-05-22|
    KR100440753B1|2004-07-21|
    JP4016079B2|2007-12-05|
    WO1998024184A1|1998-06-04|
    US6084434A|2000-07-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-11-26|Priority to US8/757,738
    1996-11-26|Priority to US08/757,738
    1996-11-26|Priority to US08/757,738
    1997-11-26|Application filed by 린치 마이클 엘., 마이크론 테크놀로지 인코포레이티드
    2000-09-15|Publication of KR20000057264A
    2004-07-21|Application granted
    2004-07-21|Publication of KR100440753B1
    优先权:
    申请号 | 申请日 | 专利标题
    US8/757,738|1996-11-26|
    US08/757,738|1996-11-26|
    US08/757,738|US5949254A|1996-11-26|1996-11-26|Adjustable output driver circuit|
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