• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    A memory device in which an input / output sense amplifier is shared by neighboring memory banks to reduce the number of data lines and a chip area is described. The memory device may include a plurality of memory banks, a plurality of global input / output lines provided in each of the memory banks for transferring data read from the memory banks, and at least two neighbors of the memory banks. And a plurality of input / output sense amplifier units shared in one memory bank and selectively sensing and amplifying data transmitted to the global input / output lines.
    公开号:KR20000054884A
    申请号:KR1019990003222
    申请日:1999-02-01
    公开日:2000-09-05
    发明作者:윤홍일；이창호
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Multi-bank memory device having shared IO sense amplifier by adjacent memory banks
    The present invention relates to a semiconductor memory device, and more particularly, to a memory device in which an input / output sense amplifier is shared by neighboring memory banks.
    In general, in order to improve the performance of a computer system, an operation speed of a central processing unit (CPU) is required, and a performance of a memory device for storing data, programs, and the like required by a CPU is required. The operating speed of the CPU has been remarkably improved to exceed the operating speed of the DRAM. As a result, the operating speed of the DRAM is slower than the operating speed of the CPU.
    In order to overcome this problem, a DRAM, which is composed of a plurality of banks and operates in synchronization with a system clock, has been developed, that is, a multi-bank synchronous DRAM. Recently, with the development of multimedia technology, there is an increasing demand for a semiconductor memory device having a large bandwidth, that is, a large amount of input / output data transmitted per unit time. Accordingly, a semiconductor memory device having a high bandwidth such as X16, X32, and X64 has been developed. Is being developed.
    However, a memory device having a high bandwidth has a problem in that the number of data lines for transferring data is greatly increased. In particular, in the case of a double data rate synchronous DRAM that outputs two data for one clock, the number of required data lines is doubled compared to the general synchronous DRAM.
    This increase in the number of data lines is a direct cause of increasing chip area. Since the manufacturing cost increases as the chip area increases, there is a need to reduce the chip area by efficiently using data lines when designing a semiconductor memory device.
    An object of the present invention is to provide a memory device having a reduced chip area by reducing the number of data lines.
    1 is a block diagram illustrating a configuration of a multi-bank memory device according to a first embodiment of the present invention.
    FIG. 2 is a detailed circuit diagram of the input / output sense amplifier unit shown in FIG. 1.
    3 is a block diagram illustrating a configuration of a multi-bank memory device according to a second embodiment of the present invention.
    4 is a detailed circuit diagram of the input / output sense amplifier unit illustrated in FIG. 3.
    According to an aspect of the present invention, there is provided a memory device including a plurality of memory banks, a plurality of global input / output lines provided in each of the memory banks for transferring data read from the memory banks, and And a plurality of input / output sense amplifier units shared in at least two neighboring memory banks of the memory banks, for selectively sensing and amplifying data transmitted to the global input / output lines.
    Preferably, each of the input / output sense amplifier units may include a plurality of input / output sense amplifiers and a plurality of switches for selectively connecting global input / output lines of a memory bank selected by activation of a predetermined bank selection signal to a corresponding input / output sense amplifier. Equipped with. The switch may be implemented as a transfer gate whose on / off is controlled by activation of the bank selection signal.
    Each of the plurality of input / output sense amplifier units may be shared by two neighboring memory banks or by four neighboring memory banks. When one input / output sense amplifier unit is shared by four neighboring memory banks, two memory banks may be disposed to the left and right of one column decoder to share them.
    According to the present invention, since at least two neighboring memory banks share an input / output sense amplifier, the number of data lines is reduced, and as a result, the chip area is reduced.
    In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.
    FIG. 1 is a block diagram showing the configuration of a multi-bank memory device according to a first embodiment of the present invention. For convenience, a double data rate synchronous DRAM having eight memory banks is described as an example.
    In the memory device according to the first embodiment of the present invention, the first to eighth memory banks Bank1 to Bank8, the first to fourth input / output sense amplifier units IOSA1 to IOSA4, and the row decoders 11 to 18. Column decoders 21 to 28, data input / output multiplexers MUX1 and MUX2, and data input / output buffers BUF.
    Each of the first to eighth memory banks Bank1 to Bank8 includes first to eighth global input / output lines GIO1 to GIO8, row decoders 11 to 18, and column decoders 21 to 28. do.
    Each of the first to fourth input / output sense amplifier units IOSA1 to IOSA4 according to the first embodiment of the present invention may be configured to include two neighboring memory banks Bank1 / Bank2, Bank3 / Bank4, Bank5 / Bank6, and Bank7 /. Is shared by Bank8). Each of the first to fourth input / output sense amplifiers IOSA1 to IOSA4 selectively senses and amplifies data transmitted to the corresponding global input / output lines GIO1 to GIO8. For example, the first input / output sense amplifier unit IOSA1 selectively senses and amplifies data transmitted to any one of the first and second global input / output lines GIO1 and GIO2.
    The data input / output multiplexers MUX1 and MUX2 receive the sensed amplified data through first to fourth data input / output lines DIO1 to DIO4 and transmit the data to the data input / output buffer BUF.
    When the first to eighth global input / output lines GIO1 to GIO8 each include N lines, the first to fourth data input / output lines DIO1 to DIO4 may each include N lines. Accordingly, the number of data input / output lines DIO1 to DIO4 is reduced by half, compared to the conventional method in which an input / output sense amplifier is provided in each of the memory banks.
    For example, assuming that the input / output sense amplifier unit is provided in each of the memory banks shown in FIG. 1, two input / output sense amplifier units are provided between two neighboring memory banks. Since one input / output sense amplifier unit is connected to N data input / output lines, two input / output sense amplifier units provided in two neighboring memory banks are connected to 2N data input / output lines.
    However, when the input / output sense amplifier unit is shared by two memory banks as in the first embodiment of the present invention, since one input / output sense amplifier unit is provided for each of the two memory banks, each data input / output line DIO1 to DIO4 is divided into N. do. Therefore, the number of input / output data lines is reduced by half compared to the case where the input / output sense amplifier unit is not shared.
    FIG. 2 is a detailed circuit diagram of the input / output sense amplifier units IOSA1, IOSA2, IOSA3, and IOSA4 illustrated in FIG. 1, and the i-th global input / output line GIOi of the first memory bank sharing one input / output sense amplifier unit is shown. The j th global I / O line GIOj of the first memory bank and the input / output sense amplifier IOSAij shared therewith are described.
    Each of the first to fourth input / output sense amplifier units IOSA1, IOSA2, IOSA3, and IOSA4 according to the first embodiment of the present invention basically has the same configuration, and as illustrated, a plurality of input / output sense amplifiers IOSAij ) And a plurality of switches SWi and SWj.
    Each of the input / output sense amplifiers IOSAij serves to sense and amplify data transmitted to the global input / output lines GIOi and GIOj. Each input / output sense amplifier IOSAij may be implemented as a PMOS cross-coupled amplifier known to operate at a high speed and to consume low power.
    According to a preferred embodiment, as shown, it is composed of two PMOS transistors PM1, PM2 and three NMOS transistors NM1, NM2, NM3. Since the implementation of the input / output sense amplifier (IOSAij) can be easily implemented by those skilled in the art, a detailed description thereof will be omitted.
    The switches SWi and SWj are provided in each of the N global input / output lines. Each of the switches SWi and SWj is enabled by the activation of the predetermined bank selection signals BS1 and BS2 to transfer the corresponding global input / output lines GIOi, GIOiB, GIOj, and GIOjB to the corresponding input / output sense amplifiers IOSAij. Connect.
    For example, the i-th global input / output lines GIOi and GIOiB are connected to the input / output sense amplifier IOSAij by activating a first bank selection signal BS1, and the j-th global input / output line GIOj / GIOjB is connected to the second bank. The selection signal BS2 is connected to the input / output sense amplifier IOSAij.
    As illustrated, each of the switches SWi and SWj has transmission gates TG1, TG2, TG3, whose on / off is controlled by activation of the bank selection signals BS1 and BS2. TG4).
    Meanwhile, each of the input / output sense amplifiers IOSA1, IOSA2, IOSA3, and IOSA4 according to the present invention includes load transistors for precharging each of the global input / output lines GIOi, GIOiB, GIOj, and GIOjB. (P1-P4) can be further provided.
    In the input / output sense amplifiers IOSA1 to IOSA4 according to the first embodiment of the present invention, when one memory bank is selected and predetermined bank selection signals BS1 and BS2 are activated, corresponding global input / output lines GIOi and GIOiB. , GIOj, GIOjB) are connected to the corresponding input / output sense amplifiers (IOSAij).
    For example, when the first memory bank is selected and the first bank selection signal BS1 is activated, the switch SWi provided in the i-th global input / output line GIOi is enabled. As a result, the i-th global input / output line GIOi is connected to the corresponding input / output sense amplifier IOSAij. As a result, the data transmitted to the i-th global input / output line GIOi is sensed and amplified through the corresponding input / output sense amplifier IOSAij and transmitted to the corresponding data line DIOij and DIOijB.
    According to the first embodiment of the present invention, two neighboring memory banks are shared by one input / output sense amplifier unit. Therefore, when any one of two neighboring memory banks, for example, the first and second memory banks Bank1 and Bank2 is selected, any one of the first and second global input / output lines GIO1 and GIO2 provided therein is selected. The transmitted data is selectively sensed and amplified by the first input / output sense amplifier unit IOSA1. As a result, the number of data input / output lines DIO1, DIO2, DIO3, and DIO4 connected to the input / output sense amplifier unit is reduced by half, and layout efficiency is also improved because two memory banks share one input / output sense amplifier unit. .
    3 is a block diagram illustrating a configuration of a multi-bank memory device according to a second embodiment of the present invention, in which one input / output sense amplifier unit is shared by four memory banks, and a column decoder is formed by two neighboring memory banks. Same as the first embodiment except that it is shared. Incidentally, the same reference numerals as in Fig. 1 denote the same members, and like the first embodiment, the case of a double data rate synchronous DRAM having eight memory banks is described as an example.
    The memory device according to the second embodiment of the present invention may include first to eighth memory banks Bank1 to Bank8, first and second input / output sense amplifiers IOSA11 and IOSA22, and row decoders 11 to 18. Column decoders 31 to 34, a data input / output multiplexer MUX, and a data input / output buffer BUF.
    Each of the first to eighth memory banks Bank1 to Bank8 includes first to eighth global input / output lines GIO1 to GIO8 and row decoders 11 to 18. The column decoders 31 to 34 are provided between two neighboring memory banks and are shared by them.
    For example, the column decoder 31 provided between the first and second memory banks Bank1 and Bank2 is shared by the first and second memory banks Bank1 and Bank2. In addition, the first and second memory banks Bank1 and Bank2 may be disposed at left and right sides thereof with the column decoder 31 interposed therebetween as shown.
    Each of the first and second input / output sense amplifiers IOSA11 and IOSA22 according to the second embodiment of the present invention is shared by four neighboring memory banks Bank1 to Bank4 and Bank5 to Bank8. The first and second input / output sense amplifiers IOSA11 and IOSA22 selectively sense and amplify data transmitted to the corresponding global input / output lines GIO1 to GIO8.
    The data input / output multiplexer MUX receives the sensed amplified data through first and second data input / output lines DIO1 and DIO2 and transmits the data to the data input / output buffer BUF.
    When the first to eighth global input / output lines GIO1 to GIO8 each include N lines, the first and second data input / output lines DIO1 and DIO2 may each include N lines. Therefore, the number of data input / output lines DIO1 and DIO2 is reduced to one quarter compared to the conventional method in which an input / output sense amplifier is provided in each of the memory banks.
    For example, assuming that a conventional input / output sense amplifier unit is provided in each of the memory banks shown in FIG. 3, four input / output sense amplifier units are provided in four neighboring memory banks. Therefore, the four input / output sense amplifier units are connected to 4N data input / output lines.
    However, when the input / output sense amplifiers are shared by four memory banks as in the second embodiment of the present invention, since one input / output sense amplifier unit is provided for each of the four memory banks, each data input / output line (DIO1, DIO2) is N. do. Therefore, the number of input / output data lines is reduced to 1/4 compared to the case where the input / output sense amplifier unit is not shared.
    FIG. 4 is a detailed circuit diagram of the input / output sense amplifiers IOSA11 and IOSA22 shown in FIG. 3 and illustrates the i-th global input / output line GIOi and the second memory bank of the first memory bank sharing one input / output sense amplifier. The j th global I / O line (GIOj), the k th global I / O line (GIOk) of the third memory bank, the l th global I / O line (GIOl) of the fourth memory bank, and the I / O sense amplifier (IOSAijkl) shared therewith Is described. In the input / output sense amplifiers IOSA11 and IOSA22 according to the second embodiment of the present invention, one input / output sense amplifier IOSAijkl is shared by four global input / output lines GIOi, GIOj, GIOk, and GIOl. Except for the input / output sense amplifier sections (IOSA1 to IOSA4 in Fig. 2), except for the first embodiment.
    As illustrated, each of the first and second input / output sense amplifiers IOSA11 and IOSA22 according to the second embodiment of the present invention includes a plurality of input / output sense amplifiers IOSAijkl and a plurality of switches SWi, SWj, and SWk. , SWl).
    Each of the input / output sense amplifiers IOSAijkl serves to sense and amplify data transmitted to the global input / output lines GIOi, GIOj, GIOk, and GIOl.
    Each of the switches SWi, SWj, SWk, and SWl is provided in each of the corresponding global input / output lines GIO1 to GIO4. It is enabled by the activation of the predetermined bank selection signals BS1 to BS4 to connect the corresponding global input / output lines GIOi, GIOiB, GIOj, GIOjB, GIOk, GIOkB, GIOl, GIOlB to the corresponding input / output sense amplifiers IOSAijkl. do.
    For example, the i-th global input / output lines GIOi and GIOiB are connected to the input / output sense amplifier IOSAijkl by activating a first bank selection signal BS1, and the j-th global input / output lines GIOj and GIOjB are connected to the second bank. The selection signal BS2 is connected to the input / output sense amplifier IOSAijkl. Similarly, the k-th global input / output lines GIOk and GIOkB are connected to the input / output sense amplifier IOSAijkl by activating a third bank selection signal BS3, and the l-th global input / output lines GIOl and GIOlB are connected to the fourth bank. The selection signal BS4 is connected to the input / output sense amplifier IOSAijkl.
    As illustrated, each of the switches SWi, SWj, SWk, and SWl has transmission gates TG1 to on / off controlled by activation of the bank selection signals BS1 to BS4. TG8).
    Meanwhile, each of the input / output sense amplifiers IOSA11 and IOSA22 according to the present invention includes load transistors P1 for precharging each of the global input / output lines GIOi, GIOiB, GIOj, GIOjB, GIOk, GIOkB, GIOl, and GIOlB. To P8).
    In the input / output sense amplifiers IOSA11 and IOSA22 according to the second embodiment of the present invention, when one memory bank is selected and predetermined bank selection signals BS1 to BS4 are activated as in the first embodiment, The corresponding global input / output lines GIOi, GIOiB, GIOj, GIOjB, GIOk, GIOkB, GIOl, and GIOlB are connected to the corresponding input / output sense amplifiers IOSAijkl.
    For example, when the first memory bank is selected and the first bank selection signal BS1 is activated, the switch SWi provided in the i-th global input / output line GIOi is enabled. As a result, the i-th global input / output line GIOi is connected to the corresponding input / output sense amplifier IOSAijkl. As a result, the data transmitted to the i-th global input / output line GIOi is sensed and amplified through the corresponding input / output sense amplifier IOSAijkl and transmitted to the corresponding data lines DIOijkl and DIOijklB.
    According to the second embodiment of the present invention, the input / output sense amplifier unit is shared by four neighboring memory banks. Therefore, when any one of four neighboring memory banks, for example, the first to fourth memory banks Bank1 to Bank4 is selected, any one of the first to fourth global input / output lines GIO1 to GIO4 provided therein is selected. The data transmitted to is selectively sensed and amplified by the first input / output sense amplifier unit IOSA11. As a result, not only the number of data input / output lines DIO1 and DIO2 connected to the input / output sense amplifier unit is reduced to 1/4, but also the layout efficiency is improved because four memory banks share one input / output sense amplifier unit.
    The best embodiments have been described in the drawings and specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. For example, in the present specification, the case where the input / output sense amplifier unit is shared by two or four memory banks is described as an example, but the number of memory banks sharing one input / output sense amplifier unit may be extended to four or more. Therefore, the scope of the present invention should be defined by the technical spirit of the appended claims.
    According to the memory device of the present invention configured as described above, the input / output sense amplifier unit is shared by at least two neighboring memory banks. As a result, the number of data input / output lines is reduced and chip area is reduced.
    权利要求:
    Claims (8)
    [1" claim-type="Currently amended] A plurality of memory banks;
    A plurality of global input / output lines provided in each of the memory banks to transmit data read from the memory banks; And
    And a plurality of input / output sense amplifier units shared in at least two neighboring memory banks of the memory banks, and selectively sensing and amplifying data transmitted to the global input / output lines.
    [2" claim-type="Currently amended] The method of claim 1, wherein each of the input and output sense amplifier unit,
    A plurality of input / output sense amplifiers; And
    And a plurality of switches for selectively connecting global input / output lines of a memory bank selected by activation of a predetermined bank selection signal to a corresponding input / output sense amplifier.
    [3" claim-type="Currently amended] The method of claim 2, wherein the switch,
    And a transfer gate whose on / off is controlled by activation of the bank selection signal.
    [4" claim-type="Currently amended] The method of claim 1, wherein each of the plurality of input and output sense amplifier units,
    A memory device, characterized by being shared by two neighboring memory banks.
    [5" claim-type="Currently amended] The memory device of claim 4, wherein each of the memory banks further includes a row decoder and a column decoder, and the column decoders are disposed between the input / output sense amplifier unit and the memory banks sharing the same.
    [6" claim-type="Currently amended] The method of claim 1, wherein each of the plurality of input and output sense amplifier units,
    A memory device, characterized by being shared by four neighboring memory banks.
    [7" claim-type="Currently amended] The memory bank of claim 6, wherein the memory banks further include row decoders and column decoders, wherein each column decoder is configured by at least two memory banks among the four memory banks sharing one input / output sense amplifier unit. Memory device, characterized in that shared.
    [8" claim-type="Currently amended] The method of claim 6, wherein each of the input and output sense amplifier unit,
    A plurality of input / output sense amplifiers; And
    And a plurality of switches for selectively connecting global input / output lines of a memory bank selected by activation of a predetermined bank selection signal to a corresponding input / output sense amplifier.
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    同族专利:
    公开号 | 公开日
    KR100363079B1|2002-11-30|
    US6327214B1|2001-12-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-02-01|Application filed by 윤종용, 삼성전자 주식회사
    1999-02-01|Priority to KR1019990003222A
    2000-09-05|Publication of KR20000054884A
    2002-11-30|Application granted
    2002-11-30|Publication of KR100363079B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019990003222A|KR100363079B1|1999-02-01|1999-02-01|Multi-bank memory device having shared IO sense amplifier by adjacent memory banks|
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