• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method for fabricating a capacitor is provided to suppress a lifting phenomenon and a surface characteristic drop between upper and lower metal electrodes. CONSTITUTION: In a method for fabricating a capacitor, a flattened interlayer insulation film(20) is formed on a wafer, and a titanium film(21) as an adhesion layer is formed on the flattened interlayer insulation film(20). A platinum film(22) for a lower electrode is deposited on the platinum film(22) by a sputtering method, and a lower electrode is formed by etching the films(22,21). A ferroelectric film(23) is formed so as to cover the lower electrode. A titanium film(24) is deposited on an entire surface of a resultant structure, and the titanium film(24) on a surface of the ferroelectric film(23) is selectively etched. A titanium film(25) for an upper electrode is deposited on an entire surface, and an upper electrode is formed by etching the films(25,24).
    公开号:KR20000044611A
    申请号:KR1019980061110
    申请日:1998-12-30
    公开日:2000-07-15
    发明作者:이석재
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Capacitor Formation Method of Semiconductor Device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a method of forming a capacitor of a semiconductor device.
    With high integration of semiconductor devices including DRAM (Dynamic Random Access Memory), securing a sufficient capacitance of a capacitor has emerged as a big problem. As a solution to this problem, the surface area of the charge storage electrode, which is the lower electrode of the capacitor, is increased. Many researches and developments on technology have been conducted. However, there is also a limit to increase the surface area of the charge storage electrode due to the decrease in the process margin associated with high integration.
    In order to overcome this limitation, high-density DRAMs have been applied to high-density DRAMs using high-k dielectric materials such as BST, which are high-k dielectrics, as capacitor dielectric layers. This applies the principle that the capacitance of the capacitor is proportional to the permittivity.
    On the other hand, ferroelectric memory devices (FeRAM), which are in the spotlight as the next generation of nonvolatile memory devices, include SrBi 2 Ta 2 O 9 (SBT) and Pb (Zr x Ti 1-x ) O 3 (PZT) as dielectric materials constituting a capacitor. Ferroelectric materials are used.
    As described above, in manufacturing a high dielectric capacitor or a ferroelectric capacitor, in order to secure excellent dielectric thin film characteristics, selection of upper and lower electrodes and surrounding materials and control of an appropriate process are essential.
    Currently, platinum (Pt) having excellent electrode characteristics is mainly used as the upper and lower electrode materials of high dielectric capacitors or ferroelectric capacitors. The platinum film has little reactivity with oxygen and thus does not form an oxide compound at the junction with the oxide-based dielectric, and also has excellent chemical stability against high temperature thermal processes in an oxygen atmosphere which is performed to improve dielectric properties. When such a platinum film is used as the lower electrode, since the bonding strength with the lower interlayer insulating film (mainly silicon oxide film) is not good, a titanium (Ti) film having excellent adhesion with both the oxide film and the platinum film is used as the adhesive layer.
    1 is a cross-sectional view of a ferroelectric capacitor formed according to the prior art, which will be described with reference to the following.
    The conventional ferroelectric capacitor forming process first deposits a Ti film (which is oxidized and changed into a TiO x film during the subsequent thermal process) 11 as an adhesive layer on top of the entire structure on which the planarized interlayer insulating film 10 is formed after completing a predetermined lower layer process. The upper electrode platinum film 12, the ferroelectric thin film 13, and the upper electrode platinum film 14 are sequentially deposited thereon, and the upper electrode platinum film 14 and the ferroelectric thin film 13 are subjected to a mask process. The lower electrode platinum film and the Ti film 11 are selectively etched to pattern a capacitor having a so-called MIM (Metal / Insulator / Metal) stacked structure.
    However, due to the stress of the thin film induced by the large thermal expansion coefficient difference between the platinum film (12, 14) and the ferroelectric thin film (13) during the high temperature heat treatment process in the oxygen atmosphere which is usually performed in the capacitor formation process The interface between the platinum films 12 and 14 and the ferroelectric thin film 13 is very rough, or there is a problem in that a lifting phenomenon A occurs between them. This lifting phenomenon A is a factor that greatly reduces the characteristics of the capacitor.
    This problem has been pointed out as a problem not only in the use of non-platinum electrodes but also in the formation of ferroelectric capacitors and high-k dielectric capacitors using other metal electrodes.
    SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of suppressing the deterioration and the lifting phenomenon of the interface between the dielectric thin film and the metal electrodes above and below.
    1 is a cross-sectional view of a ferroelectric capacitor formed in accordance with the prior art.
    2A to 2D are ferroelectric capacitor manufacturing process diagrams according to an embodiment of the present invention.
    * Explanation of symbols for the main parts of the drawings
    20: interlayer insulating film 21, 24: Ti film
    22: platinum film for lower electrode 23: ferroelectric thin film
    25 platinum film for upper electrode 26 capping oxide film
    27 metal wiring
    According to the present invention, a dielectric thin film is deposited to cover the entire bottom electrode after patterning, and then the upper electrode is covered with the upper electrode, thereby reducing stress induction in a balanced MIM stacked structure, thereby increasing the MIM structure during a high temperature thermal process. This is a technique for preventing the lifting phenomenon from occurring at the interface between the metal electrode and the dielectric thin film. In addition, the present invention can further increase the effect by applying the adhesive layer to the upper electrode as well as the lower electrode.
    In order to achieve the above technical problem, a method of forming a capacitor of a characteristic semiconductor device provided by the present invention includes: a first step of forming a lower electrode metal film on a predetermined lower layer; A second step of patterning the lower electrode by selectively etching the lower electrode metal film; Forming a dielectric film covering the lower electrode surface; A fourth step of forming a metal film for the upper electrode on the entire structure after performing the third step; And a fifth step of patterning the upper electrode by selectively etching the upper electrode metal film.
    In addition, a method of forming a capacitor of a characteristic semiconductor device provided from the present invention to achieve the above technical problem, the first step of forming a first adhesive layer on the interlayer insulating film formed on a predetermined lower layer; Forming a lower electrode metal film on the first adhesive layer; A third step of patterning the lower electrode by selectively etching the lower electrode metal layer and the first adhesive layer; A fourth step of forming a dielectric film covering the lower electrode surface; A fifth step of forming a second adhesive layer on the exposed interlayer insulating film after performing the fourth step; A sixth step of forming a metal film for the upper electrode on the entire structure after the fifth step; And a seventh step of patterning the upper electrode by selectively etching the upper electrode metal layer and the second adhesive layer.
    Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
    2A to 2D illustrate a ferroelectric capacitor manufacturing process according to an embodiment of the present invention, which will be described below with reference to the drawings.
    The process according to the present embodiment first finishes a predetermined lower layer process as shown in FIG. 2A, and then forms a Ti film 21 as an adhesive layer on the wafer on which the planarized interlayer insulating film 20 is formed, and then on top of it. The lower electrode platinum film 22 is deposited using a sputtering method, and then the lower electrode is patterned by selectively etching the platinum film 22 and the Ti film 21.
    Subsequently, as shown in FIG. 2B, the ferroelectric thin film 23 is deposited on the platinum film 22 and patterned to form a structure in which the ferroelectric thin film 23 covers the lower electrode.
    Next, as shown in FIG. 2C, the Ti film 24 is further deposited on the entire structure, the Ti film 24 on the surface of the ferroelectric thin film 23 is selectively removed, and then the upper electrode platinum is formed on the entire structure. The film 25 is deposited, and the platinum film 25 and the Ti film 24 are selectively etched to pattern the upper electrode.
    Thereafter, as shown in FIG. 2D, a conventional capacitor manufacturing process is performed to form the capping oxide layer 26 and the metal wiring 27 contacting the platinum layer 25 through the capping oxide layer 26.
    In the capacitor completed through the above process, both ends of the upper electrode as well as the lower electrode are strongly bonded to the adhesive layer, so that the stress between the metal electrode and the dielectric thin film generated by the thermal process that is typically performed when the capacitor is formed. It can support.
    The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
    For example, in the above-described embodiment, the case where the platinum film is used as the upper and lower electrodes has been described as an example, but the present invention can be applied to the case of using other kinds of metal electrodes such as iridium (Ir).
    In addition, in the above-described embodiment, the case of using the Ti film as the adhesive layer has been described as an example, but the present invention may be applied to the case of using other materials as the adhesive layer.
    The present invention described above has the effect of improving the interfacial characteristics between the metal electrode and the dielectric of the capacitor and suppressing the lifting phenomenon, thereby improving the capacitor characteristics and the reliability of the device can be expected. In addition, since the present invention uses the sidewall of the lower electrode, there is a side effect of increasing the effective capacitor area.
    权利要求:
    Claims (7)
    [1" claim-type="Currently amended] Forming a lower electrode metal film on the predetermined lower layer;
    A second step of patterning the lower electrode by selectively etching the lower electrode metal film;
    Forming a dielectric film covering the lower electrode surface;
    A fourth step of forming a metal film for the upper electrode on the entire structure after performing the third step; And
    A fifth step of patterning the upper electrode by selectively etching the upper electrode metal film
    Capacitor formation method of a semiconductor device comprising a.
    [2" claim-type="Currently amended] The method of claim 1,
    And the metal film for the lower electrode is a platinum film.
    [3" claim-type="Currently amended] The method according to claim 1 or 2,
    And the metal film for the upper electrode is a platinum film.
    [4" claim-type="Currently amended] A first step of forming a first adhesive layer on the interlayer insulating film formed on the predetermined lower layer;
    Forming a lower electrode metal film on the first adhesive layer;
    A third step of patterning the lower electrode by selectively etching the lower electrode metal layer and the first adhesive layer;
    A fourth step of forming a dielectric film covering the lower electrode surface;
    A fifth step of forming a second adhesive layer on the exposed interlayer insulating film after performing the fourth step;
    A sixth step of forming a metal film for the upper electrode on the entire structure after the fifth step; And
    A seventh step of patterning the upper electrode by selectively etching the upper electrode metal layer and the second adhesive layer
    Capacitor formation method of a semiconductor device comprising a.
    [5" claim-type="Currently amended] The method of claim 4, wherein
    And the first and second adhesive layers are titanium films.
    [6" claim-type="Currently amended] The method of claim 4, wherein
    And the metal film for the lower electrode is a platinum film.
    [7" claim-type="Currently amended] The method according to claim 4 or 6,
    And the metal film for the upper electrode is a platinum film.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-12-30|Application filed by 김영환, 현대전자산업 주식회사
    1998-12-30|Priority to KR1019980061110A
    1998-12-30|Priority claimed from KR1019980061110A
    2000-07-15|Publication of KR20000044611A
    2002-09-04|Application granted
    2002-09-04|Publication of KR100326241B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980061110A|KR100326241B1|1998-12-30|A method for forming capacitor in semiconductor device|
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