• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A test device and testing method in exchanger system is provided to self-test by continuously generating the constant test data as same as the application of electric source. CONSTITUTION: A test device in exchanger system comprises a test data generator(111), a parallel/serial converter(115), an E1 line insert unit(117), a multiplexor(119), an E1 line expeller/insert unit(120), a demultiplexor(121), an E1 line expeller(123), a serial/parallel converter(125) and a comparator(127). The test data generator(111) reads a parallel test data for the operating test of exchanger system. The parallel/serial converter(115) converts the parallel test data generated from the test data generator(111) to a serial test data. The E1 line insert unit(117) inserts the converted serial test data to an E1 line of synchronous channel. The multiplexor(119) multiplexes the E1 line data communication inserting data in prescribed speed. The E1 line expeller/insert unit(120) expels the data corresponding to a first 0 channel among the multiplexed channel and inserts the first 0 channel of E1 line. The demultiplexor(121) inputs the E1 line including the test data and demultiplexes the E1 line in the original speed. The E1 line expeller(123) expels the first 0 channel of E1 line among the demultiplexed serial data signal. The serial/parallel converter(125) converts the first 0 channel data to a parallel data. The comparator(127) compares the parallel first 0 channel data with the first test signal of the test data generator(111).
    公开号:KR20000044433A
    申请号:KR1019980060931
    申请日:1998-12-30
    公开日:2000-07-15
    发明作者:이홍기
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Testing apparatus and method of exchange system
    The present invention relates to an exchange system, and more particularly, to a data testing apparatus and method for testing data errors of a particular module.
    In general, in order to perform self-testing in the exchange system, a CRT that can be matched with TELEPHONY DEVICE CONTROL BUS (TD_BUS), a TD_BUS cable (CABLE) for physical coupling of the exchange system and the CRT, and data interfacing. It had to be equipped with a number of equipment such as RS-232C cable. In addition, when testing a specific module of the exchange system through the CRT, the operator must input a command for testing, check the output data output after inputting the command, and determine whether there is an abnormality, and also command the operator. It was not possible to perform continuous testing just by single testing.
    Accordingly, it is an object of the present invention to provide a testing apparatus and method of an exchange system that performs self-testing continuously upon power up.
    In order to achieve the above object, the present invention provides a testing apparatus for an exchange system that performs data communication using an E1 method, and detects a power supply to perform predetermined testing data that is preset for operation testing of the exchange system. A testing data generator configured to latch and generate parallel testing data, a parallel / serial converter configured to serially convert the parallel testing data generated by the testing data generator, and test data serially converted through the parallel / serial converter; An E1 line insertion unit inserted into a first channel, which is a synchronization channel of the E1 line of the switching system, a mux for doubling and multiplexing the E1 line data communication into which the testing data is inserted at a predetermined speed, and doubling at a predetermined speed through the mux And extracting the data corresponding to the 0th channel of the multiplexed signal to the 0th channel of the E1 line A demux for inserting E1 line extracting and inserting unit, a demux for inputting E1 line including testing data into a 0 channel through the E1 line extracting and inserting unit, and demultiplexing at the original speed, and demultiplexing through the demux. An E1 line extractor extracting the 0th channel of the E1 line from the serial data signal and 0 channel data output from the E1 line extractor are input, and the 0th channel data is converted in parallel to result data. A serial / parallel conversion unit for outputting and a comparison unit for generating a predetermined alarm control signal by comparing the zero channel result data converted in parallel through the serial / parallel conversion unit with the first testing data generated by the testing data generation unit; It is characterized by the configuration.
    1 is a block diagram showing an internal configuration of a testing apparatus for performing a function in an embodiment of the present invention.
    2 is a diagram illustrating input data generation and latch timing according to an exemplary embodiment of the present invention.
    3 is a testing timing diagram according to an embodiment of the present invention.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.
    1 is a block diagram showing an internal configuration of a testing apparatus for performing a function in an embodiment of the present invention.
    The testing device starts a test data storage unit 113 that stores specific testing data that is random or fixed (FIXED), in response to detecting power supply, and is stored in the testing data storage unit 113. A testing data generating unit 111 for reading and enabling testing data, and a parallel / serial converting unit for serial data conversion of parallel testing data generated by the testing data generating unit 111 ( 115), an E1 line inserting unit 117 for inserting the serialized conversion test data through the parallel / serial converting unit 115 into a first channel which is a synchronization channel of the E1 line of the switching system, and the testing data The MUX 119 doubles the inserted E1 line data communication at a predetermined speed and multiplexes the data, and the data corresponding to the 0th channel among the multiplexed signals is doubled at a predetermined speed through the MUX 119. E1 line extraction and insertion unit 120 to be inserted into the 0th channel of the E1 line and the E1 line including the testing data into the 0th channel through the E1 line extraction and insertion unit 120 at the original speed. A DEMUX 121 for demultiplexing, an E1 line extracting unit 123 for extracting a zero channel of the E1 line among the demultiplexed serial data signals through the DEMUX 121, and the E1 line extracting unit 123 Serial to parallel conversion unit 125 for parallel-converting the 0-channel output data extracted through) and outputting the result data as result data, and the zero-converted parallel conversion through the serial / parallel conversion unit 125. Comparing unit 127 for generating a predetermined alarm control signal by comparing the channel result data with the first testing data generated in the testing data generator 111 and an alarm corresponding to the alarm control signal generated in the comparator 127. Configure including the alarm unit 129 to generate.
    2 is a diagram illustrating input data generation and latch timing according to an exemplary embodiment of the present invention.
    3 is a testing timing diagram according to an embodiment of the present invention.
    Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 3.
    The switching system is E1 (32 timeslots of PCM schemes, which is recommended by ITU-TS G.732, constitutes one frame, and a time division multiplexing transmission scheme having a transmission rate of 2048 Mbps. The 0th channel is for synchronization and the 16th channel is And data communication, and when the power is applied, the exchange system activates the E1 line. Accordingly, as shown in FIG. 2, the E1 line is activated at the same time as the power is applied, and thus the synchronization channel MFS 211, CNTFS0 213, CNTFS1 215, CNTFS2 217, and CNTFS3 ( 219 are each enabled with logical HIGH. In this case, one frame (FRAME) of the synchronization channel MFS 211 has a cycle of 125μs, the CNTFS0 213 has a cycle of 125μs of one frame, the CNTFS1 215 has a cycle of 250μs of two frames, the CNTFS2 (217) ) Is enabled at a logic high of 4 frames 500 μs, and the CNTFS3 219 is 8 frames of 1000 μs. The testing data generator 111, which detects the activation of the synchronization channel of the E1 line, generates a clock RCOCLK 221 for latching testing data stored in the testing data storage 113. At this time, the testing data generator 111 sets the RCOCLK 221 at every occurrence of the total synchronization channel of the E1 line, that is, the MFS 211, the CNTFS0 213, the CNTFS1 215, and the CNTFS2 217. And, when each of CNTFS3 219 are all enabled, is logic high. That is, the testing data generator 111 applies the RCOCLK 221 enabled at the cycle of 16 frames 2ms to the testing data storage 113. Accordingly, the testing data storage unit 113 latches the previously stored testing data RND0 # FIXD0-RND7 # FIXD7 223 and transmits them to the parallel / serial conversion unit 115. The parallel / serial converter 115 inputs the test data RND0 # FIXD0-RND7 # FIXD7 223 generated by latching the testing data storage 113 to the parallel data. Is applied to the E1 line insertion unit 117 by serial conversion 315. The E1 line inserting unit 117 inputs the serialized testing data outputted from the parallel / serial converting unit 115 and uses the input testing data as a synchronization channel of the E1 line of the exchange system. After inserting into the 0th channel CH0, it outputs to the MUX 119 for 32E1 * 32CH. Frame synchronization FSs (311, 319, 327, 335) are signals for frame synchronization, respectively. In addition, the data streams 313, 321, 329, and 337 perform data transmission at varying frequencies of 2 MHz and 8 MHz according to circumstances. At this time, the E1 line inserting unit 117 generates a DEN (DATA ENABLE) 317 for enabling data and inserts the serialized testing data 315 into the 0th channel. The MUX 119 multiplexes and outputs data of the E1 line into which the testing data 315 is inserted. The testing data 323 multiplexed through the MUX 119 is outputted to the E1 line extraction and insertion unit 120. The E1 line extraction and insertion unit 120 enables the OEN (OUT ENABLE) 325 to expel the testing data 323 of the 0th channel among the signals output from the MUX 119 and then DMEN (DEMUX INPUT). ENABLE) 333 is enabled to insert the extracted testing data 331 into the 0th channel of the DEMUX 121. The DEMUX 121 demultiplexes the received signal and outputs the demultiplexed signal. The E1 line extracting unit 123 inputs the signal output from the DEMUX 121, enables the clock DOEN (DATA OUT ENABLE) 241 to test the data 339 of the 0th channel of the E1 line. Ejected and output to the serial / parallel conversion unit 125. The serial / parallel conversion unit 125 inputs the data output from the E1 line extraction unit 123, performs parallel conversion (SERIAL TO PARALLEL) on the input serial testing data 339, and outputs the result data.
    Accordingly, the comparison unit 127 inputs the test data 223 generated by the testing data generator 111 stored temporarily and the result data output from the serial / parallel conversion unit 125, respectively, and the testing data. Compare the result data with 223. The comparator 127 is implemented as a 2-INPUT X-OR (EXCLUSIVE OR) gate, and gates the test data 223 and the result data as two inputs. When the gating result is a logic low, that is, when the test data 223 and the result data match, an alarm control signal of a logic low indicating that the operation of the switching system according to the test is normal is generated and output to the alarm unit 129. do. In addition, when the gating result is a logic high, that is, when the testing data 223 and the result data do not match, an alarm control signal of a logic high indicating an abnormal operation of the switching system according to the test is generated to the alarm unit 129. Output The alarm unit 129 performs an operation corresponding to the alarm control signal generated by the comparator 127. When the alarm control signal is a logic low alarm signal, the alarm unit 129 does not perform a special operation but generates an alarm corresponding to an alarm control signal of a logic high signal. Occurs. In this case, the generated alarm may be a visual alarm through a display element such as an LED or an acoustic alarm such as a beep sound.
    Thus, such a testing apparatus makes it possible to automatically perform continuous testing upon powering up.
    As described above, the embodiments of the present invention have been described with reference to the drawings, for example, but various changes and modifications can be made within the scope allowed by the matter.
    As described above, the present invention is capable of performing continuous testing by continuously generating a certain test data and performing testing at the same time the power is supplied to the exchange system, and performs the automatic testing without the operator's command so that it can be matched with the operator. There is no need to provide a separate equipment for the operator, and also has the advantage that the operator is provided with the convenience of maintenance and maintenance due to the removal of a separate command for testing.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] In the testing apparatus of the switching system for performing data communication using the E1 method,
    A testing data generator which detects a power supply and latches predetermined testing data which is preset for operation testing of the switching system to generate parallel testing data;
    A parallel / serial converter configured to serially convert parallel testing data generated by the testing data generator;
    An E1 line inserting unit for inserting serially converted testing data through the parallel / serial converting unit into a first channel which is a synchronization channel of the E1 line of the switching system;
    MUX for doubling and multiplexing the E1 line data communication into which the testing data is inserted, at a predetermined speed;
    An E1 line extracting and inserting unit extracting data corresponding to a 0th channel among the multiplexed signals multiplied at a predetermined speed through the mux and inserting the data corresponding to the 0th channel of the E1 line;
    Demux for demultiplexing at the original speed by inputting the E1 line including the test data to the 0 channel through the E1 line extraction and insertion unit,
    An E1 line extracting unit for extracting a 0th channel of the E1 line from the demultiplexed serial data signal through the demux;
    A serial / parallel converter for inputting the zero channel data output from the E1 line extracting unit, converting the input zero channel data in parallel and outputting the result data as result data;
    And a comparison unit configured to generate a predetermined alarm control signal by comparing the zero channel result data converted in parallel through the serial / parallel conversion unit with the first testing data generated by the testing data generator. Testing device.
    [2" claim-type="Currently amended] The method of claim 1,
    The comparison unit comprises a logic low alarm control signal indicating that the operation of the switching system is normal when the first testing data generated by the testing data generator is identical to the zeroth channel result data;
    And when the initial testing data and the zeroth channel output data do not coincide with each other, generating an alarm control signal of a logic high indicating that the operation of the switching system is abnormal.
    [3" claim-type="Currently amended] The method of claim 2,
    And the comparing unit is implemented with a single exclusive ora gate.
    [4" claim-type="Currently amended] The method of claim 2,
    And an alarm unit for generating a predetermined alarm corresponding to the alarm control signal of the logic high output from the comparison unit.
    [5" claim-type="Currently amended] In the testing method of the exchange system to perform data communication using the E1 method,
    Detecting a power supply to the exchange system to generate predetermined testing data;
    Multiplexing and inserting the generated testing data into the 0th channel of the E1 line of the exchange system;
    Extracting data corresponding to a 0th channel of the multiplexed signals and inserting the same into a 0th channel of an E1 line of the exchange system;
    Demultiplexing the data input through the E1 line;
    Extracting the zero channel data of the demultiplexed E1 line data and converting the extracted serial zero channel data in parallel;
    And when the parallel-converted zero channel result data is not matched with the first generated test data, generating an alarm control signal of logic high indicating that the operation of the switching system is abnormally performed. Testing method.
    类似技术:
    公开号 | 公开日 | 专利标题
    US5761216A|1998-06-02|Bit error measurement system
    EP0852730B1|2005-06-08|Parallel processing integrated circuit tester
    US5144297A|1992-09-01|Digital cross connection apparatus
    TWI273259B|2007-02-11|Built-in test architecture
    US5136587A|1992-08-04|Digital signal multiplexing apparatus and demultiplexing apparatus
    US4316284A|1982-02-16|Frame resynchronization circuit for digital receiver
    US6084889A|2000-07-04|ATM multiplexing apparatus, ATM demultiplexing apparatus, and communication network with the apparatus
    EP0333122B1|1996-06-12|Method and apparatus for frame synchronization
    EP0482550B1|1996-03-20|A virtual identifier conversion system
    US4658152A|1987-04-14|Adaptive rate multiplexer-demultiplexer
    US5357249A|1994-10-18|Apparatus and method for high speed flexible multiplexing for fiber optic data transmissions
    CA1205550A|1986-06-03|Distributed digital exchange with improved switchingsystem and input processor
    EP0068595B1|1986-08-13|A bit-interleaved time division multiplexer
    CA1229184A|1987-11-10|Frame arrangement for multiplexing a plurality ofsubchannels onto a fixed rate channel
    US4858224A|1989-08-15|Diagnostic method of equipment and system using the same
    US5485470A|1996-01-16|Communication circuit fault detector
    JP4009666B2|2007-11-21|SDH network and data transmission method thereof
    EP0214783A2|1987-03-18|Digital transmisson including add/drop module
    US5034906A|1991-07-23|Pseudorandom Binary Sequence delay systems
    US3632882A|1972-01-04|Synchronous programable mixed format time division multiplexer
    US5265096A|1993-11-23|Sonet alarm indication signal transmission method and apparatus
    JP4541155B2|2010-09-08|Frame synchronization device and method
    EP0320882A2|1989-06-21|Demultiplexer system
    EP0849972A2|1998-06-24|Path test signal generator and checker for use in a digital transmission system using a higher order virtual container VC-4Xc in STM-N frames
    US5978377A|1999-11-02|STM-based ATM cell physical layer processing circuit
    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-12-30|Application filed by 윤종용, 삼성전자 주식회사
    1998-12-30|Priority to KR1019980060931A
    2000-07-15|Publication of KR20000044433A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980060931A|KR20000044433A|1998-12-30|1998-12-30|Test device and testing method in exchanger system|
    [返回顶部]