• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an electrostatic protection circuit of a semiconductor device. Disclosed is an electrostatic protection circuit capable of forming a source / drain portion of a gate oxide transistor in a trench to increase a corner area of a drain to prevent damage to a device due to overcurrent generated at the corner.
    公开号:KR20000027648A
    申请号:KR1019980045605
    申请日:1998-10-28
    公开日:2000-05-15
    发明作者:황정열
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Static electricity protection circuit
    The present invention relates to an electrostatic protection circuit of a semiconductor device.
    In general, a plurality of semiconductor devices are manufactured together in a wafer state, and then cut into chips and used in a packaging state.ElectroStatic Discharge generated by an apparatus or a human body during a manufacturing process or transportation in a wafer state or a package state When ESD is applied, a high voltage of 4000 V or more is applied to destroy the device.
    This internal circuit damage is caused by junction spiking and oxide rupture in the place where the charge injected through the input terminal during electrostatic discharge is vulnerable due to joule heat, which is finally passed through the internal circuit to the other terminal. ), Etc.
    In order to solve this problem, before the electric charge injected into the electrostatic discharge is discharged through the internal circuit, it is possible to prevent the damage of the semiconductor device due to the electrostatic discharge by using an antistatic circuit that can discharge the electric charge injected into the input terminal directly to the power supply terminal. have.
    Conventional ESD protection devices include field transistors that consume most of the current when ESD is applied between the input pads and the internal circuits, gate-ground NMOS transistors for protecting the gate oxide of the internal circuits, and excessive currents to the NMOS transistors. The ESD protection field transistor is a source / drain region of the field transistor on one side and the other side of the field oxide film formed on the semiconductor substrate including the P well. n + diffusion region is formed, the n + diffusion region on one side is connected to the input pin, the other n + diffusion region is connected to Vss. The ESD protection device itself is destroyed when the ESD is applied, and the drain portion of the field transistor is mainly damaged because the drain portion is directly connected to the input pin.
    The operation of the ESD device may be described as bipolar operation of the field transistor.
    First, when a high voltage is applied to the input pad, avalanche breakdown starts at the drain of the gate ground transistor connected to the resistor. This is because the layout is designed such that the field transistor is not sharply angled in general, and the junction breakdown voltage is high. If the current flows to the junction of the field transistor after the junction breakdown, a voltage difference occurs in the resistance, and when the sum of the junction breakdown voltage and the voltage difference in the resistance becomes similar to the junction breakdown voltage of the field transistor, the current becomes the junction of the field transistor. As the current flows into the well, the junction breaks to ground, and the current into the well increases, the well voltage around the field transistor increases due to the voltage difference due to the well resistance. Here, the source of the field transistor becomes the emitter of the bipolar transistor, the well becomes the base and the drain becomes the collector to start the bipolar operation. This is because the base voltage of the bipolar transistor rises and the emitter-base junction is forward. In general, an ESD protection circuit connects a pad by drilling a metal contact in a junction.
    When a thick gate oxide transistor is used as an ESD protection transistor, bipolar operation of the gate oxide transistor is started only when the junction breakdown voltage is reached. In general, since the breakdown voltage is low at the corner of the drain connected to the pad, current is driven to the corner. However, since the edge portion is small in area, device damage due to overcurrent is generated, such as a lot of heat.
    An object of the present invention is to increase the edge area of the drain in order to enhance the bipolar operation of the gate oxide transistor.
    1A to 1C are cross-sectional views illustrating a method of manufacturing an electrostatic protection circuit according to the present invention.
    In order to achieve the above object, the present invention forms a source / drain region of the gate oxide transistor in a trench to increase the area of the edge portion of the drain. As a result, the current density at the edge portion is reduced, thereby preventing damage to the device due to overcurrent.
    During ESD zapping, a large amount of current is injected into a specific pin, which triggers the gate oxide transistor, which is an ESD protection transistor, to subtract this current. The gate oxide transistor allows current to flow in bipolar operation upon break down. However, if the amount of current is momentarily large and the junction cannot afford, an ESD fail occurs because the current is driven to the narrow edge of the drain region.
    In the present invention, the trench structure is used to increase the edge area of the source / drain.
    Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.
    1A-1C illustrate one embodiment according to the present invention.
    First, an element isolation oxide film 12 and a gate oxide film 14 are formed on the substrate 10 (FIG. 1A).
    Next, the trench 20 is formed by etching the source / drain regions of the gate oxide transistor by a trench process. Subsequently, N + ions are implanted into the trench 20 to form a high concentration ion implantation region 16 for the source / drain. (FIG. 1B) However, due to the nature of the ion implantation process, it is difficult to dope the sidewalls of the trench. . Therefore, after ion implantation, the doped polysilicon layer 18 is deposited on the inner wall of the trench 20 so that the N-type doping is also performed on the sidewalls of the trench (FIG. 1C). Quite wide.
    Therefore, a phenomenon in which overcurrent occurs due to a current gathered at the corners during ESD zapping can be prevented, and the reliability of the device can be improved.
    The other static protection function is the same as the conventional one.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] An electrostatic protection circuit, wherein the source and / or drain are formed in a trench.
    [2" claim-type="Currently amended] The static electricity protection circuit according to claim 1, wherein a high concentration ion implanted polysilicon film is formed on the inner wall of the trench.
    [3" claim-type="Currently amended] The static electricity protection circuit according to claim 2, wherein the polysilicon film is implanted with ions having the same polarity as the ions implanted in the source / drain regions.
    [4" claim-type="Currently amended] (a) forming a device isolation oxide film and a gate oxide film on the substrate;
    (b) forming trenches in the source and drain regions of the substrate;
    and (c) implanting high concentration ions into the trench bottom and sidewalls.
    [5" claim-type="Currently amended] The method of claim 4, wherein the step (c) is performed by forming a polysilicon film implanted with high concentration ions on the inner wall of the trench after implanting high concentration ions into the bottom of the trench.
    [6" claim-type="Currently amended] 6. The static electricity protection circuit according to claim 5, wherein the polysilicon film is implanted with ions having the same polarity as the ions implanted in the source / drain regions.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-10-28|Application filed by 김영환, 현대전자산업 주식회사
    1998-10-28|Priority to KR1019980045605A
    2000-05-15|Publication of KR20000027648A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980045605A|KR20000027648A|1998-10-28|1998-10-28|Circuit for protecting electrostatic|
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