• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a processor arbitration apparatus, wherein the same bootable memory device can be used by translating one of the addresses accessed by two master processors, and the bus can be equally authorized by giving two processors equal access rights. Can be used jointly. Therefore, by sharing a bootable memory device, not only is the use of high performance and resources very efficient, but also all the useful functions as a master can be utilized when all the processors are used as masters.
    公开号:KR19990086858A
    申请号:KR1019980020030
    申请日:1998-05-30
    公开日:1999-12-15
    发明作者:박영섭
    申请人:강병호；대우통신 주식회사；
    IPC主号:
    专利说明:

    Processor arbitration device
    The present invention relates to a processor arbitration apparatus, and more particularly, to an arbitration apparatus of a processor such that two processors share a bus and a bootable memory element to process instructions simultaneously.
    In general, various electrical, electronic, computer, and communication systems have a multiprocessor structure for processing various commands and performing a plurality of functions in order to improve the efficiency of the system.
    Such a multiprocessor system uses one processor as a master and the other processor as a slave, and the arbitration unit allows one master memory device to be shared between the master and slave processors, and for each processor to boot. There is a way to use all processors as masters by separating and interfacing buses with memory devices using DPRAM or buffers.
    However, multiprocessor systems that use all processors as masters must use one-to-one bootable memory elements for each processor, and must use memory devices such as buffers or buffers to interface and use the bus associated with each processor. As a result, the overall circuit is complicated and the processing time of each processor is delayed, which adversely affects the performance of the entire system.
    SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to allow a multiprocessor operating as a master to use the same bootable memory element and to equalize bus usage rights to each processor so that the buses can be used jointly. To provide an arbitration device.
    In order to achieve the above object, the present invention provides a processor arbitration apparatus comprising: a memory device in which a booting program for initial driving of a first and a second processor is stored; An arbitration unit for arbitrating a bus use right to sequentially access a boot program stored in a memory device when a bus use request occurs simultaneously with initial driving of the first and second processors; And an address conversion unit connected to any one of the first and second processors to convert an address output from the first or second processor to access a booting program stored in the memory device.
    1 is a block diagram of a processor arbitration apparatus according to the present invention;
    2 is a partial timing diagram of a processor arbitration apparatus according to the present invention.
    <Description of the symbols for the main parts of the drawings>
    10: first processor 20: second processor
    30: arbitration unit 40: address translation unit
    50 memory element 60 bus
    Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.
    1 is a block diagram of a multiprocessor system according to an embodiment of the present invention, wherein the first and second processors 10 and 20, the arbitration unit 30, the address conversion unit 40, the memory element 50, And a bus 60.
    The first and second processors 10 and 20 acting as masters generate addresses necessary to access a booting program stored in the memory device 50. The address conversion unit 40 connected to the second processor 20 includes an inverter circuit and performs a function of converting an address generated in the second processor 20 by the inverter circuit.
    The arbitration unit 30 arbitrates the first processor 10 and the second processor 20, which operate as a master, to access the bootable program stored in the memory device 50 by sharing the bus 60. The arbitration unit 30 arbitrates to equally use the bus 60 in a time division manner.
    That is, when an initialization signal is applied from an external operator in the first processor 10 and the second processor 20, an address that loads a stack pointer to read a booting program in the memory device 50, that is, "0". Output an address with a value.
    The address having the zero address "0" value output from the first processor 10 is directly output to the memory device 50 through the bus 60 and the zero address "0" value output from the second processor 20 is output. The address having the same is provided to the memory element 50 through the address conversion section 40.
    At this time, the address conversion unit 40 inverts the address output from the second processor 20 by the inverter circuit to an address having a value of “1111” and provides the address to the memory device 50 through the bus 60. Therefore, the address for loading the program counter and the stack pointer into the memory device 50 is prevented from overlapping.
    The memory device 50 stores a booting program required by the first and second processors 10 and 20 to initialize.
    The operation of the processor arbitration apparatus according to the present invention will be described in more detail with reference to the timing diagram shown in FIG. 2.
    If an error occurs in the first and second processors 10 and 20 due to a system failure while the first and second processors 10 and 20 operate as masters and process various commands, both may operate as masters. When reset by the operator so that a reset signal as shown in FIG. 2A is applied to the first and second processors 10, 20.
    When a reset signal (FIG. 2A) is applied from the outside, the first and second processors 10 and 20 respectively have an address for loading a stack pointer to read a booting program in the memory element 50, i. A bus occupancy request signal as shown in Figs. 2B and 2C is output while simultaneously outputting an address having a value. An address having a "0" value output from the first processor 10 is directly input to the memory device 50 through the bus 60, while an address having a "0" value output from the second processor 20. Is converted into an address having a value of " 1111 " via the address conversion unit 40 and then input to the memory element 50 through the bus 60.
    At this time, the arbitration unit 30 equally assigns the bus 60 authority to the first and second processors 10 and 20 in a time division manner, and assigns the priority to the first and second processors 10 and 20. Arbitrate to equalize bus usage rights.
    By the arbitration operation of the arbitration unit 30, a bus grant signal as shown in FIGS. 2D and 2F is provided to the first and second processors 10 and 20. FIG.
    That is, the first processor 10 receiving the bus acknowledgment signal (FIG. 2D) by the arbitration operation of the arbitration unit 30 receives an address having a value of “0” through the bus 60 to load the stack pointer. It transfers to the memory element 50 and reads the booting program (FIG. 2E) stored in the memory element 50, so that it is initialized and operated.
    Next, the second processor 20 which has received the bus acknowledgment signal (FIG. 2F) by the arbitration operation of the arbitration unit 30 sends an address having a value of "0" to load the stack pointer. To send. The address conversion unit 40 converts an address having a value of "0" into an address having a value of "1111", transmits the address to the memory device 50 through the bus 60, and stores the boot stored in the memory device 50. Since the program (FIG. 2G) is read out, it initializes and operates.
    As described above, the present invention shares not only the high performance and resource utilization by sharing a bootable memory device, but also makes it possible to utilize all useful functions as a master when all processors are used as masters.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] A processor arbitration apparatus of a multiprocessor system having at least two first and second processors operating as a master, the apparatus comprising:
    A memory device in which a booting program for initial driving of the first and second processors is stored;
    An arbitration unit arbitrating a bus usage right to sequentially access a boot program stored in the memory device when a bus use request occurs simultaneously with initial driving of the first and second processors;
    And an address conversion unit connected to any one of the first and second processors to convert an address output from the first or second processor to access a booting program stored in the memory device. Processor Arbitration Device.
    [2" claim-type="Currently amended] The method of claim 1,
    And the arbitration unit arbitrates a bus usage right to the first and second processors in a time division manner.
    [3" claim-type="Currently amended] The method of claim 1,
    And the arbitration unit arbitrates to selectively grant bus usage rights to assign priority to the first and second processors.
    [4" claim-type="Currently amended] The method of claim 1,
    And the address conversion unit comprises an inverter circuit.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-05-30|Application filed by 강병호, 대우통신 주식회사
    1998-05-30|Priority to KR1019980020030A
    1999-12-15|Publication of KR19990086858A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980020030A|KR19990086858A|1998-05-30|1998-05-30|Processor arbitration device|
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