• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention discloses a boosting circuit. The circuit includes a plurality of MOS transistors having a common connected gate electrode and a drain electrode connected in series between a power supply voltage applying terminal and an output terminal, and a common point of the gate electrode and the drain electrode of each of the even-numbered MOS transistors among the plurality of MOS transistors. A plurality of capacitors are connected between the clock signal and between the common and inverted clock signals of the gate electrode and the drain electrode of each of the odd-numbered MOS transistors, and a MOS capacitor connected between the output terminal and the ground voltage. Therefore, stable high voltage can be generated.
    公开号:KR19990032217A
    申请号:KR1019970053200
    申请日:1997-10-17
    公开日:1999-05-15
    发明作者:이흥우
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Boost circuit
    The present invention relates to a boost circuit, and more particularly to a boost circuit for use in a semiconductor memory device.
    In general, semiconductor IC products use a single power supply, but some products use multi-level power supplies. Integrated circuit products using these multilevel power sources generate and use power from outside and inside the product.
    Generating and using multiple levels inside an integrated circuit with a single power source is very convenient for the user. A single power supply uses 5V or less power, and electrically erasable programmable read only memory (EEPROM) internally provides a voltage of about 20V, much higher than the power supply to the integrated circuit. Generated from and used to write and erase cells.
    However, during the generation of about 20V, an unstable fixed voltage is boosted, causing the EEPROM cell to be incompletely written / erased, resulting in destruction of the internal transistor and voltage drop due to unstable high voltage.
    The high voltage boosting circuit is a transistor in which a charging capacitor, a drain electrode and a gate are connected in series, and is designed so that the voltage rise is limited by the field break-down voltage of the transistor. However, the field break-down characteristic of the small transistor has a curve in which the break-down voltage changes with the current, so that the dispersion of the limit of the high voltage is large, so that it does not have a stable high voltage.
    This not only damages the circuit through which the high voltage passes, but also affects the characteristics of the EEPROM cell, thereby reducing its reliability.
    It is an object of the present invention to provide a boosting circuit capable of generating a stable high voltage.
    According to an embodiment of the present invention, a boost circuit includes a plurality of MOS transistors having a gate electrode and a drain electrode connected in common between a power supply voltage supply terminal and an output terminal, and even-numbered MOS transistors among the plurality of MOS transistors. A plurality of capacitors connected between the common point and the clock signal of each gate electrode and the drain electrode and between the common point and the inverted clock signal of each of the gate and drain electrodes of the odd-numbered MOS transistors, and connected between the output terminal and the ground voltage. An MOS capacitor is provided.
    1 is a circuit diagram of a conventional boost circuit.
    FIG. 2 is a curve showing the change in current versus break-down voltage of the circuit shown in FIG.
    FIG. 3 shows field break-down of the circuit shown in FIG.
    4 is a circuit diagram of a boost circuit of the present invention.
    FIG. 5 is a curve showing the change in current versus break-down voltage of the circuit shown in FIG.
    FIG. 6 shows the junction break-down of the circuit shown in FIG.
    Hereinafter, a description will be given of a conventional boosting circuit before explaining the boosting circuit of the present invention with reference to the accompanying drawings.
    1 is a circuit diagram of a conventional boosting circuit, in which a plurality of NMOS transistors M0, M1, M2, and M3 having a gate electrode and a drain electrode connected in common between a power supply voltage Vcc and an output voltage Vpp are connected in series. , ..., M (n-1), Mn), and each of the even-numbered NMOS transistors among the NMOS transistors M0, M1, M2, M3, ..., M (n-1), Mn. Capacitors C0, C2, ... C (n-1) connected between the common electrode of the gate electrode and the drain electrode and the clock signal CK, and odd-numbered NMOS transistors M1, M3, ..., Mn The capacitors C1, C3, ..., Cn are connected between the common point of each gate electrode and the drain electrode and the inverted clock signal CKB.
    The boosting circuit configured as described above is sequentially charged using the clock signal CK and the inverted clock signal CKB to boost the output voltage Vpp to 20V or more. During a write operation of the EEPROM, the boosted voltage is supplied to the gate electrode of the cell to store data from the data line in the cell. In the read operation, the power supply voltage Vcc is applied to the gate electrode of the cell as it is to transfer data stored in the cell to the data line.
    FIG. 2 is a curve showing a change in current versus break-down voltage of the circuit shown in FIG. 1, and FIG. 3 shows an output voltage (Vpp) limited field break-down of the circuit shown in FIG. The -down characteristic causes the breakdown voltage to change with current. Therefore, in order to generate a stable breakdown voltage due to a constant break-down voltage in the current change, it is necessary to design a transistor having a very large width, in which case there is a problem that the chip size becomes very large.
    In order to generate a stable high voltage, the present invention does not limit the boosted high voltage to the break-down, but is limited by the junction break-down of the transistor having little effect of the break-down according to the current change. It was.
    Fig. 4 is a circuit diagram of the boosting circuit of the present invention, in which an NMOS capacitor C is added between the output voltage Vpp and the ground voltage GND of the conventional circuit shown in Fig. 1. That is, the source and drain electrodes of the NMOS capacitor C are commonly connected to the output voltage Vpp, and the gate electrode is further connected to the ground voltage.
    In such a configuration, breakdown occurs at the junction of the channel portion of the transistor so that the breakdown voltage is not controlled by the field breakdown of the conventional boost circuit, but instead the breakdown is caused by the junction breakdown of the added NMOS capacitor. The voltage is controlled.
    FIG. 5 is a curve showing a change in current versus breakdown voltage of the circuit shown in FIG. 4, and it can be seen that the breakdown voltage is constant with respect to the change in current. FIG. 6 shows the output voltage (Vpp) limiting junction break-down of the circuit shown in FIG. 4, showing that break-down occurs at the junction of the channel portion of the NMOS capacitor.
    In the circuit of the present invention, the high voltage is limited by the junction break-down of the NMOS capacitor, which not only damages the circuit of the rear stage but also obtains a stable high voltage in process changes, thereby improving the characteristics and reliability of the EEPROM cell.
    The boosting circuit of the present invention generates a stable high voltage and does not damage the circuit of the rear stage, and can improve the characteristics and reliability of the EEPROM cell.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] A plurality of MOS transistors having a common connected gate electrode and a drain electrode connected in series between a power supply voltage supply terminal and an output terminal;
    A plurality of capacitors connected between the common and clock signals of the gate electrode and the drain electrode of each of the even-numbered MOS transistors, and the common and inverted clock signals of the gate and drain electrodes of each of the odd-numbered MOS transistors. field; And
    And a MOS capacitor connected between the output terminal and the ground voltage.
    [2" claim-type="Currently amended] 2. The boost circuit of claim 1, wherein the plurality of MOS transistors are NMOS transistors.
    [3" claim-type="Currently amended] The boost circuit of claim 1, wherein the MOS capacitor is an NMOS capacitor having a source electrode and a drain electrode connected to the output terminal, and a gate electrode connected to the ground voltage.
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    同族专利:
    公开号 | 公开日
    KR100470991B1|2005-07-11|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-17|Application filed by 윤종용, 삼성전자 주식회사
    1997-10-17|Priority to KR1019970053200A
    1999-05-15|Publication of KR19990032217A
    2005-07-11|Application granted
    2005-07-11|Publication of KR100470991B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970053200A|KR100470991B1|1997-10-17|1997-10-17|Boost circuit|
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