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    • 专利摘要:
    The invention describes a method of forming spacers (150) of a gate (120) of a field effect transistor (100), the gate (120) including flanks (125) and a peak (126) and being located above a layer (146) of a semiconductor material, the method comprising a step (410) of forming a dielectric layer (152) overlying the gate of the transistor, the method comprising: - after the step of forming the dielectric layer (152), at least one step of modifying (430) said dielectric layer (152) by ion implantation while retaining portions of the dielectric layer (152) covering the flanks (125); ) of the grid (120) unmodified over their entire thickness; the ions being ions based on hydrogen (H) and / or on the basis of helium (He); at least one step of removing (440) the modified dielectric layer by means of a selective etching of said dielectric layer; the step of removing (440) the modified dielectric layer comprises a wet etching based on a solution comprising hydrofluoric acid (HF) diluted to x% by mass, with x≤0.2 and having a lower or equal pH at 1.5.
    公开号:FR3052911A1
    申请号:FR1655739
    申请日:2016-06-20
    公开日:2017-12-22
    发明作者:Olivier Pollet；Maxime Garcia-Barros；Nicolas Posseme
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    A titre de comparaison, le tableau suivant donne un exemple des épaisseurs consommées au bout d’une durée de 600 secondes par une solution de HF diluée à 0.1% et présentant un pH de 2.43:
    Ainsi, la sélectivité (rapport des vitesses de gravure) de la gravure du SiN modifié par rapport au SiN non modifié est de 11.2.
    De manière encore plus marquée, la sélectivité de la gravure du SiN modifié par rapport au Si02 est de 33.7. Cela permet de contrôler de manière très précise la gravure des portions modifiées 158 de la couche diélectrique 152 par rapport aux couches en oxyde de silicium telles que les tranchées d’isolation 117, le masque dur 124 et l’oxyde de grille par exemple. A titre de comparaison, les sélectivités de la gravure du SiN modifié par rapport au SiN non modifié et au Si02 sont respectivement de 10.5 et 4.1 pour une solution de HF diluée à 0.1% et présentant un pH de 2.43:
    La mise en présence est réalisée de préférence en plongeant l’empilement comprenant la couche diélectrique 152 dans un bain de la solution à base d’HF. De manière plus générale, le procédé pourrait être mis en oeuvre dans tout équipement permettant la mise en contact d’une solution liquide avec une plaque. Notamment on pourrait le faire par aspersion de liquide ou en immersion. L’équipement utilisé pour cette étape de retrait peut par exemple être tout équipement de gravure ou nettoyage humide acceptant des pH faible et en particulier inférieur à 1.7 et de préférence inférieur à 1.
    La gravure humide permet par exemple de retirer une épaisseur de la couche diélectrique modifiée 158 comprise entre 1 nanomètre et quelques dizaines de nanomètres. L’arrêt de la gravure se fait au temps. Il se fait de préférence sur la couche diélectrique non modifiée 152 ou sur le silicium monocristallin de la couche 146 ou encore sur le masque dur 124 au sommet 126 des grilles 120 ou sur le sommet des tranchées d’isolation 117. À l’issue de cette étape de retrait 440 il ne reste donc de la couche diélectrique 152 initiale que des motifs verticaux, essentiellement sur les flancs 125 de l’empilement de couches qui forment la grille 120. Ils constituent les espaceurs 150 de grille du transistor.
    La figure 2d illustre l’étape 460 de formation des zones de drain et de source d’un transistor par exemple de type FDSOI. A l’issue de la dernière ou unique étape de retrait de la couche diélectrique modifiée 158, c'est-à-dire lorsqu’on a fini de l’enlever sur toutes les surfaces horizontales, on procède à une opération de nettoyage dite « nettoyage humide » le plus souvent qualifiée par son vocable anglais de « wet clean ».
    On peut ensuite procéder à la formation 470 des électrodes de source et de drain 110. Comme on l’a déjà mentionné, le dopage qui va délimiter source et drain et donc la longueur du canal 132 peut se faire par implantation ionique avant qu’on ne procède à une croissance épitaxiale sur ces zones afin d’augmenter leur section et diminuer leur résistance. Si le dopage est effectué avant croissance épitaxiale, comme représenté sur la figure 2d, le procédé est dit être « extension first » vocable anglais utilisé pour indiquer que les extensions (de source et de drain sous les espaceurs) sont réalisées en premier, c'est-à-dire avant croissance épitaxiale. Dans le cas contraire qui est dit être « extension last », on procède directement à l’étape de croissance épitaxiale sans dopage préalable. Le dopage des zones source/drain ne se fait qu’après croissance épitaxiale de ces zones. Dans le cas de transistors à canal de type n (nMOS), les dopants implantés sont typiquement l’arsenic (As) ou le phosphore (P). Pour les transistors à canal de type p (pMOS) les dopants sont le bore (B) ou le difluorure de bore (BF2).
    Le résultat est illustré sur la figure 2d qui montre les zones source/drain dopées 114 avant croissance épitaxiale des zones source/drain surélevées 116.
    Avantageusement, la grille du transistor est située sur un empilement de couches formant un substrat élaboré de type silicium sur isolant (SOI). De préférence, elle est disposée directement au contact de la couche formant le canal de conduction. Avantageusement, l’utilisation de l’invention avec un tel substrat SOI permet de préserver l’intégrité de la couche superficielle de très faible épaisseur qui forme le canal de conduction d’un transistor formé à partir d’un substrat SOI.
    La figure 3 illustre un graphe représentant la concentration, plus précisément la fraction molaire, des espèces fluorées dans la solution en fonction du pH de la solution.
    On constate sur ce graphe que dans une zone 32 dont le pH est entre 2 et 4, les concentrations molaires en HF et en ions F'sont importantes.
    Lorsque l’on rajoute du HCl pour augmenter l’acidité de la solution et que le pH devient inférieur à 1.7, la concentration molaire en ions F' est très fortement réduite et la concentration molaire en HF est très importante. Cela s’explique par l’association des ions H"" du HCl avec les ions F' pour former des molécules de HF. Cela apparaît clairement dans la zone 31 du graphe.
    Cr, dans le cadre du développement de la présente invention il s’est avéré que ces ions F'gravent le nitrure modifié avec une sélectivité moindre que les molécules de HF.
    Cn notera que sur ce graphe, l’abréviation M est une abréviation du système international d’unités qui désigne une concentration en mol/L. La droite verticale notée pH pour 0.05M désigne le pH de la solution de HF de concentration 0.05M à l’équilibre, c’est-à-dire si l’on a uniquement le HF en solution dans l’eau sans chercher à modifier le pH. A noter que la concentration molaire de 0.05M correspond à la concentration massique 0.1%, le pH à l’équilibre d’une telle solution est égal à 2.25.
    La figure 4 résume les étapes du procédé de l’invention destinées à former des espaceurs et qui n’induisent peu ou aucun des défauts décrits notamment dans les figures 1b, 1c et 1d pour la réalisation de transistors, par exemple mais non limitativement de type FDSCI.
    Après dépôt 410 par LPCVD d’une couche diélectrique 152 uniforme sur toutes les surfaces des dispositifs en cours de fabrication, on procède au retrait de ladite couche diélectrique modifiée 158 sur les surfaces qui ne sont pas destinées à former les espaceurs. Ce retrait comprend plusieurs étapes, dont les étapes 430, 440 et optionnellement l’étape 420 préalable.
    Ainsi, optionnellement, on procède à une gravure « principale », de préférence une gravure humide conventionnelle isotrope 420 de la couche diélectrique modifiée 158. Dans le cadre de mises en œuvre spécifiques de l’invention, on peut décider de maintenir ou non l’étape de gravure principale 420, les étapes suivantes s’appliquent alors soit sur la couche diélectrique 152 telle que déposée ou sur la couche restante après qu’une gravure principale a été préalablement effectuée comme dans le procédé standard de gravure des espaceurs.
    Comme montré sur la figure 2b, l’étape suivante 430 consiste à modifier de façon anisotrope tout ou partie 154 de la couche diélectrique restante 152 par implantation d’ions légers.
    Suivant les applications du procédé de l’invention on pourra préférer utiliser un graveur plasma pour l’implantation plasma notamment pour les raisons suivantes : le coût de l’appareillage est moins élevé, les temps de cycle de fabrication peuvent être plus courts puisque l’étape de gravure principale 420 et celle de modification 430 de la couche diélectrique 152 peuvent alors se faire dans le même appareillage sans remise à l’air des dispositifs en cours de fabrication. On notera en particulier que l’étape de modification 430 peut se pratiquer de nombreuses façons différentes en adaptant toutes sortes de moyens couramment employés par l’industrie de la microélectronique, tel qu’à l’aide de tout type graveur, par exemple dans un réacteur ICP de l’anglais « Inductively Coupled Plasma » c'est-à-dire « plasma à couplage inductif », ou dans un réacteur de type CCP de l’anglais « Capacitively Coupled Plasma » c'est-à-dire « plasma à couplage capacitif » qui permet de contrôler l’énergie des ions. On peut aussi utiliser un type de plasma dit par immersion couramment utilisé pour pratiquer une implantation d’espèces en surface d’un dispositif en cours de fabrication.
    Pour choisir les paramètres d’implantation l’homme du métier, afin de déterminer le comportement du matériau à graver dans le type de graveur plasma choisi, procédera préalablement de préférence à des essais « pleine plaque » afin d’établir des courbes de comportement. Il en déduira les paramètres de l’implantation, en particulier l’énergie et la dose d’ions, c'est-à-dire le temps d’exposition, à utiliser pour atteindre l’épaisseur voulue de matériau à modifier.
    Le tableau ci-après donne des conditions typiques de mise en œuvre de l’étape 430 de modification de la couche diélectrique 152 dans le cas d’utilisation d’un réacteur de gravure plasma standard. Ces conditions sont largement dépendantes de l’épaisseur à modifier dans la couche diélectrique 152. Ceci n’est qu’un exemple particulier de mise en œuvre de l’étape 430 de modification de la couche à graver.
    La possibilité de puiser la source et/ou le bias permet également d’avoir un meilleur contrôle sur la profondeur d’implantation pour de faibles épaisseurs.
    L’étape suivante 440 est celle où l’on pratique le retrait par gravure de la couche modifiée ou tout au moins de l’épaisseur modifiée de la couche diélectrique modifiée 158. Pour éviter les problèmes des procédés traditionnels de gravure des espaceurs décrits dans les figures 1b à 1d, il est nécessaire que la gravure de la couche diélectrique modifiée 158 soit la plus sélective possible par rapport au silicium notamment afin de ne pas attaquer le silicium monocristallin des zones source/drain avec les inconvénients et conséquences décrits précédemment.
    Le retrait 440 de la couche diélectrique modifiée 158 comprend la gravure humide à base d’une solution comprenant du HF et dont le pH est inférieur à 1.7. L’épaisseur de la couche diélectrique modifiée 158 est typiquement comprise dans une gamme de valeurs allant de 1 nanomètre à quelques dizaines de nanomètres. Les temps de gravure peuvent aller de quelques secondes à quelques minutes. Ils sont évidemment directement dépendants de l’épaisseur de la couche diélectrique qui a été modifiée 158.
    Les étapes suivantes 460, 470 du procédé ne sont pas différentes de celles correspondantes des procédés standard où l’on réalise possiblement les extensions des zones source/drain 460 par implantation ionique de dopants avant croissance épitaxiale des source/drain surélevés 470 de transistors par exemple de type FDSOI.
    Exemple détaillé non limitatif A titre d’exemple non limitatif de l’invention, on dépose une couche de nitrure de silicium (SiN) de 15nm destinée à former un espaceur 125.
    Pour modifier une épaisseur de 12 nm de nitrure de silicium dans un graveur de type ICP (TCP RF), en continu, on applique une tension de 250V (tension de polarisation) pendant une durée de 60 secondes pour un plasma formé à partir d’un composant à base d’hydrogène (H) dont le débit est de 48 sccm. Dans ce cas, la pression utilisée est de 10 mTorr et la puissance de la source de 500W.
    Par exemple pour retirer lOnm de SiN modifié, on expose ce dernier à une solution de HF diluée à 0.1% dont le pH est de 0.93 pendant 12 minutes (720 secondes).
    Au vu de la description qui précède, il ressort clairement que l’invention permet non seulement un contrôle des dommages pouvant être engendrés suite à une implantation ionique, mais également une amélioration du retrait de la couche diélectrique modifiée 152, en proposant un procédé présentant une meilleure sélectivité de gravure entre la couche diélectrique modifiée et la couche diélectrique non modifiée d’une part, entre la couche diélectrique modifiée et la couche en oxyde de silicium et entre la couche diélectrique modifiée et la couche en un matériau semi-conducteur d’autre part.
    Avantageusement, la présente invention propose une sélectivité infinie de la couche diélectrique modifiée. Ainsi, la présente invention permet un meilleur contrôle des dimensions critiques. Le procédé selon la présente invention permet en outre une gravure sélective de la couche diélectrique modifiée au regard d’autres couches non modifiées, évitant tout risque de consommer tout ou partie d’une couche à base de nitrure de silicium ou une couche à base d’oxyde de silicium. En particulier le masque dur recouvrant la grille et les tranchées d’isolation en oxyde silicium ne sont pas altérées par la gravure des espaceurs. L’invention n’est pas limitée aux seuls modes et exemples de réalisation décrits ci-dessus, mais s’étend à tous les modes de réalisation entrant dans la portée des revendications.
    TECHNICAL FIELD OF THE INVENTION
    The present invention generally relates to field effect transistors (FETs) and more particularly to the realization of gate spacers of the metal-oxide-semiconductor (MOSFET) type transistors.
    STATE OF THE ART
    Figure 1a is a sectional view of an example of transistor 100 in progress. It contains the source and drain areas 110, generally designated source / drain zones, since they are very generally perfectly symmetrical and can play both roles depending on the electric polarizations that are applied to the transistor. The grid conventionally consists of a stack of layers 120, a large part of which is most often composed of polycrystalline silicon 123. The formation of the source and drain zones is typically done by ion implantation 105 of dopants in the zones 110, the grid 120 serving as a mask, thus preventing doping of the area of the MOSFET transistor in which, depending on the voltages applied on the gate, will be able to develop the channel 130 of conduction between source and drain.
    In this example illustrated, the substrate 140 is of the silicon on insulator (SOI) type. It comprises a thin surface layer of monocrystalline silicon 146 resting on a continuous layer of silicon oxide 144, called buried oxide or BOX, acronym for "buried oxide layer". The solidity and the mechanical rigidity of the assembly are ensured by the layer 142 which constitutes the body of the SOI substrate, often described as "bulk".
    The spacers 150, typically made of silicon nitride (SiN), will allow in particular the implementation of a technique called "Source and Drain elevated". In order to maintain low electrical resistance to access the source and drain electrodes, despite the size reduction of the transistors, it was indeed necessary to increase their section. This is obtained by selective epitaxy of the source / drain zones 110. During this operation, the initial layer of monocrystalline silicon 14 will be grown locally 112. It is then necessary to protect the grid areas to prevent the growth from also being made from polycrystalline silicon 123 of the grid. It is, among other things, the role of spacers to ensure this function. They also perform a role of preserving the gate during siliciding of the contacts (not shown) which is then performed for the same purpose in order to reduce the series resistance of access to the electrodes of the transistor.
    The formation of the spacers 150 has become a crucial step in the formation of transistors that now reach dimensions that are commonly measured in nanometers (nm = 10® meters) and which are generally of decananometric sizes. The spacers are made without involving any photoengraving operation. They are self-aligned on the gate 120 from the deposition of a uniform layer of silicon nitride 152 (SiN) which then undergoes a very strongly anisotropic etching. This etching of the SiN preferentially attacks the horizontal surfaces, that is to say all the surfaces that are parallel to the plane of the SOI substrate. It leaves in place, imperfectly, only the vertical portions of the layer 152, those substantially perpendicular to the plane of the substrate, in order to obtain in practice the patterns 150 whose ideal shape is often rectangular.
    With the known solutions, the size reduction of the transistors makes it very difficult to obtain spacers that fully play their role of isolation and do not induce defects in the production of transistors from SOI substrates. Indeed, it has been found that several types of defect such as those mentioned below appear during the etching of the spacers using one or other of the known methods of anisotropic etching.
    Figures 1b, 1c and 1d each illustrate a type of defect observed.
    In particular, a type of etching is used which is said to be "dry" and which is implemented using a process which is most often referred to by its acronym RIE, of the English "reactive-ion eching", c 'ie reactive ion etching'. It is an etching process in which a plasma is formed in a confined space that reacts physically and chemically with the surface of the wafer to be etched. In the case of the etching of a silicon nitride layer, which is, as we have seen, a material that is usual for the production of spacers, the reactive gas is typically methyl fluoride (CH 3 F) which is reacted. with the material to be etched by also introducing oxygen (02). An etching plasma based on fluorine chemistry is thus formed and often designated by its constituents: CH3F / 02 / He. The advantage of this type of etching is that it is fairly anisotropic and allows to control sufficiently the profile of the spacers 150 even if one can not obtain in practice the ideal rectangular shape. The disadvantage of this type of etching is that the etch selectivity of the underlying silicon is however limited. The selectivity, that is to say the ratio of the etching rates between the silicon nitride and the silicon is of the order of 10 and can reach a maximum of 15 depending on the conditions of formation of the plasma (the nitride is etched 10 to 15 times faster than silicon).
    We also use so-called "wet" etchings based on phosphoric acid (H3PO4) that do not allow to control the profile of the spacers since the etching is essentially isotropic in this case. Note that this type of engraving is also called "wet cleaning" translation of the English "wet clean".
    FIG. 1b illustrates a first problem which is related to the insufficient etching selectivity which exists during dry etching of the CH3F / 02 / He type between the silicon nitride and the silicon of the surface layer 146. The result is that a significant fraction of the thin surface layer of monocrystalline silicon 146 of the SOI substrate can then be partially consumed 147 during the anisotropic etching of the nitride. As previously mentioned, the surface layer 146 is chosen to be thin in order to improve the electrical characteristics of the transistors. It is typically less than 10 nm. The remaining thickness 145 may be very small. Under these conditions the ion implantation 105 to form the source and drain zones 110 which will follow is likely to be very damaging for the remaining monocrystalline silicon. The implantation energy of the dopants may be sufficient to cause complete amorphization 149 of the single-crystal silicon, which will then in particular compromise the next epitaxial growth step 112 intended to form the raised source / drain. Growth from a partially or fully amorphous silicon layer will create many defects in the epitaxial layer.
    FIG. 1c illustrates another problem where there is no significant consumption of the silicon of the surface layer 146 but there is formation of "feet" 154 at the bottom of the remaining silicon nitride patterns on the sides of the gate after etching . The consequence is that the transition 114 of the junctions which are formed after ion implantation doping 105 of the source and drain zones 110, with the zone of the channel 130, is much less abrupt than when the spacers do not have feet as represented in FIG. previous figures. The presence of feet 154 affects the electrical characteristics of the transistors. It will be noted here that the formation or not of feet at the bottom of the spacers and the consumption or not of silicon of the silicon surface layer 146 of the SOI substrate, described in the previous figure, are antagonistic adjustment parameters of the etching which require that a compromise can be found for which, ideally, no feet are formed and the surface layer of silicon is not attacked significantly.
    Figure 1d illustrates a third problem that occurs when etching produces excessive erosion of the spacers in the upper portions of the grids and exposes the polysilicon 123 in these areas 156. The consequence is that the subsequent epitaxial growth 112 to form the raised source / drain will also occur at these locations, as well as silicidation of parasitic contacts, which may cause short circuits between electrodes. Indeed, the etching of the spacers requires that the etching time is adjusted to etch, for example, 150% of the deposited nitride thickness. That is, a 50% overgraft is performed in this example to account for the non-uniformity of the deposit, or the etching operation itself, at a wafer. Thus, in some parts of the slice we can see that there is a too sharp overgrading that exposes the grid areas 156. This type of defect is also called "faceting". Other solutions have been proposed in documents US2014 / 0273292 and FR12 / 62962. These solutions provide a step of modification by implantation of a silicon nitride layer to modify it on either side of the gate, followed by a step of removing the modified silicon nitride layer.
    In the FR12 / 62962 solution, the step of removing the modified nitride layer can be carried out by wet cleaning using hydrofluoric acid (HF). The disadvantage is that wet HF cleaning does not allow selective removal of the modified nitride layer from the unmodified nitride layer. The selectivity to the unmodified nitride layer is, for example, 7 (for a 1% HF concentration).
    Moreover, hydrofluoric acid is a chemical compound, one of the main properties of which is to etch silicon oxide, so this method is intrinsically non-selective to the silicon oxide layer forming the hard mask as well as the trenches. of insulation (in English acronym STI for "shallow trench isolation"). The selectivity of this oxide layer to HF is, for example, 1 (for a concentration of HF of 1%).
    The object of the present invention is to provide a method of forming spacers which would eliminate or limit at least some of the defects in the production of transistors, such as the consumption or the alteration of the semiconductor material (ie Si, SiGe) of the active layer underlying the layer to be etched, the formation of "feet" at the bottom of the patterns on the sides of the gate of a transistor, the consumption of a hard mask or an isolation trench based on oxide.
    Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated.
    SUMMARY OF THE INVENTION
    To achieve this objective, one aspect of the present invention relates to a method of forming spacers of a gate of a field effect transistor, the gate having flanks and a top and being located above a layer. in a semiconductor material, the method comprising a step of forming a dielectric layer covering the gate of the transistor, the method comprising: - after the step of forming the dielectric layer, at least one step of modifying said layer dielectric electrode by implantation of ions at least in portions of the dielectric layer which are located on one vertex of the gate and on either side of the gate and which are perpendicular to the sidewalls of the gate while maintaining portions of the layer dielectric covering the sides of the grid unmodified or unmodified over their entire thickness; the ions being ions based on hydrogen (H) and / or on the basis of helium (He); at least one step of removing the modified dielectric layer by selectively etching said layer-modified dielectric layer in a semiconductor material and vis-à-vis the non-dielectric layer changed. The step of removing the modified dielectric layer comprises wet etching based on a solution comprising hydrofluoric acid (HF) diluted to x% by weight, with x <0.2 and having a pH less than or equal to 1.5.
    It has been found that with these shrinkage conditions, in particular the association between this specific acidity of the solution and this specific dilution of HF, the modified dielectric layer is etched in a particularly selective manner with respect to the layer. in a semiconductor material and vis-à-vis the unmodified dielectric layer. Thus, it avoids or at least reduces the consumption or the alteration of the semiconductor material (ie Si, SiGe) of the active layer underlying the layer to be etched and the formation of "feet" at the bottom of the patterns on the flanks of the gate of a transistor.
    Moreover, particularly surprisingly, this etching makes it possible to increase very significantly the selectivity of the etching of the modified dielectric layer with respect to silicon oxide-based materials, generally designated SiOy in the present invention. patent application, where y is greater than or equal to 1.
    This improved selectivity is very advantageous since often a hard mask on the top of the grid or an isolation trench, based on SiOy, are present during the etching step.
    It follows that the hard mask or the isolation trenches are not affected by the etching of the spacers. They can therefore fully play their roles.
    Usually such acidic pHs are not used because they are not of interest in the conventional SiOy etching framework such as SiO 2.
    The usual approach of a person skilled in the art would have led him to increase the pH in order to improve the selectivity and for a given concentration of HF. In any case the person skilled in the art would have found no incentive to: both lower the pH to a value less than or equal to 1.5 and dilute the HF to a dilution less than or equal to 0.2. He could not have foreseen this surprising result procured by the invention.
    However, this surprising advantage provided by the invention lies in this specific combination of this pH and this dilution.
    For example, with the process according to the invention, a selectivity of the etching with respect to the silicon dioxide is obtained such that for a thickness e1 of etched modified nitride, it is not possible to engrave at the same time that a thickness e1 / 33.7 of silicon dioxide.
    Thus, the invention makes it possible to obtain spacers based on a dielectric material while reducing or even eliminating at least some of the problems of the known and previously mentioned solutions.
    Optionally, the method may further have at least any of the features and steps below.
    The solution used in the removal step is obtained by mixing a dilute HF solution and a component to reduce the pH of the HF solution. This component is, for example, HCl. Alternatively it may be H2SO4 (sulfuric acid), HNO3 (nitric acid). This list is not exhaustive, any acid not generating species likely to engrave one of the materials considered could be suitable in the context of the invention.
    The solution can be obtained by mixing only a solution of HF diluted in H2O water and HCl. Alternatively it may also contain H2SO4, or HNO3.
    The solution could also be prepared from concentrated HF diluted in H 2 O plus HCl or H 2 SO 4 or HNO 3.
    According to one embodiment, the pH is less than or equal to 1.3, preferably less than or equal to 1. According to one embodiment, the pH is strictly less than 1.
    According to one embodiment, the percentage of HF is between 0.02% and 0.2% by weight. According to one embodiment, the percentage of HCl is between 0.3% and 3% by weight.
    According to one embodiment, x <0.15, preferably x <0.1. According to one embodiment is substantially equal to 0.1. According to an embodiment x <0.1.
    According to one embodiment, the method comprises, before the step of removing a step of forming a mask (124) located on the top of the grid, said mask being based on silicon oxide SiOy being an integer greater than or equal to 1, and preferably based on silicon dioxide (SiO 2).
    According to one embodiment, the method comprises, before the step of removing a step of forming an isolation trench extending through the layer of a semiconductor material, said isolation trench being based on silicon oxide SiOy, y being an integer greater than or equal to 1, and preferably based on silicon dioxide (SiO 2).
    According to one embodiment, the dielectric layer is formed of one or more dielectric materials whose dielectric constant k is less than or equal to 7.
    According to one embodiment, the dielectric layer is a nitride layer, preferably a silicon nitride (SiN) layer. Alternatively the dielectric layer is a layer based on silicon (Si). According to one embodiment, the material of the dielectric layer is taken from: SiC, SiCN, SiCBN.
    According to one embodiment, the method comprises a single modification step carried out so as to modify the dielectric layer throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer in all its thickness on the surfaces perpendicular to this plane.
    According to one embodiment, the layer made of a semiconductor material is selected from: silicon (Si), germanium (Ge), silicon-germanium (SiGe).
    According to one embodiment, the step of modifying said dielectric layer by ion implantation comprises placing the dielectric layer in the presence of a plasma creating an anisotropic ion implantation in a preferred direction parallel to the sides of the gate. .
    According to one embodiment, the plasma conditions, in particular the energy of the ions and the implanted dose, are chosen so as to modify, by implantation of the ions, at least portions of the dielectric layer which are situated on an apex of the grid and on either side of the grid and which are perpendicular to the sidewalls of the grid while maintaining portions of the dielectric layer covering the sides of the grid unmodified or unmodified over their entire thickness.
    Alternatively, the step of modifying said dielectric layer by ion implantation comprises an anisotropic ion implantation in a preferred direction parallel to flanks of the gate, the implantation being performed by an implanter.
    According to one embodiment, the ions are ions based on hydrogen (H) and / or based on helium (He). According to one embodiment, the plasma is obtained by injection into a gas reactor especially from helium (He) and / or hydrogen (H2) and / or ammonia (NHS). According to one embodiment, the plasma is obtained by injection into a gas reactor especially from helium (He), hydrogen (H2) and ammonia (NHS) the injection rate of these gases being respectively from 50 to 500 sccm, 10 to 500 sccm, 10 to 500 sccm.
    According to one embodiment, the ions are based on hydrogen and are taken from: H, H +, H2 +, HS +.
    According to one embodiment, the step of modifying the dielectric layer is carried out with a polarization power or source power of between 20V (volt) and 500V, with a pressure of between 5 mTorr (milNTorr) and 100 mTorr, at a temperature of between 10 ° C and 100 ° C, for a period of a few seconds to a few hundred seconds.
    According to one embodiment, the step of modifying the dielectric layer made from a plasma modifies the dielectric layer continuously from the surface of the dielectric layer and to a thickness of between 1 nm (nm) and 30 nm preferably between 1 nm and 10 nm.
    According to one embodiment, the insulating layer is disposed in contact with the layer of a semiconductor material, forming the conduction channel. Preferably, the layer is disposed in contact with the layer. Preferably, the layer is disposed directly in contact with the gate oxide formed by the layer, if the layer is absent or is disposed directly in contact with the layer. Preferably, the dielectric layer is disposed directly in contact with the layer at the edges of the gate. Preferably, the dielectric layer is disposed directly in contact with the layer of a semiconductor material for forming the conduction channel.
    According to one embodiment, the transistor is a FDSOI type or FinFET type transistor.
    BRIEF DESCRIPTION OF THE FIGURES
    The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:
    FIGS. 1a to 1d show, on the one hand, a sectional view of an exemplary MOSFET transistor of the FDSOI type in progress, and, on the other hand, illustrate various defects that can be observed on FDSOI transistor structures. when etching the spacers using either of the standard anisotropic etching processes developed by the microelectronics industry.
    FIGS. 2a to 2d illustrate the steps of an exemplary method according to the invention applied to the production of transistors.
    FIG. 3 illustrates a graph showing the concentration of fluorinated species in the solution as a function of the pH of the solution.
    FIG. 4 summarizes the steps of an exemplary method of the invention intended to form spacers and which do not induce or at least limit the defects described in FIGS. 1b to 1d.
    The accompanying drawings are given by way of example and are not limiting of the invention. These drawings are schematic representations and are not necessarily at the scale of the practical application. In particular, the relative thicknesses of the layers and substrates are not representative of reality.
    DETAILED DESCRIPTION OF THE INVENTION
    It is specified that in the context of the present invention, the term "over", "overcomes" or "underlying" or their equivalent do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by another layer or another element.
    In the following description, the thicknesses are generally measured in directions perpendicular to the plane of the lower face of the layer to be etched or a substrate on which the lower layer is disposed. Thus, the thicknesses are generally taken in a vertical direction in the figures shown. On the other hand, the thickness of a layer covering a flank of a pattern is taken in a direction perpendicular to this flank.
    In the description which follows, a solution of HF diluted to x% corresponds to a mass concentration. A solution of HF diluted to x% means that the mass of HF represents x% of the total mass of the solution. It will be noted, as will be detailed later that the addition of the preferably strong acid such as HCl in the initial solution (that is to say after dilution of the HF but before addition of the acid), does not significantly modify or modify very little the mass% of HF. Thus, the mass% of HF varies very little between the initial solution and the final solution (that is to say after addition of the acid).
    FIGS. 2a to 2d describe the steps of a detailed example of a method according to the invention applied to the production of transistors, for example of the FDSOI type, without this type of transistor being limiting.
    In FDSOI type transistors, the monocrystalline silicon surface layer 146 can be precisely controlled in terms of thickness and doping. In particular, it is advantageous for the performance of the transistors that the channel 130 is completely deserted carriers, that is to say "fully depleted" (FD), English term which is generally used to designate this state. This can be achieved by making the transistors from SOI substrates whose surface layer 146 is very thin.
    The principles of the following steps can also be applied to the formation of spacers on the flanks 125 of a gate 120 of another type of transistor.
    FIG. 2a illustrates the step of depositing a dielectric layer 152, preferably of substantially uniform thickness, on all the surfaces, vertical and horizontal, of the devices being manufactured. This step is preferably carried out using a deposition method known as LPCVD, the acronym for "low pressure chemical vapor deposition", that is to say "low pressure chemical vapor deposition". . This type of deposit which is practiced under atmospheric pressure allows indeed a uniform deposit on all surfaces regardless of their orientation.
    Although this is not necessary for understanding the method of the invention, it will be noted that in this example the gate electrode is composed at this stage of the multi-layer method for certain types of transistors. In addition to the polycrystalline or monoctristalline silicon layer 123, there is, in the stack of layers forming the grid 120, first of all the thin insulating layer of gate oxide 121 through which an electric field will be able to develop to create the underlying conduction channel 130 between source and drain, when a sufficient electrical voltage is applied to the gate. In the most recent MOSFET transistors, it is implemented a qualified technology of the English term "high-k / metal spoils" that is to say that the insulating layer 121 is made of an insulating material with high permittivity (high-k) covered by a metal grid (metal spoil) represented by the layer 122. This technology was developed in particular to reduce the leakage currents through the grid which became much too important due to the decrease in thickness insulating layer 121 to atomic dimensions. At this point, the stack of layers of the grid also comprises a hard mask 124 of protection which will be removed later to allow the resumption of contact on this electrode. This hard mask, which remains in place after etching the gate, is typically made of silicon oxide (SiOy) y being an integer greater than or equal to 1 and most often silicon dioxide SiO 2. Its role is to protect the top 126 of the grid from any damage during the etching of the spacers.
    It is also expected to form isolation trenches 117 whose function is to electrically isolate regions of the active layer 146 in a semiconductor material. An isolation trench 117 is formed of a dielectric material which passes through the active layer 146 to extend into the insulating layer, for example made of a buried oxide 144. Often the isolation trench extends to through the entire insulating layer 144 to reach the support substrate 142. The isolation trenches 117 for this type of transistors are often referred to as STI, acronym for the English term "shallow trench isolation".
    According to one embodiment, the dielectric layer 152 is based on nitride. According to one embodiment, the nitride dielectric layer 152 has a thickness of between 5 and 20 nm, and typically of the order of 10 nm. By way of example, the dielectric layer 152 is based on silicon nitride (SiN). The dielectric layer 152 may also be selected from silicon carbide (SiC), silicon carbonitride (SiCN), carbonitride boron and silicon (SiCBN).
    According to another embodiment, the dielectric layer 152 comprises a low-permittivity dielectric material ε (the permittivity is denoted epsilon) or a low dielectric constant k, with preferably k less than or equal to 7. Thus, the present invention does not is not limited to a dielectric layer formed based on nitride. The present invention is also not limited to a dielectric layer of silicon nitride (SiN).
    The present invention advantageously extends to any spacer comprising a dielectric material with low permittivity ε (called "low-k" in English). The term "permittivity of a material", at the microscopic level, the electric polarizability of the molecules or atoms constituting said material. The permittivity of a material is a tensor quantity (the response of the material may depend on the orientation of the crystallographic axes of the material), which is reduced to a scalar in isotropic media. The dielectric constant is denoted k in the field of integrated circuits and semiconductors, for example. The so-called "low-k" materials are dielectrics with low permittivity. They are used as insulators between metal interconnects to reduce the coupling between them.
    In one embodiment, the dielectric layer 152 has or comprises a material having a dielectric constant of less than 7, preferably 4 and preferably less than 3.1 and preferably less than or equal to 2, thereby reducing the capacitance parasite to possibly improve the performance of the transistor. For example, as indicated above, the material of the dielectric layer 152 is taken from: SiC, SiCN, SiCBN. This makes it possible to reduce the parasitic capacitance and to improve the performance of the transistor accordingly.
    Preferably, but only optionally, the method of the invention comprises an optional step of reducing the dielectric constant of the dielectric layer 152. According to an advantageous embodiment, the reduction of the dielectric constant is obtained during the step of depositing the dielectric layer 152.
    According to one embodiment, the reduction of the dielectric constant comprises the introduction into the dielectric layer 152 in forming precursors which form bonds reducing the polarizability of the dielectric layer 152. These precursors are chosen so as to generate less polar bonds silicon nitride, such as Si-F, SiOF, Si-O, CC, CH, and Si-CH3.
    According to another embodiment, alternative or combinable with the previous one, the reduction of the dielectric constant comprises the introduction into the dielectric layer 152 forming a porosity.
    FIG. 2b illustrates the next step of the invention in which a modification 430 of the dielectric layer 152 that has just been deposited is carried out directly. Optionally, this operation may have been preceded by a "main" etching 420, for example a conventional dry etching of type CH3F / 02 / He. The modification step 430 of the dielectric layer 152 as deposited, or of the layer remaining after a first conventional etching, is by implantation 351 of light species also designated light ions. In the context of the present invention, these ions are ions based on hydrogen (H) and / or based on helium (He).
    The hydrogen-based ions (H) are for example taken from: H, H +, H2 +, H3 +.
    Advantageously, these species can be taken alone or in combination. For example, the possible chemistries for implantation are: H, He, NH3, He / H2, He / NH3. These ions can be implanted in a material to be etched, without causing dislocation of its atomic structure such that it would cause a spray of the latter.
    The term "light ions" means ions from materials whose atomic number in the periodic table of elements is low. In a general way all the elements that can be implanted in the material to be engraved, without causing dislocation of its atomic structure such that it would result in a spraying of the latter, and therefore without re-deposition of the material etched on the reactor walls or the patterns being etched themselves, are likely to agree.
    Particularly advantageously, the implantation of light species is favored by the incorporation into the plasma of a component allowing the dissociation of light ions and therefore the increase of the density of light ions in the plasma and the increase of the implanted dose.
    Advantageously, the implantation parameters, in particular the energy imparted to the ions, the duration and the implantation dose are provided so that the modified dielectric layer 158 can be etched selectively with respect to the layer 146 in a semiconductor material. driver.
    Advantageously, these parameters are also adjusted so that the modified dielectric layer 158 can be etched selectively with respect to the unmodified portion of the dielectric layer 152.
    Advantageously, these parameters are also adjusted so that the modified dielectric layer 158 can be etched selectively with respect to a layer made of an oxide, typically an oxide of said semiconductor material, the latter forming for example an oxide layer gate, a hard mask 124 or an isolation trench 117. Typically, the etching is selective of the modified dielectric material by implantation of hydrogen vis-à-vis silicon oxide SiOy. Implantation is carried out, according to a non-limiting example of the invention, in a plasma based on hydrogen gas (H2). More generally, all the gaseous components, which can dissociate the light ions mentioned above, can be used in the plasma. It will be noted here that this modification step 430 of the dielectric layer 152 to be etched can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry. In particular, standard etching reactors are used in which low or high density plasmas can be produced and where the energy of the ions can be controlled to allow the implantation of the light species above intended to modify the layer to be etched. It is also possible to use a type of so-called immersion plasma commonly used for practicing implantation of species on the surface of a device during manufacture.
    Finally, implantation can also be done in a standard implanter where the ions are accelerated in an electric field to obtain their implantation in a solid. The modification operation is advantageously very anisotropic for the production of the spacers on the flanks 125 of the grids because of the directionality of the ions of the plasma or the implanter. It therefore preferably affects the horizontal surfaces, that is to say all the surfaces parallel to the plane of the substrate 142. The thickness modified on the horizontal surfaces 154 is thus much larger than on the vertical surfaces 156 that is to say on all surfaces perpendicular to the plane of the substrate 146 developed, on which is arranged the grid. Advantageously, the implantation according to the present invention makes it possible not to attack the vertical surfaces. Thus, according to a preferred embodiment, the modified thickness on the vertical surfaces 156 is almost zero, preferably of the order of 1 to 3 nanometers.
    This plane is perpendicular to the plane of the section shown in Figures 2a to 2d. The prepared substrate 142 preferably forms a plate (or "wafer" in English) with two parallel faces. It is for example in the form of a disk, a square, a polygon, etc. The thin layer 146, the buried oxide layer 144 and the solid substrate 142 are arranged in parallel planes. Thus, a surface will be described as horizontal if it is parallel to the plane of the layer or layers forming the substrate 146, on which the grid is formed and a surface will be described as vertical if it is perpendicular to the same plane.
    Typically, a thickness 154 of 10 nm on the horizontal surfaces can be changed during this operation. A thickness 156 of the layer 152 ranging from 1 to 3 nm is however also modified on the vertical surfaces regardless of the plasma conditions. These vertical surfaces with respect to the plane of the substrate 146 are therefore parallel to the sides 125 of the grid. The modified thicknesses depend on the conditions of implementation, in particular on the means employed (plasma or implanter) and also on the fact that it is desired to obtain the etching of the spacers in a single overall step of modification and etching, or that on the contrary repeat these operations until you obtain a complete engraving.
    Thus, depending on the particular implementations of the method of the invention and the initial thickness of the dielectric layer 152, the step of modifying this layer can affect the whole of this layer where, as represented in the example of Figure 2b, only part of it. In this particular case, the material is modified over its entire thickness but only at the level of the horizontal zones 154. In this case, the modification step 430 and the following step 440 of the withdrawal of the modified layer described below may be repeated until complete removal of the dielectric material from the modified dielectric layer 158 on all horizontal surfaces. Plasma implantation has the advantage of allowing implantation to be continuous in a volume extending from the surface of the implanted layer. In addition, the use of plasma allows implantation at lower depths than the minimum depths that can be achieved with implants. Thus, a plasma implantation makes it possible to implement efficiently and relatively homogeneously or at least continuously thin layers that can then be removed by selective etching. This continuity of implantation from the implanted face makes it possible to improve the homogeneity of the modification according to the depth, which leads to a constant etching rate in the time of the implanted layer. Moreover, the increase of the selectivity conferred by the implantation with respect to the other layers is effective from the beginning of the etching of the implanted layer. The plasma implantation thus allows a significantly improved control of the engraving accuracy. Plasma implantation typically allows implanting and then removing thicknesses extending from the surface of the implanted layer and at a depth of 0 nm to 100 nm. Traditional implanters allow implantation in a volume between 30 nm and several hundred nanometers. On the other hand, conventional implanters do not make it possible to implant the species between the surface of the layer to be implanted and a depth of 30 nm. It has been noted that the implanters then do not make it possible to obtain a sufficiently constant etching rate of the modified layer and this from the surface of the latter, thus leading to a lower engraving accuracy compared to that allowed by the invention. The use of a plasma to modify the layer to be removed is therefore particularly advantageous in the context of the invention which aims to remove a thin layer of a dielectric layer 152, typically between 1 and 10 nm and more generally between 1 and 10 nm. and 30 nm. The modification step made from a plasma modifies the dielectric layer 152 continuously from the surface of the dielectric layer 152 and over a thickness of between 1 nm and 30 nm and preferably between 1 nm and 10 nm.
    Preferably, the modification of the dielectric layer 158 maintains an unmodified dielectric thickness 152 on the sidewalls 125 of the grid. This thickness is preserved, at least in part, during the selective etching. It then defines gate spacers 150.
    Preferably, the implantation parameters, in particular the implantation energy of the light ions and the implanted dose, are provided so that the modified dielectric layer 158 can be etched selectively with respect to the material of the implant. layer 146 made of a semiconductor material and vis-à-vis the unmodified dielectric layer 152.
    Preferably, a single modifying step is performed so as to modify the dielectric layer 152 throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer 152 in all its thickness on the surfaces parallel to the preferred direction of implantation.
    Preferably, the implantation modifies the dielectric layer 152 uninterruptedly from the surface.
    According to a particular embodiment, the method comprises a single modification step 430 performed so as to modify the dielectric layer 152 throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer 152 throughout its thickness on the surfaces perpendicular to this plane. These surfaces perpendicular to this plane, that is to say perpendicular to the layer 146 of a semiconductor material forming a conduction channel or solid substrate are typically parallel to the sides 125 of the gate of the transistor. Thus, following this single modification step 430, a recess 440 which will be subsequently described as selective of the modified dielectric layer 158 makes it possible to remove the dielectric layer on all the surfaces except those parallel to the sidewalls 125 of the gate.
    According to another embodiment, the method comprises several sequences each comprising a modification step 430 and a withdrawal step 440. During at least one of the modification steps 430, only a part of the thickness of the dielectric layer 152 is modified. This embodiment has the advantage of removing larger thicknesses of material. It is thus preferable to carry out several cycles each comprising a modification then a withdrawal. Advantageously, the sequences are repeated until the dielectric layer 152 disappears on all the surfaces parallel to the plane of a substrate on which the grid rests. Only the faces parallel to the sidewalls 125 of the grid retain a dielectric thickness, this thickness has not been modified by implantation.
    According to an advantageous embodiment, the dielectric layer 152 is disposed directly in contact with the layer 146 of a semiconductor material. Preferably the dielectric layer 152 is disposed directly in contact with the gate which is preferably formed of a semiconductor material.
    FIG. 2c illustrates the final result of the next step after etching, that is selective removal 440 of the modified dielectric layer 158.
    This selective shrinkage comprises an etching carried out by bringing the stack into contact with one another, in particular the dielectric layer 152, with a solution comprising hydrofluoric acid (HF). More particularly, this solution is obtained from a solution of HF diluted to x%, with x <0.2.
    Advantageously, it has a pH of less than 1.5.
    The decrease of the pH to increase the acidity is for example obtained by adding hydrochloric acid to the solution of HF diluted to x%.
    As indicated above, the concentration of HF at x% corresponds to the mass concentration of HF in the initial solution, that is to say before addition of HCl. However, the necessary volume of HCl to lower the pH of the solution to the desired value is very low. By way of nonlimiting example, 24 ml (10 '^ liters) of concentrated HCl at 36% by weight suffice to lower the pH below 1 for a solution of 3 liters of HF diluted to 0.1% by weight. As a result, the concentration of HF increases from 0.1% to 0.0997% by weight in the final solution after addition of HCl. The concentration of HCl in such a mixture is 0.3% by weight.
    According to one embodiment, in the final solution, the concentrations of HF and HCl are as follows: HF 0.098% and HCl 0.7%.
    The usable ranges are preferably: HF from 0.02% to 0.2% by weight, HCl from 0.3% to 3% by weight.
    This specific solution based on HF makes it possible to etch the modified dielectric layer 158 selectively with respect to the layer 146 in a semiconductor material and vis-à-vis the unmodified dielectric layer 152.
    In a particularly advantageous manner, and unlike solutions of HF diluted to 1% and whose pH is close to 2.5, the HF solution according to the invention makes it possible to etch the modified dielectric layer 158 very selectively with respect to screw oxide layers. Thus the hard mask 124 or insulating trenches 117 made of oxide, for example silicon dioxide SiO 2, are not altered by etching.
    The following table gives an example of the thicknesses (in nanometers 10® meters) consumed after a period of 600 seconds by a solution of HF diluted to 0.1% and having a pH of 0.93:
    By way of comparison, the following table gives an example of the thicknesses consumed after a period of 600 seconds by a solution of HF diluted to 0.1% and having a pH of 2.43:
    Thus, the selectivity (ratio of etch rates) of the etching of the modified SiN compared to the unmodified SiN is 11.2.
    Even more markedly, the selectivity of the etching of the modified SiN relative to the SiO 2 is 33.7. This makes it possible to very precisely control the etching of the modified portions 158 of the dielectric layer 152 with respect to the silicon oxide layers such as the isolation trenches 117, the hard mask 124 and the gate oxide, for example. By way of comparison, the selectivities of the etching of the modified SiN relative to the unmodified SiN and the SiO2 are respectively 10.5 and 4.1 for a solution of HF diluted to 0.1% and having a pH of 2.43:
    The bringing into contact is preferably carried out by dipping the stack comprising the dielectric layer 152 in a bath of the HF-based solution. More generally, the method could be implemented in any equipment for contacting a liquid solution with a plate. In particular it could be done by spraying liquid or immersion. The equipment used for this removal step may for example be any etching or wet cleaning equipment accepting low pH and in particular less than 1.7 and preferably less than 1.
    The wet etching makes it possible, for example, to remove a thickness of the modified dielectric layer 158 between 1 nanometer and a few tens of nanometers. The stop of the engraving is done at the time. It is preferably on the unmodified dielectric layer 152 or on the monocrystalline silicon of the layer 146 or on the hard mask 124 at the top 126 of the grids 120 or on the top of the isolation trenches 117. At the end of this step of withdrawal 440 so that only the initial dielectric layer 152 remains vertical patterns, essentially on the sides 125 of the stack of layers that form the gate 120. They constitute the gate spacers 150 of the transistor.
    FIG. 2d illustrates the step 460 for forming the drain and source zones of a transistor, for example of the FDSOI type. At the end of the last or only step of removing the modified dielectric layer 158, that is to say when it has been removed on all the horizontal surfaces, a cleaning operation called " wet cleaning "most often qualified by its English term" wet clean ".
    The formation 470 of the source and drain electrodes 110 can then proceed. As already mentioned, the doping that will delimit the source and the drain and therefore the length of the channel 132 can be done by ion implantation before does epitaxial growth on these areas in order to increase their section and decrease their resistance. If the doping is carried out before epitaxial growth, as shown in FIG. 2d, the process is said to be an English term "first extension" used to indicate that the extensions (of source and of drain under the spacers) are carried out first, that is, before epitaxial growth. In the opposite case which is said to be "extension last", one proceeds directly to the epitaxial growth step without prior doping. The doping of the source / drain zones is done only after epitaxial growth of these zones. In the case of n-channel transistors (nMOS), the implanted dopants are typically arsenic (As) or phosphorus (P). For p-channel transistors (pMOS) the dopants are boron (B) or boron difluoride (BF2).
    The result is illustrated in FIG. 2d which shows the doped source / drain zones 114 before epitaxial growth of the raised source / drain zones 116.
    Advantageously, the gate of the transistor is located on a stack of layers forming an elaborate silicon-on-insulator (SOI) substrate. Preferably, it is disposed directly in contact with the layer forming the conduction channel. Advantageously, the use of the invention with such an SOI substrate makes it possible to preserve the integrity of the superficial layer of very thin thickness which forms the conduction channel of a transistor formed from an SOI substrate.
    FIG. 3 illustrates a graph showing the concentration, more precisely the molar fraction, of the fluorinated species in the solution as a function of the pH of the solution.
    It can be seen from this graph that in a zone 32 whose pH is between 2 and 4, the molar concentrations of HF and of F ions are important.
    When adding HCl to increase the acidity of the solution and the pH becomes less than 1.7, the molar concentration of F 'ions is very greatly reduced and the molar concentration of HF is very important. This is explained by the association of the H "ions of the HCl with the F 'ions to form HF molecules. This appears clearly in area 31 of the graph.
    Cr, in the context of the development of the present invention, it has been found that these ions F 'degrade the modified nitride with a lower selectivity than the HF molecules.
    It will be noted that on this graph, the abbreviation M is an abbreviation of the international system of units which designates a concentration in mol / L. The vertical line denoted pH for 0.05M denotes the pH of the equilibrium 0.05M HF solution, that is to say if one only has the HF in solution in water without seeking to modify the pH. Note that the molar concentration of 0.05M corresponds to the 0.1% mass concentration, the equilibrium pH of such a solution is equal to 2.25.
    FIG. 4 summarizes the steps of the method of the invention intended to form spacers and which induce few or none of the defects described in particular in FIGS. 1b, 1c and 1d for the production of transistors, for example but not exclusively of type FDSCI.
    After depositing LPCVD with a uniform dielectric layer 152 on all the surfaces of the devices being manufactured, said modified dielectric layer 158 is removed on the surfaces that are not intended to form the spacers. This removal comprises several steps, including steps 430, 440 and optionally step 420 beforehand.
    Thus, optionally, a "main" etching, preferably an isotropic conventional wet etching 420 of the modified dielectric layer 158. is carried out. In the context of specific implementations of the invention, it is possible to decide whether or not to maintain the main etching step 420, the following steps then apply either on the dielectric layer 152 as filed or on the remaining layer after a main etching has been previously performed as in the standard method of etching the spacers.
    As shown in FIG. 2b, the following step 430 consists in anisotropically modifying all or part 154 of the remaining dielectric layer 152 by implantation of light ions.
    Depending on the applications of the process of the invention, it may be preferred to use a plasma etcher for plasma implantation, in particular for the following reasons: the cost of the apparatus is lower, the manufacturing cycle times may be shorter since the main etching step 420 and that of modification 430 of the dielectric layer 152 can then be done in the same apparatus without releasing devices in the process of manufacture. It will be noted in particular that the modification step 430 can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry, such as using any type of burner, for example in a ICP reactor of the English "Inductively Coupled Plasma" that is to say "inductively coupled plasma", or in a type of reactor CCP of the English "Capacitively Coupled Plasma" that is to say "plasma Capacitive coupling "which controls the energy of the ions. It is also possible to use a type of so-called immersion plasma commonly used for practicing implantation of species on the surface of a device during manufacture.
    In order to choose the implantation parameters, the person skilled in the art, in order to determine the behavior of the material to be etched in the type of plasma etcher chosen, will preferentially proceed to "full-plate" tests in order to establish behavior curves. He will deduce the parameters of the implantation, in particular the energy and the dose of ions, that is to say the exposure time, to use to reach the desired thickness of material to be modified.
    The following table gives typical conditions for implementing step 430 of modifying the dielectric layer 152 in the case of using a standard plasma etching reactor. These conditions are largely dependent on the thickness to be modified in the dielectric layer 152. This is only a particular example of implementation of step 430 for modifying the layer to be etched.
    The possibility of drawing the source and / or the bias also allows to have a better control on the depth of implantation for small thicknesses.
    The next step 440 is that in which etching of the modified layer or at least the modified thickness of the modified dielectric layer 158 is practiced by etching. To avoid the problems of the traditional methods of etching the spacers described in FIGS. 1b to 1d, it is necessary that the etching of the modified dielectric layer 158 is as selective as possible with respect to silicon in particular so as not to attack the monocrystalline silicon source / drain areas with the disadvantages and consequences described above.
    The withdrawal 440 of the modified dielectric layer 158 comprises wet etching based on a solution comprising HF and whose pH is less than 1.7. The thickness of the modified dielectric layer 158 is typically in a range of values from 1 nanometer to a few tens of nanometers. Burning times can range from seconds to minutes. They are obviously directly dependent on the thickness of the dielectric layer that has been modified 158.
    The following steps 460, 470 of the process are not different from those corresponding to the standard processes where the extensions of the source / drain zones 460 are possibly carried out by ion implantation of dopants before epitaxial growth of the raised source / drain 470 of transistors, for example FDSOI type.
    Nonlimiting detailed example As a non-limiting example of the invention, depositing a 15nm layer of silicon nitride (SiN) intended to form a spacer 125.
    To modify a thickness of 12 nm of silicon nitride in an ICP type burner (TCP RF), continuously, a voltage of 250V (bias voltage) is applied for a period of 60 seconds for a plasma formed from a hydrogen-based component (H) with a flow rate of 48 sccm. In this case, the pressure used is 10 mTorr and the power of the source is 500W.
    For example, to remove 10 nm of modified SiN, the latter is exposed to a solution of HF diluted to 0.1%, the pH of which is 0.93 for 12 minutes (720 seconds).
    In view of the above description, it is clear that the invention not only allows a control of the damage that can be generated following an ion implantation, but also an improvement in the removal of the modified dielectric layer 152, by providing a method having a better selectivity of etching between the modified dielectric layer and the unmodified dielectric layer on the one hand, between the modified dielectric layer and the silicon oxide layer and between the modified dielectric layer and the layer made of a semiconductor material on the other share.
    Advantageously, the present invention provides an infinite selectivity of the modified dielectric layer. Thus, the present invention allows better control of critical dimensions. The method according to the present invention also allows selective etching of the modified dielectric layer with respect to other unmodified layers, avoiding any risk of consuming all or part of a silicon nitride layer or a layer based on silicon oxide. In particular, the hard mask covering the gate and the silicon oxide isolation trenches are not affected by the etching of the spacers. The invention is not limited to the only embodiments and embodiments described above, but extends to all embodiments within the scope of the claims.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    A method of forming spacers (150) of a gate (120) of a field effect transistor (100), the gate (120) including flanks (125) and a peak (126) and being located above a layer (146) of a semiconductor material, the method comprising a step (410) of forming a dielectric layer (152) overlying the gate of the transistor, the method comprising: - after step for forming the dielectric layer (152), at least one step of modifying (430) said dielectric layer (152) by ion implantation at least in portions of the dielectric layer (152) which are located on a top ( 126) of the grid and on either side of the grid (120) and which are perpendicular to the sidewalls (125) of the grid (120) while retaining portions of the dielectric layer (152) covering the flanks (125) the grid (120) unmodified or unmodified throughout their thickness; the ions being ions based on hydrogen (H) and / or on the basis of helium (He); at least one step of removing (440) the modified dielectric layer by selectively etching said modified dielectric layer with respect to the layer (146) in a semiconductor material and screwed to -vis the dielectric layer (152) unmodified; characterized in that the step of removing (440) the modified dielectric layer comprises wet etching based on a solution comprising hydrofluoric acid (HF) diluted to x% by weight, with x <0.2 and exhibiting a pH less than or equal to 1.5 ..
    [2" id="c-fr-0002]
    2. Method according to the preceding claim wherein the pH is less than or equal to 1.3, preferably less than or equal to 1 and preferably strictly less than 1.
    [3" id="c-fr-0003]
    3. Method according to any one of the preceding claims wherein x <0.15 and preferably x <0.1.
    [4" id="c-fr-0004]
    4. Method according to any one of the preceding claims wherein x is substantially equal to 0.1.
    [5" id="c-fr-0005]
    5. Method according to any one of the preceding claims wherein the solution is obtained by adding at least one of: hydrochloric acid (HCl), sulfuric acid H2SO4, nitric acid HNO3.
    [6" id="c-fr-0006]
    A method according to any one of the preceding claims comprising, prior to the step of removing (440) a step of forming a mask (124) located on the top (126) of the gate (120), said mask being based on silicon oxide SiOy y being an integer greater than or equal to 1, and preferably based on silicon dioxide (SiO 2).
    [7" id="c-fr-0007]
    A method according to any one of the preceding claims comprising, prior to the step of removing (440) a step of forming an isolation trench (117) extending through the layer (146) into a semi material -conducteur, said isolation trench (117) being based on silicon oxide SiOy, y being an integer greater than or equal to 1, and preferably based on silicon dioxide (SiO 2).
    [8" id="c-fr-0008]
    The method of any of the preceding claims wherein the dielectric layer (152) is a nitride layer, preferably a silicon nitride (SiN) layer.
    [9" id="c-fr-0009]
    The method of any one of claims 1 to 7 wherein the dielectric layer (152) is a silicon-based layer (Si) and wherein the material of the dielectric layer (152) is preferably selected from: SiC, SiCN, SiCBN.
    [10" id="c-fr-0010]
    A method according to any one of the preceding claims comprising a single modification step (430) performed so as to modify the dielectric layer (152) throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid (120) and not to modify the dielectric layer (152) throughout its thickness on the surfaces perpendicular to this plane.
    [11" id="c-fr-0011]
    The method of any of the preceding claims, wherein the step of modifying (430) said dielectric layer (152) by ion implantation comprises contacting the dielectric layer (152) with a plasma creating an anisotropic implantation of ions in a preferred direction parallel to flanks (125) of the gate (120).
    [12" id="c-fr-0012]
    12. The method according to any of the preceding claims, wherein the ions are ions based on hydrogen (H) and / or based on helium (He).
    [13" id="c-fr-0013]
    13. Process according to any one of the preceding claims, in which the plasma is obtained by injection into a gas reactor, in particular taken from helium (He), hydrogen (H2) and ammonia (NHS). injection of these gases being respectively 50 to 500 sccm, 10 to 500sccm, 10 to 500 sccm.
    [14" id="c-fr-0014]
    A method according to any one of the preceding claims wherein the step of modifying (430) the dielectric layer (152) is performed with a bias power or source power of between 20V (volts) and 500V, with a pressure between 5 mTorr (milliTorr) and 100 mTorr, at a temperature between 10 ° C and 100 ° C, for a period of seconds to a few hundred seconds.
    [15" id="c-fr-0015]
    15. The method according to claim 1, wherein the transistor is a FDSOI type or FinFET type transistor.
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    同族专利:
    公开号 | 公开日
    EP3261124B1|2020-08-19|
    EP3261124A1|2017-12-27|
    FR3052911B1|2018-10-12|
    US9947541B2|2018-04-17|
    US20180012766A1|2018-01-11|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20030017686A1|2001-05-23|2003-01-23|Matsushita Electric Industrial Co., Ltd.|Method for fabricating semiconductor device|
    US20130037919A1|2011-08-10|2013-02-14|Micron Technology, Inc.|Methods of forming trenches in silicon and a semiconductor device including same|
    US20140179107A1|2012-12-21|2014-06-26|Intermolecular Inc.|Etching Silicon Nitride Using Dilute Hydrofluoric Acid|
    US20140273292A1|2013-03-14|2014-09-18|Applied Materials, Inc.|Methods of forming silicon nitride spacers|
    FR1262962A|1960-07-12|1961-06-05|Automatic connection for removable pipes|
    US7763510B1|2009-01-07|2010-07-27|Freescale Semiconductor, Inc.|Method for PFET enhancement|
    US9780191B2|2014-07-18|2017-10-03|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method of forming spacers for a gate of a transistor|KR20190038945A|2016-08-29|2019-04-09|도쿄엘렉트론가부시키가이샤|Semi-atomic layer etching method of silicon nitride|
    TW201903895A|2017-02-23|2019-01-16|日商東京威力科創股份有限公司|Anisotropic extraction method for germanium nitride mandrel for manufacturing self-aligned bulk structure|
    WO2018156975A1|2017-02-23|2018-08-30|Tokyo Electron Limited|Method of quasi-atomic layer etching of silicon nitride|
    法律状态:
    2017-06-27| PLFP| Fee payment|Year of fee payment: 2 |
    2017-12-22| PLSC| Publication of the preliminary search report|Effective date: 20171222 |
    2018-06-27| PLFP| Fee payment|Year of fee payment: 3 |
    2020-06-30| PLFP| Fee payment|Year of fee payment: 5 |
    2021-06-30| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1655739|2016-06-20|
    FR1655739A|FR3052911B1|2016-06-20|2016-06-20|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|FR1655739A| FR3052911B1|2016-06-20|2016-06-20|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|
    EP17176724.7A| EP3261124B1|2016-06-20|2017-06-19|Method for forming spacers of a transistor gate|
    US15/627,713| US9947541B2|2016-06-20|2017-06-20|Method of forming spacers for a gate of a transistor|
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