• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method for producing a semiconductor rod structure capable of forming at least one transistor channel, comprising the steps of: a) providing a semiconductor structure formed by an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconductor material, then b) removing portions of the structure based on the first material unveiled by an opening in a masking formed on the structure, the by selective etching in the opening of the first material vis-à-vis the second material, so as to release a space around the second bars, then c) grow in the opening, a semiconductor material ( 25) given around the second bars (6c), the given semiconductor material having a mesh parameter different from that of the second material (7), so as to induce a constraint on the sheaths based on the given semiconductor material.
    公开号:FR3051970A1
    申请号:FR1654690
    申请日:2016-05-25
    公开日:2017-12-01
    发明作者:Remi Coquand；Emmanuel Augendre；Nicolas Loubet；Shay Reboh
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；International Business Machines Corp；
    IPC主号:
    专利说明:

    IMPLEMENTING A FORMAL CHANNEL STRUCTURE OF A PLURALITY OF RODS
    CONDUCTOR SEMICONDUCTORS
    DESCRIPTION
    TECHNICAL FIELD AND PRIOR ART
    The present application relates to the field of strained semiconductor structures capable of forming a transistor channel region and in the form of a plurality of constrained semiconductor elements.
    The realization of a transistor whose channel structure is formed of a plurality of superimposed semiconductor bars or nano-wires is known.
    The document FR 2 989 515 presents an example of a method of producing a transistor equipped with such a type of channel structure and a coating grid (GAA for "Gât AN Around").
    The channel structure may be formed of a stack of different semiconductor materials with at least one constrained semiconductor material but its embodiment typically comprises at least one stage of etching of the bars capable of generating a relaxation phenomenon and therefore of loss of stress.
    STATEMENT OF THE INVENTION
    One embodiment of the present invention provides a method for producing a semiconductor rod structure capable of forming at least one transistor channel, the method comprising the steps of: a) providing on a substrate, at least one semiconductor structure formed of an alternation of first bars based on at least one first material and second bars based on at least one second material, the second material being a semiconductor material, then b) removing portions of the structure based on the first material unveiled by an opening in a masking formed on the structure, the removal being achieved by selective etching in the opening of the first material vis-à-vis the second material, so as to release a space around the second bars, then c) forming, in the opening, a constrained region by coating the second bars of a given semiconductor material constrained because having a mesh parameter different from that of the second material.
    "Bars" means oblong shaped elements such as nano-son or membranes or fins ("end" according to the English terminology).
    Thus, with such a method, after having performed step b) for releasing these second bars, a constraint is made on a region, called sheath or envelope, made using a semiconductor material. given mesh parameter adapted and formed around the second bars.
    The structure produced in step a) is such that the first bars and the second bars are stacked.
    According to one possibility of implementing the method, the second material is based on Si or Sii-xGex (with x> 0), the given semiconductor material being based on Sii-yGey with 0 <x <y. In this case, sheaths of given material are constrained in compression around the second bars, these bars being adapted to form a P-type transistor channel structure, in particular PMOS. When the given semiconductor material is based on Sii-yGey, advantageously, the given semiconductor material has a concentration of germanium such that y> 0.25.
    According to another possibility of implementing the method, the second material may be based on silicon germanium while the semiconductor material given is silicon. In this case, the given material sheath is voltage-stressed and can be adapted to form an N-type transistor channel structure, in particular NMOS.
    Advantageously, said alternation is an alternation of silicon-based bars and silicon germanium-based bars.
    Between step a) and step b), the masking can be formed by depositing a masking layer and then making an opening in the masking layer revealing said structure. The realization of this opening may comprise a step of removing a sacrificial gate formed around a region of the stack.
    Advantageously, the method further comprises a step of thinning the second bars. This can facilitate the electrical control of the channel structure. Preferably, the thinning is performed before step b) leading to the formation of a sheath of given semiconductor material constrained around the bars. It is thus possible to perform a step of thinning the second bars after the step of selective etching of the first material and before the step of growth of the given semiconductor material. The thinning step can be carried out for example by thermal oxidation, so as to form an oxide layer around the second bars. A removal of said oxide layer is then performed.
    It is also possible to thin using an etching process, in particular of the ALE type (for "Atomic Layer Etching" in English terminology).
    After stressing said structure, it is possible to complete the formation of a transistor and in particular to perform a step of forming a gate in the opening.
    Advantageously, between step c) and the step of forming the grid, the sheath or envelope of semiconductor material that is given is intact.
    In particular, it is preferable to implement a process without intermediate heat treatment or annealing step between step c) of forming the sheath or envelope of semiconductor material given and the step of forming the gate. Such thermal annealing could, in addition to causing a diffusion of the given semiconductor material of the sheath into the bars, also induce an untimely diffusion of dopants from the source and drain regions towards a zone of the bars intended to form a structure. of channel.
    According to one possible implementation of the method, after formation in step a) of a stack of first bars and second bars is made a sacrificial gate and spacers on both sides the sacrificial gate.
    The method can then further include steps of: - removal of portions of the bars at the ends of the stack and on either side of the spacers. - Formation of source and drain semiconductor blocks by growth of at least one semiconductor material on either side of the spacers.
    The growth is advantageously carried out on end zones of the stack which protrude from the spacers.
    The present invention also relates to a semiconductor structure implemented using a method as described above, and a transistor comprising such a semiconductor structure.
    One embodiment of the present invention provides a device provided with a semiconductor structure capable of producing at least one transistor channel, the structure being formed of bars based on a semiconductor material arranged above one another. others, the semiconductor bars being each surrounded by a sheath of another given semiconductor material having a mesh parameter different from that of said semiconductor material, so that the sheaths based on said semiconductor material are put in constraint.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:
    FIGS. 1A-1K illustrate an example of a method for producing a semiconductor structure with superposed bars and comprising a constrained semiconducting sheath;
    FIG. 2 illustrates an exemplary configuration of semiconductor bars after formation of a constrained sheath around them;
    FIGS. 3A-3C illustrate an alternative embodiment of the superimposed semiconductor structure in which the bars are thinned before the growth of a semiconductor material of different mesh parameter to make it possible to obtain a constraint on their periphery;
    FIG. 4 illustrates an example of stress state simulation in a semiconductor structure that can be obtained by means of a method according to the invention;
    Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily in a uniform scale to make the figures more readable.
    In addition, in the following description, terms that depend on the orientation, such as "on", "above", "upper", "lower", "lateral", etc. of a structure apply considering that the structure is oriented in the manner illustrated in the figures.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    An example of a method for producing a semiconductor structure having a plurality of constrained semiconductor elements and capable of forming at least one transistor channel will now be described in connection with FIGS. 1A-1K and 2 .
    The starting material of the process is typically a solid semiconductor substrate 1 (commonly called "Bulk" according to the English terminology), for example silicon.
    First of all, at least one stack 3 of bars, also called nano-wires, that is to say blocks of oblong shape and which may be parallelepipedal, or of circular or ellipsoidal section, is produced first on this substrate 1.
    This stack comprises semiconductor bars with an alternation of bars 4a, 4b, 4c, 4d based on a first material 5 and bars 6a, 6b, 6c based on a second material 7 (Figure lA).
    The first material 5 is preferably a semiconductor material such as for example silicon germanium (Sii-aGea with a> 0) while the second material 7 is a semiconductor, for example silicon (Si). The first material 5 is a material chosen so as to have an etching selectivity with respect to the second material 7. When the second material 7 is made of silicon and the first material 5 is made of Sii-aGea, the first material 5 may have a germanium content for example between 5% and 100%, preferably between 20 and 40%. This germanium content of the first material 5 is chosen so that it can be removed selectively by etching with respect to the second material 7. Advantageously, the first material 5 has a Ge concentration at least 5% greater than that of the second material 7 .
    To build the stack of bars, it is possible firstly to produce a stack of semiconductor layers, formed for example by epitaxy, of an alternation of layers based on the first material 5 and layers based on the second material 7 This layer stack is then etched through a masking, which may be a hard mask, for example based on silicon nitride. Anisotropic etching is then performed of the zones of the stack of layers that are not protected by the hard mask.
    The bars or nanowires obtained at the end of this etching can thus have a parallelepipedal shape with a critical dimension of, for example between 5 nanometers and 40 nanometers. "Critical dimension" means the smallest dimension of a pattern other than its thickness, the critical dimension of being measured in a direction parallel to the main plane of the substrate (ie a plane passing through the substrate and which is parallel to the plane [O; x; y] of the orthogonal reference [O; x; y; z] given in FIG. 1). The bars 4a, 4b, 4c, 4d, 6a, 6b, 6c may have a thickness e, for example between 5 nanometers and 15 nanometers (measured in a direction parallel to the vector z orthogonal reference [O; x; y; z ] in Figure 1).
    At least one sacrificial gate 11 is then produced on a central region of the stack 3, the sacrificial gate 11 being able to be formed of a layer of dielectric material covered with a layer of gate material such as, for example, poly silicon. The sacrificial gate 11 also called "dummy gate" ("dummy gate") covers the top and side flanks of this central region of the stack 3.
    Insulating spacers 13a, 13b are then formed on either side of the sacrificial gate 11, the insulating spacers 13a, 13b encasing the stack of semiconductor bars. The insulating spacers 13a, 13b thus cover the top and side flanks of the stack 3. The insulating spacers 13a, 13b are for example based on silicon nitride. The insulating spacers 13a, 13b and the sacrificial gate 11 thus cover at least one central zone of the stack 3 of semiconductor bars (FIG. 1B).
    Source and drain blocks 15a, 15b can then be formed. These blocks can be produced for example in the manner described in the publication "Density scaling with gate-all-around Silicon nanowire MOSFETs forthe 10 nm node and beyond", by S. Bangsaruntip et al., EDM 2013. Thus, by an etching anisotropic is removed end portions of the stack of bars of first material and second material, that is to say portions located on either side of the spacers 13a, 13b. The etching is preferably carried out so as to stop in line with the spacers 13a, 13b. It is also possible to make internal spacers as described for example in document WO 2015/050546 A1. An epitaxial growth step doped in situ and originating at least on a section of second material bars then makes it possible to form the electrodes. source and drain uniformly doped.
    Then, forming a masking layer 17 also called layer 17 "encapsulation" so as to cover the structure. The masking layer 17 may for example be based on silicon oxide (FIG. 1C giving a perspective view of the structure and FIG. 1 giving a sectional view along a plane parallel to the plane [0; y; z] ).
    A removal step, for example by flattening or CMP polishing (CMP for "Chemical Mechanical Planarization"), of this masking layer 17 can then be performed with a stop at the top or the upper face of the sacrificial gate 11. Then, an opening 19 is made in the masking layer 17 so as to reveal again a central region of the stack of semiconductor bars (FIGS. 1E and 1F). This opening 19 is formed by removing the sacrificial gate 11. When the sacrificial gate 11 is polysilicon, its removal can be achieved for example by wet etching with an ammonia-based solution. with a stop on the sacrificial gate dielectric, which can then be withdrawn into the opening 19, for example by etching with hydrofluoric acid for the typical case of a dielectric based on silicon oxide.
    Then, in the opening 19, a withdrawal of one of the materials 5, 7 of the unveiled region of the stack is carried out. In particular, the first material 5 is removed selectively from the second material 7 (FIGS. This selective shrinkage can be carried out, for example by chemical vapor-etching, for example using HCl mixed with a carrier gas or by chemical etching based on CF4, in the case where the material removed is SiI 2. -aGea. Thus, in the opening 19, suspension bars 6a, 6b, 6c based on the second semiconductor material 7 are formed. The bars 6a, 6b, 6c based on the second material 7 advantageously have a central portion that is not not covered by another material, so that a void space is formed around the central portion of the bars 6a, 6b, 6c based on the second semiconductor material 7.
    Next, a layer 24 of semiconductor material 25 on the portions exposed by the opening 19 of the semiconductor bars 6a, 6b is made to grow by chemical vapor deposition ("Chemical Vapor Deposition" in English terminology). , 6c (Figures 11 and IJ). This deposit is preferably selective, the deposited semiconductor material being advantageously crystalline. In the case of a non-selectively deposited layer 24, a subsequent etching step of the semiconductor material 25 is provided, for example under HCl or during a diluted SCI cleaning in the case where the semiconductor material 25 is based on SiGe.
    In the case where the layer 24 is deposited in amorphous form, it is subjected to at least one annealing so as to crystallize in a controlled manner. Slow crystallization is favored, so as to promote the most monocrystalline structure possible.
    When the second semiconductor material 7 is for example silicon Si, the given semiconductor material 25 may for example be Si-xGex with x> 0 and preferably such that x is at least 25%. The layer 24 can be obtained by epitaxy at a temperature of between 500 ° C. and 600 ° C. If the deposit is made around 425 ° C, the deposited material may be amorphous. It is then advantageous to crystallize it between 500 ° C. and 550 ° C.
    The semiconductor material 25 that is grown is a material having a mesh parameter different from that of the second semiconductor material 7. The difference in mesh parameter between the semiconductor materials 7 and 25 is such that the given semiconductor material 25 is constrained.
    When the second material 7 is, for example, silicon Si, the given semiconductor material 25 may for example be Sii xGex with x> 0 and preferably such that x is at least equal to 25%, so as to have a high level of stress, for example of the order of between 1 and 2 GPa for a thickness of the layer 24 of the order of 2 nm when the Germanium x concentration is between 25-50%. The level of stress strongly depends on the dimensions of the structure. Advantageously, the growth is isotropic, with a similar growth rate on each of the faces of the bars 6a, 6b, 6c: i.e. side faces, upper and lower.
    The layer 24 of semiconductor material 25 preferably covers all the periphery of the central portion of the semiconductor bars 6a, 6b, 6c, so as to form a closed semiconductor contour or a ring, also called "sheath" or "wraps" around the central portion of the semiconductor bars 6a, 6b, 6c. A core-shell configuration is thus obtained as illustrated in the cross-sectional view of FIG. 2 of a semiconductor bar 6a (forming the core) in FIG. base of the second material 7 covered over the entire outer surface of its central portion by the layer 24 of semiconductor material given 25 (forming the envelope or the sheath).
    A replacement grid 30 may then be formed in the aperture 19. A grid stack may be conformably formed, for example by CVD (Chemical Vapor Deposition), a gate dielectric for example based on HfO 2, and at least one gate material, for example formed of a layer containing metal such as TiN or TaN and a layer of semiconductor material such as polysilicon or metal such as Tungsten, so as to fill the opening 19.
    An encircling grid, forming a closed contour or a ring around a central portion of the bars 6a, 6b, 6c and the sheath of constrained material 25 formed around this central portion is thus achieved (Figure IK).
    A step of removing the gate material protruding above the mouth of the opening 19 or the upper face of the masking in which this opening 19 is made may then be performed, for example by planarization CMP. At the end of this step, a gate having a length W (measured parallel to the y axis of the reference [O; x; y; z] and corresponding to the channel length) for example between 5 and 50 nm can to be formed.
    Thus, in this example, a coating or GAA ("Around AN" gate) pattern is produced around a semiconductor structure provided with several constrained semiconductor elements, in particular constrained in compression, and capable of forming at least a transistor channel region.
    Preferably, between the formation of the given semiconductor material sheath 25 and the production of the grid 30, an annealing or heat treatment step is avoided. It is thus possible to preserve the sheath of given semiconductor material 25 without causing this material to diffuse into the core of the bars 6a, 6b, 6c.
    By avoiding a high-budget thermal annealing after the step of forming the given semiconductor material sheath 25, it also prevents the unwanted diffusion of dopants from the source and drain electrodes previously formed in regions of the bars 6a, 6b. , 6c.
    In FIG. 4, the curves Co, Ci give results of stress tensor simulation along the x axis in a semiconductor structure of the type of that described with reference to FIG. 1H with 3 silicon bars arranged at one end. above the others and having a thickness e of 6 nm, a critical dimension of 10 nm (width W of the channel), and a length Lg (corresponding to the channel or gate length) of 12 nm, and layers of SiGe 30%. A first curve Co is representative of a stress state simulation of the structure after performing the step of releasing the silicon bars by selective etching and before the epitaxial growth is carried out in the case of a process. involving the etching of the source and drain zones after formation of the main spacer, as in the publication "Density scaling with gate-all-around Silicon nanowire MOSFETs for the 10 nm node and beyond", S. Bangsaruntip et al. , lEDM 2013. The curve Co shows that the stress can be slightly tensile, which is unfavorable to the p-type transistor.
    A second curve Ci is representative of a simulation of stress state of the structure following the epitaxial growth step as described in connection with FIG. 1J, in this example with a layer of silicon of Germanium with a thickness of the order of 2 nm and with a Germanium concentration of 30%. The second curve Ci shows that it is possible to reach a compressive stress of the order of -1.6 GPa in the sheath.
    A constrained bar semiconductor structure can be implemented using semiconductor materials different from those of the embodiment which has just been given. For example, it is possible to provide bars 6a, 6b, 6c based on Silicon Germanium (Sii-zGez, with z> 0) around which epitaxial growth is made by a layer of semiconductor material based on Sii-xGex with x> z and preferably such that x - z> 0.1. Such a layer may have a thickness of between 2 nm and 5 nm.
    This may also make it possible to form a semiconductor rod channel structure 6a, 6b, 6c with the compression-constrained sheath.
    According to one variant, it is possible to provide bars 6a, 6b, 6c, for example based on Silicon Germanium (Sii-zGez with z> 0) around which a layer 24 of a semiconductor material 25 is grown by epitaxial growth. base of Si.
    In this case, a channel structure with semiconductor bars 6a, 6b, 6c is produced, this time with the voltage-constrained sheath. Thus, a method according to the invention can also be applied to the implementation of at least one N-type transistor channel structure, in particular NMOS.
    According to another variant embodiment of one or the other of the examples of the method which have just been described, thinning of the bars 6a, 6b, 6c suspended semiconductors after release of the latter by selective etching is provided. (Figure 3A). Thinning can be achieved for example by etching with HCl when the bars 6a, 6b, 6c to thin are silicon or silicon germanium. It is also possible to carry out type engraving by ALE (Atomic Layer Etching). For an ALE etching, this is carried out for example under an IC 2 atmosphere by alternating adsorption at room temperature and desorption at 650 ° C. To thin the bars 6a, 6b, 6c and to reduce their volume, it is also possible to perform an oxidation of their surface. Such oxidation can be carried out between 900 ° C. and 1000 ° C. and is followed by deoxidation.
    Then epitaxial growth of given semiconductor material 25 is carried out in a region in the aperture 19 on a central portion of the thinned rods 6a, 6b, 6c. The material that is grown has a mesh parameter different from that of the bars 6a, 6b, 6c, so as to be constrained by them. In this embodiment, a configuration is obtained in which at least a portion of the given semiconductor material sheath 25 is aligned with or located in the same plane parallel to the substrate as a region 61 of the bars 6a, 6b, 6c, itself in contact with the source and drain electrodes 15a, 15b. With respect to an arrangement as provided in FIG. 1J, it will thus be possible to promote current flow in the sheath of constrained semiconductor material. The given thickness of semiconductor material being grown may be less than or equal to (Figure 3B) the thickness of material that was removed during the thinning step described above.
    Then, a grid 30 is formed in the opening 19, for example using CVD deposition (CVD for "Chemical Vapor Deposition") of a gate dielectric, for example based on SiO 2 and HfO 2, and at least one gate material, for example formed of a metal layer such as Tungsten or containing a metal for example based on TiN or TaN and / or a layer of doped semiconductor material such as only polysilicon (Figure 3C).
    By performing the thinning of the bars before the formation of the sheath, it is ensured to limit the heat treatment steps after formation of the sheath and which could induce a diffusion of the semiconductor material given in the heart of the bars 6a, 6b , 6c. Thinning makes it possible to implement an improved arrangement as illustrated in FIG. 3C in which the outer surface of the sheath and portions of the bars 6a, 6b, 6c attached to the source and drain blocks are aligned in one direction. parallel to the main plane of the substrate (ie a plane parallel to the plane [O; x; y] of the reference [O; y; y; z]. A stress sheath is formed which is not situated in front of the spacers. thinning of the bars before the formation of the sheath, it is arranged to facilitate the transfer of charge carriers between the source and drain zones and the sheath.
    In the embodiment described above, the stack is made on a solid substrate. However, a method according to the invention can also be adapted to a semiconductor-on-insulator type substrate, for example SOI ("SOI for" Silicon On Insulator "or silicon-on-insulator) or semiconductor-on-insulator type sSOI (sSOI for "strained SOI" or SOI constrained) formed of a semiconductor layer for example based on Si covered with an insulating layer for example based on SiO 2, itself covered with a superficial semiconductor layer.
    A method according to the invention can be adapted to the implementation of transistors according to advanced technological nodes, in particular with a channel or gate length of less than 20 nm.
    A constrained semiconductor rod transistor structure as described above may be integrated in a high performance, low power logic circuit, or for example in a NAND flash memory, or in a molecular memory.
    权利要求:
    Claims (10)
    [1" id="c-fr-0001]
    A method of producing a semiconductor rod structure capable of forming at least one transistor channel, the method comprising the steps of: a) providing on a substrate (1) at least one semiconductor structure formed an alternation of first bars (4a, 4b, 4c) based on at least a first material (5) and second bars (6a, 6b, 6c) based on at least one second material (7), the second material being a semiconductor material, the first bars and the second bars being stacked, then, b) removing portions of the structure based on the first material revealed by an opening (19) in a masking (17) formed on the structure, the removal being carried out by selective etching in the opening (19) of the first material vis-à-vis the second material, so as to release a space around the second bars (6a, 6b, 6c), then c) to grow or deposit, in the opening, a semiconductor material the given semiconductor material having a mesh parameter different from that of the second material (7), so as to induce a stress on the layer of the second layer (6a, 6b, 6c), given semiconductor material.
    [2" id="c-fr-0002]
    2. Method according to claim 1, wherein the second material (7) is based on Si or Sii-xGex (with x> 0), the given semiconductor material (25) being based on Sii-yGey with 0 <x <y.
    [3" id="c-fr-0003]
    The method of claim 2, wherein the given semiconductor material (25) has a concentration of germanium such that y> 0.25.
    [4" id="c-fr-0004]
    4. The method of claim 1, wherein the second material (7) is based on silicon germanium, the given semiconductor material being silicon.
    [5" id="c-fr-0005]
    5. Method according to one of claims 1 to 4, wherein said alternation is an alternation of silicon-based bars and silicon germanium bars.
    [6" id="c-fr-0006]
    6. Method according to one of claims 1 to 5, comprising between step a) and step b), the formation of masking by deposition of a masking layer (17) and then making an opening (19). ) in the masking layer revealing said structure, the production of said opening comprising the removal of a sacrificial gate (11) formed around a region of the stack.
    [7" id="c-fr-0007]
    7. Method according to one of claims 1 to 6, wherein after formation in step a) of a stack of first bars (4a, 4b, 4c) and second bars (6a, 6b, 6c), forms a sacrificial gate (11) and insulating spacers on either side of the sacrificial gate, the method further comprising steps of: - portion removal of the bars at the ends of the stack and on both sides insulating spacers, - formation of semiconductor source and drain blocks by growth of at least one semiconductor material on either side of the spacers.
    [8" id="c-fr-0008]
    8. Method according to one of claims 1 to 7, further comprising, after step b) and prior to step c): a step of thinning the second bars (6a, 6b, 6c).
    [9" id="c-fr-0009]
    9. A method of producing a transistor comprising a method according to one of claims 1 to 8, and then after step c), a step of forming a gate (31) in the opening (19).
    [10" id="c-fr-0010]
    10. Device provided with a semiconductor structure capable of producing at least one transistor channel, the structure being formed of bars based on a semiconductor material arranged above, the semiconductor bars being surrounded each of a sheath of another given semiconductor material having a mesh parameter different from that of said semiconductor material, so as to induce a stress on the sheaths based on the given semiconductor material.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20110049473A1|2009-08-28|2011-03-03|International Business Machines Corporation|Film Wrapped NFET Nanowire|
    WO2013095343A1|2011-12-19|2013-06-27|Intel Corporation|Group iii-n nanowire transistors|
    US20140175379A1|2012-12-20|2014-06-26|Benjamin Chu-Kung|Epitaxial film on nanoscale structure|
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    CN111435642A|2019-01-11|2020-07-21|中国科学院上海微系统与信息技术研究所|Three-dimensional stacked semiconductor nanowire structure and preparation method thereof|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1654690A|FR3051970B1|2016-05-25|2016-05-25|REALIZATION OF A CHANNEL STRUCTURE FORMED OF A PLURALITY OF CONSTRAINED SEMICONDUCTOR BARS|
    FR1654690|2016-05-25|FR1654690A| FR3051970B1|2016-05-25|2016-05-25|REALIZATION OF A CHANNEL STRUCTURE FORMED OF A PLURALITY OF CONSTRAINED SEMICONDUCTOR BARS|
    US15/603,738| US10141424B2|2016-05-25|2017-05-24|Method of producing a channel structure formed from a plurality of strained semiconductor bars|
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