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    • 专利摘要:
    An electronic device (100) comprising at least: a plurality of MOSFET transistors (102), among which first transistors (104) are such that each first transistor comprises a channel in which a concentration of dopants of the same type as those present in the source and drain of said first transistor is greater than that in the channel of each of the other transistors of said plurality of transistors; and an identification circuit (106) capable of determining a unique identifier of the electronic device from at least one intrinsic electrical characteristic of each of the first transistors whose value depends at least in part on the conductance of said first transistor.
    公开号:FR3051600A1
    申请号:FR1654544
    申请日:2016-05-20
    公开日:2017-11-24
    发明作者:Romain Wacquez；Jacques Fournier；Carlo Reita
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    ELECTRONIC DEVICE WITH IDENTIFICATION OF PUF TYPE
    DESCRIPTION
    TECHNICAL FIELD AND PRIOR ART The invention relates to the field of security and identification of electronic devices such as electronic chips and / or electronic integrated circuits, used in particular in embedded systems or connected objects (loT, or " Internet of Things ").
    An approach called PUF ("Physically Unclonable Function") to identify or authenticate in a secure and unique way a circuit or an electronic chip is to identify unique characteristics and specific to this circuit to identify this circuit, similar to fingerprints of a person. Ideally, these characteristics must be stable in time (against aging), stable with respect to variations related to the measurement conditions (current, voltage and external / environmental conditions of measurement such as temperature), and be impossible to duplicate materially or mathematically (ie via the creation of a mathematical model capable of replacing the material elements comprising the unique characteristics). Any manipulation or modification of the circuit or the chip must also cause a modification of these characteristics so that the reading of this identifier can guarantee the integrity of the circuit or the chip. Thus, a malicious manipulation of the circuit or the chip must not allow the duplication of this function PUF, nor an alteration of the results of this function (without destroying the chip in its entirety).
    A first solution for enabling such identification consists in integrating into the circuit electronic components capable of generating a variable and strictly different delay of circuit circuit as a result of variations in intra-plate, intra-batch and batch-to-batch manufacturing processes. The value of this delay corresponds to the unique identifier. These electronic components form, for example, one or more ring oscillators dedicated to this identification.
    The disadvantages of this first solution are that the measured time is unstable, especially in temperature, and that these electronic components can be modeled mathematically through learning methods.
    A second solution for carrying out such an identification consists in using memory elements (SRAM cells) of the circuit and in considering that the memory states in which these memory elements initialize (states of metastability) form together the identifier of the circuit. Such a solution is for example described in D. E. Holcomb et al., "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers", IEEE Transactions on Computers, Vol. 58, No. 9, September 2009.
    However, this solution has the disadvantage that the memory elements used to generate the identifier are sensitive to the current, voltage and temperature variations to which these memory elements are subjected, as well as to variations related to the aging of the circuit. In addition, this solution requires the implementation of important error correction codes and post-processing algorithms which are expensive to implement and which also cause security problems because they make this vulnerable. solution against software attacks (the post-processing can be attacked by physical attacks such as the spying of auxiliary channels or the injection of faults, to invasively recover the measured PUF value.
    In addition, in such memory elements, there is a correlation between the metastable states of a line of memory cells fed by the same power supply line. The generated identifier therefore has a certain predictability which is not desired for a PUF type identifier. Finally, there are also invasive attacks to clone these memory cells, as described in the document "Cloning Physically Unclonable Functions" by C. Helfmeier et al., Hardware-Oriented Security and Trust (HOST), 2013 IEEE International Symposium on, 2-3 June 2013, pages 1-6.
    STATEMENT OF THE INVENTION
    An object of the present invention is to propose an electronic device that can be identified, or authenticated, via an identification, or an authentication, of the PUF type and that does not have the disadvantages described above, that is to say, allowing an identification via an identifier that is stable over time and stable with respect to the variations in voltage, current and temperature at which the electronic device is likely to be subjected, which is not predictable, which reduces the need for codes error correction and which reduces the security risks in the face of physical attacks and modeling.
    For this, the invention proposes an electronic device comprising at least: a plurality of MOSFET transistors among which first transistors are such that each first transistor comprises a channel in which a concentration of dopants of the same type (of conductivity) as those present in the source and drain of said first transistor is greater than that in the channel of each of the other transistors of said plurality of transistors of the same conductivity type as said first transistor; and an identification circuit able to determine a unique identifier of the electronic device from at least one intrinsic electrical characteristic of each of the first transistors whose value depends at least in part on the conductance of said first transistor.
    In the first transistors, a very light doping is intentionally added to the channels of these transistors, this doping being of N type for NMOS transistors and of P type for PMOS transistors. The concentration of these added dopants may be of the order of 1.10 6 at / cm 2 or between about 5 × 10 6 at / cm 2 and 8 × 10 6 at / cm 2.
    By doping the channels of the first transistors (which are those intended to be used to generate the identifier of the device) of identical type to the type of carriers present in the source and drain areas of each of these first transistors, the mismatch or non-matching (corresponding to differences, or local variations from one transistor to another), increases. This increase in the mismatch, or non-matching, of the transistors thus makes it possible to achieve a good differentiation of the electrical characteristics between the transistors that are used for the determination of the unique identifier. Thus, the identification made is much more stable vis-à-vis the different possible variations on the voltages, currents and temperatures to which the electronic device is likely to be subjected.
    This increase in the stability of the identification therefore makes it possible to greatly reduce the need for error correction codes if the device makes use of such codes.
    In addition, the predictability of the identifier is greatly reduced because when the first transistors form memory cells which, with their states at initialization (that is to say when powering the memory cells), define the identifier of the device, the increase of the mismatch of the transistors used for identification leads to a greater de-correlation between the metastable states of the memory cells.
    Moreover, by virtue of this increase in the mismatch between the transistors, the identification can be carried out using electrical characteristics of the transistors other than those of the initial memory states of memory cells, for example circulating current values. in these transistors.
    Depending on the doping level of the channels of the first transistors, the non-matching dose (mismatch) can be controlled.
    Finally, compared to the prior art, this solution reduces the security risks in the face of physical attacks because, if the electronic device is made on an SOI substrate (for example with MOSFET transistors of the FDSOI type), the presence of the buried dielectric (BOX) is present. at the lower interface of the transistors will make more complex the observation of the photonic emission of the circuit and thus its cloning.
    Risks to modelings are also reduced because the electrical characteristic of each transistor is determined by the implantation of a low dose of dopants in the channel. The concentration of dopants in the channel then does not allow recovery of the atomic orbitals, and the dopant distribution is then discretized. This situation results directly from a purely stochastic process, namely ion implantation.
    When these dopants added in the channels of first transistors are N-type (first NMOS type transistors), these dopants may be phosphorus and / or arsenic. When these dopants added in channels of first transistors are of type P (first PMOS type transistors), these dopants may be boron and / or BF2.
    The transistors of said plurality of MOSFET transistors may advantageously be FD-SOI type.
    The FD-SOI transistors correspond to MOS transistors made on a semiconductor-on-insulator type substrate such as a silicon-on-insulator substrate, and which are completely deserted or completely depleted (FD for "Fully-Depleted").
    In a conventional FD-SOI transistor, the channel is said to be "intrinsic", that is to say that no dopant is added in the channel, nor for a P-type transistor, nor for an N-type transistor. There is however a residual doping, also called intrinsic doping, very low, naturally occurring in the semiconductor of the substrate used for their realization and which does not electrically impact the operation of the FD-SOI transistor. This residual doping is most often of the P type and is, for example, between about 1 × 10 -1 at / cm 2 and 1 × 10 7 at / cm 2 (which corresponds to a negligible quantity of dopants because, for example, the typical volume of The channel of an FD-SOI transistor made in 28 nm technology is about 3.2 × 10 -6 cm -1, ie between about 0.032 and 0.32 "single dopant" in a channel).
    Thus, when the concentration of the dopants added in the channels of the first transistors is, for example, of the order of 1.10 6 at / cm 2, this level of doping is approximately 100 to 1000 times greater than that naturally present in the channel of a PMOS transistor, i.e., about 100 to 1000 times greater than the intrinsic concentration of dopants in the substrate. In the case of an NMOS transistor, these dopants may be of the opposite type to those naturally present in the channel of this transistor. and are therefore distinguished from these dopants which have opposite effects (electron donors and electron acceptors).
    Such FD-SOI transistors have many electrical advantages compared to conventional CMOS transistors, and intrinsically have a better mismatch, or mismatch. In other words, two FD-SOI transistors of the same design have little differences, or variations, local from one transistor to another. However, by doping the channels of the FD-SOI transistors intended to be used to generate the identifier of the device, this mismatch increases sharply, thus making it possible to achieve a good differentiation of the electrical characteristics between the FD-SOI transistors which are used for the transmission. determination of the unique identifier.
    Finally, the use of FD-SOI transistors is also advantageous because such transistors are less sensitive to attacks from the rear face of the substrate on which these transistors are made.
    This electronic device can advantageously be made in FDSOI technology 28 nm or less, for example 14 nm. The gate length of the transistors of the electronic device is, for example, less than or equal to approximately 20 nm in order to obtain electrical behaviors of the transistors that lead to the mismatch.
    As a variant, the transistors of the said plurality of MOSFET transistors may be of bulk type, that is to say comprising their active zones produced in a solid semiconductor layer (the thickness of which is, for example, greater than about 10 μm). ) and / or Fin-FET.
    When the transistors of the said plurality of MOSFET transistors are of bulk and / or FinFET type, the channels of these transistors thus comprise dopants of the opposite type to those present in the source and drain of these transistors (an NMOS transistor having conventionally a doped channel P and a PMOS transistor conventionally having an N-doped channel). Among these transistors, the channels of the first transistors comprise, in addition to dopants of the opposite type to those present in the source and drain, dopants of the same type as those present in the source and drain of these first transistors, which differentiates them from the other transistors of said plurality of transistors whose channels comprise only dopants of the opposite type to those present in the source and drain.
    In a first embodiment, the identification circuit may be able to compare in pairs the current values flowing in the first identically polarized transistors, the results of these comparisons being able to be used to form the unique identifier of the device. electronic. Indeed, since the doping of the channel modifies the conductance of a transistor, which itself varies as a function of the potential Vg applied to the gate of the transistor, the differences between the currents of the first identically polarized transistors are data. particularly relevant for forming the identifier of the electronic device.
    The currents read by the identification circuit may correspond to the Ion currents of the first transistors, that is to say the current flowing between the drain and the source of the transistor when Vgs (gate-source voltage) = Vos (voltage drain- source) = Valim (transistor supply voltage).
    As a variant, the comparisons made to obtain the identifier can be carried out not directly on the values of the drain-source currents of the transistors, but on different electrical characteristics that can be obtained from these currents, for example by comparing the voltages of threshold of the first transistors whose values can be obtained from those of the currents flowing in the transistors (for example by dichotomy by measuring the current Ion for different values of the voltage Vg applied to the gate of the transistor).
    In this case, the identification circuit may comprise at least: a multiplexer comprising several inputs each connected to the drain or the source of one of the first transistors, and two outputs; and a comparator comprising two inputs connected to the two outputs of the multiplexer, and capable of outputting a signal the value of which depends on the result of the comparison between the values of the currents applied to the inputs of the comparator.
    Thus, the different possible combinations of two transistors among all the first transistors make it possible to obtain a large number of comparison results forming the unique identifier of the electronic device.
    According to a second embodiment, the electronic device may be such that: the first transistors form several SRAM memory cells, and the identification circuit is able to read an initial memory state of each of the SRAM memory cells formed by the first ones. transistors, the initial memory states of said SRAM memory cells together forming the unique identifier of the electronic device.
    In this second embodiment, because of the increase of the mismatch between the transistors which generates an increase in the stability of the initial states of the memory cells, the necessary error correction codes are then greatly reduced.
    Said concentration of dopants of the same type as those present in the sources and drain of said first transistor may be between approximately 5.10 ^^ and 8.10 ^^ at / cm ^ and for example of the order of 1.10 ^ ® at / cm ^.
    The gate of each of the first transistors may have a length less than that of the gate of each of the other transistors, for example less than or equal to approximately 20 nm. Such first transistors are advantageous because the increase in the mismatch obtained is particularly important in this case.
    Each of the first transistors may have an active zone of greater thickness than that of the active zone of each of the other transistors, for example greater than or equal to approximately 10 nm for FD-SOI transistors. Such first transistors are advantageous because the increase in the mismatch obtained is particularly important in this case. The invention also relates to a method for producing an electronic device, comprising at least the steps of: - producing a plurality of MOSFET transistors, among which first transistors are such that each first transistor comprises a channel in which a concentration of dopants of the same type as those present in the source and drain of said first transistor is greater than that in the channel of each of the other transistors of said plurality of transistors of the same conductivity type as said first transistor; - Realization of an identification circuit capable of determining a unique identifier of the electronic device from at least one intrinsic electrical characteristic of each of the first transistors whose value depends at least in part on the conductance of said first transistor. The addition of these dopants in the channels of the first transistors has little impact on the other steps used for producing the electronic device and is therefore compatible with existing methods.
    The realization of the first transistors may comprise the implementation of a dopant implantation in the semi-oonduoteur intended to form the active zones of each of the first transistors, with a dose of between approximately 5.10 ^^ and 5.10 ^^ at / cm and an energy of between about 0.5 and 20 keV, and advantageously between about 2 and 3 keV or between about 2 keV and 10 keV (10 keV in the case of phosphorus dopants). The energy with which the dopants are implanted can be adapted according to the implanted species and the presence or absence of a protective layer present on the channels, the thickness of this protective layer may be greater than about 10 nm. The invention also relates to a method for identifying an electronic device comprising a plurality of MOSFET transistors, among which first transistors each comprise a channel having a doping level greater than that of the channel of each of the other transistors of said plurality transistors, comprising at least the steps of: - reading currents flowing in the first identically polarized transistors; two-to-two comparison of the values of said currents, the results of these comparisons forming the unique identifier of the electronic device. The invention also relates to a method for identifying an electronic device comprising a plurality of MOSFET transistors, among which first transistors are such that each first transistor comprises a channel in which a concentration of dopants of the same type as those present in the source and drain of said first transistor is greater than that in the channel of each of the other transistors of said plurality of transistors of the same conductivity type as said first transistor, the first transistors forming a plurality of SRAM memory cells, comprising at least one reading step an initial memory state of each of the SRAM memory cells formed by the first transistors, the initial memory states of said SRAM memory cells together forming the unique identifier of the electronic device.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIG. 1 represents a part of an electronic device, object of the present invention, according to a first embodiment; FIGS. 2A to 2D show steps for producing a transistor for performing identification within an electronic device, object of the present invention, according to an example embodiment; FIG. 3 diagrammatically represents an electronic device, object of the present invention, according to a second embodiment.
    Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Referring to Figure 1 which shows a portion of an electronic device 100 according to a first embodiment.
    The electronic device 100 corresponds to an electronic chip or an integrated circuit made from a semiconductor-on-insulator substrate, for example SOI (silicon on insulator).
    The electronic device 100 includes many completely deserted MOSFET transistors 102, here FD-SOI type ("Fully-Depleted Silicon On Insulator"), that is to say having a channel formed in a very thin semiconductor layer disposed on a buried dielectric.
    A portion of the transistors 102 of the electronic device 100, called first transistors 104, are intended to serve for the identification of the electronic device 100. These first transistors 104 each comprise a channel in which a concentration of dopants of the same type as those present in the source and drain of said first transistor 104 is greater than that in the channel of each of the other transistors 102.
    The electronic device 100 also comprises an identification circuit 106 making it possible to determine a unique identifier of the electronic device 100.
    The identification circuit 106 comprises a multiplexer 108 provided with several inputs, here n inputs referenced El - En, each connected to the drain or the source of one of the first transistors 104. The multiplexer 108 also has two outputs S1 and S2 on which currents flowing in two of the first transistors 104 are able to be delivered.
    The currents flowing between the drain and the source of the first transistors 104 are read by polarizing these first transistors 104 identically. For example, the currents read may correspond to the Ion currents of the first transistors 104, that is to say the current flowing between the drain and the source of the transistor when Vgs (gate-source voltage) = Vds (drain-source voltage) = Valim (transistor supply voltage). Alternatively, the currents of the first transistors 104 can be read by polarizing the first transistors 104 with voltages of values different from that of Valim.
    The identification circuit 106 also comprises a comparator 110 comprising two inputs connected to the two outputs of the multiplexer 108, and capable of outputting a signal whose value is a function of the result of the comparison between the values of the currents received at the input by the Comparator 110. In the example of FIG. 1, the comparator corresponds to a differential amplifier. Depending on whether the value of the current applied to a first of the two inputs of the comparator 110 is greater or smaller than that of the current applied to a second of the two inputs of the comparator 110, the voltage outputted by the comparator 110 can be likened to a signal binary having a value equal to the supply voltage of the comparator 110 assimilated to a '1' binary, or a zero value assimilated to '0' binary.
    Thanks to the multiplexer 108 and the comparator 110, the identification circuit 106 thus compares in pairs the values of the currents flowing in the first transistors 104 which are polarized identically. The different values delivered by the comparator 110 for these different comparisons together form a binary number corresponding to the unique identifier of the electronic device 100.
    In the example of FIG. 1, the identification circuit 106 is able to make comparisons of Ion currents of twelve first transistors 104, thus making it possible to make 66 comparisons of currents. The identifier can therefore correspond to a binary number that can have up to 66 bits when the identification circuit 106 is capable of detecting a stable difference between all the pairs of currents measured. In the event of errors, post-processing elements can correct these errors to avoid them.
    In the example of FIG. 1, the first transistors 104 are chosen from the transistors 102 such that they are not located at the edges of the device 100. This makes it possible to consider only so-called local variations (and therefore related to stochastic phenomena, purely random) because all the first transistors 104 are identical with respect to the manufacturing processes implemented. The "edge effects" that can affect the characteristics of the transistors are in this case deleted. It also enables authentication based on a "challenge response" or "challenge response" mechanism that makes it possible to authenticate the electronic device in a secure manner.
    An exemplary embodiment of one of the first FD-SOI type transistors 104 is described with reference to FIGS. 2A to 2D. Only the main steps of the embodiment of this transistor 104 are described below.
    The first transistors 104 are made from an SOI substrate 112 having a thick semiconductor layer 114, for example comprising silicon, forming the mechanical support of the substrate 112 (FIG. 2A). The SOI substrate 112 also comprises a buried dielectric layer 116, comprising for example SiO 2, disposed on the thick layer 114. The SOI substrate 112 also comprises a thin layer 118 of semiconductor disposed on the buried dielectric layer 116 and intended to serve the production of the active areas of the transistors 102. The thickness of the thin film 118 is for example between about 7 nm and 8 nm, or more generally less than about 20 nm, and that of the buried dielectric layer 116 is for example about 25 nm. The FD-SOI character of the first transistors 104 is obtained in particular thanks to this very small thickness of the thin layer 118.
    As shown in FIG. 2B, a doping of the thick layer 114 is implemented in order to form the N or P wells 120 of the first transistors 104. The N or P wells of the other transistors 102 are also formed during this step.
    Very low doping of portions 122 of the thin layer 118 intended to form the active areas of the first transistors 104 is then realized. This doping is here obtained by implantation of dopants at very low dose, for example between about 5.10 ^^ and 5.10 ^^ at / cm ^ with a low energy, for example between about 0.5 and 20 keV, and advantageously between about 2 and 10 keV or equal to about 10 keV. Thus, the dopant concentrations obtained in these portions 122 of the thin layer 118 are, for example, between about 5 × 10 -8 and 8 × 10 -3 / cm 2.
    The first transistors 104 may be of the NMOS and / or PMOS type (NMOS and PMOS when a portion of these first transistors 104 are of the NMOS type and the other first transistors 104 are of the PMOS type). The dopants implanted in the channels of the first transistors 104 are of the same type of conductivity as these transistors 104. Thus, for an NMOS transistor, the implanted dopants are, for example, dopant species of As and / or P. For a PMOS transistor the implanted dopants are, for example, dopant species of B and / or BF2.
    A gate 124 is then made for each of the first transistors 104 on the parts 122 (Figure 2C). The gates of the other transistors 102 are also produced during this step.
    The sources 126 and drain 128 of the first transistors 104 are then doped (as well as the sources and the drain of the other transistors 102), with doping levels much greater than that previously used for doping the channels 130 of the first transistors 104, around the lightly doped channels 130 of the first transistors 104 (FIG. 2D).
    The first transistors 104 thus produced are distinguished from the other transistors 102 of the device 100 by their weakly doped channel, the channels of the other transistors 102 not being doped (apart from an intrinsic doping of the P type, for example between about 1.10 ^^ at / cm ^ and 1.10 ^ ® at / cm ^).
    Advantageously, the gate length of the first transistors 104 may be less than that of the other transistors 102 of the device 100 (which is for example 22 nm), and for example less than or equal to approximately 20 nm. This makes it possible to increase the mismatch between the transistors. Indeed, the dopants added in the channel serve as potential wells for the free charges (the electronic current), and it is this current flowing through this potential well that increases the mismatch. With a small gate length, the coupling of this current with the source and drain zones is improved.
    In addition, it is possible that the portions 122 of the thin layer 118 intended to form the active areas of the first transistors 104 have a thickness greater than that of the portions of the thin layer 118 intended to form the active zones of the other transistors 102 of the device For example, the thickness of the active areas of the other transistors 102 may be between about 7 nm and 8 nm, and that of the active areas of the first transistors 104 may be greater than or equal to about 10 nm, or between about 10 nm. nm and 20 nm. This makes it possible to increase the ionization energy of the dopants present in the channels of the first transistors 104, and thus to increase the mismatch between the transistors.
    As a variant of the first embodiment previously described, it is possible for the detection circuit 106 not to make a comparison of the values of the currents flowing in the first transistors 104, but a comparison of values of one or more other electrical characteristics of the first transistors 104, for example the threshold voltage Vt of the first transistors 104. In this case, the detection circuit 106 comprises an additional calculation element interposed between the multiplexer 108 and the comparator 110, connected to the outputs S1 and S2 of the multiplexer 108 and at the inputs of the comparator 110. This additional calculation element delivers at its outputs the values of the desired electrical characteristics, for example those of the threshold voltages of the transistors 104, calculated from the values of the currents delivered at the output of the multiplexer 108. For example, the threshold voltage of a first transistor 104 can be calculated by by measuring the current Ion for different values of the voltage Vg applied to the gate of this first transistor 104.
    Comparisons of the values of the currents flowing in the first transistors 104 can also be made at different drain and gate polarizations of the first transistors 104.
    According to a second embodiment shown diagrammatically in FIG. 3, the electronic device 100 comprises SRAM memory cells 132 formed from the MOSFET transistors 102, for example of the FD-SOI type. Among these SRAM memory cells 132, some are intended to serve for the identification of the electronic device 100. In the diagram of FIG. 3, these SRAM memory cells are referenced 134. These SRAM memory cells 134 are formed by the first transistors 104 which have a doped channel.
    The initial memory states of these SRAM cells 134 are read by the detection circuit 106, these initial memory states forming the unique identifier of the electronic device 100.
    The detection circuit 106 comprises for example elements operating in a similar manner to those described in the document by R. Maes et al. "A Soft Decision Helper Data Algorithm for SRAM PUFs," Information Theory, 2009. ISIT 2009. IEEE International Symposium on, pp. In this case, the information postprocessing and the error correction code is implemented in accordance with an SRAM based PUF.
    In the embodiments described above, the electronic device 100 comprises transistors 102 of the FD-SOI type. As a variant, it is possible for the electronic device 100 to comprise transistors 102 of bulk or FinFET type.
    In this case, the channels of the transistors 102 thus comprise dopants of the opposite type to those present in the source and drain of these transistors (an NMOS transistor having a P-doped channel and a PMOS transistor having an N-doped channel). The channels of the first transistors 104 also comprise, in addition to dopants of the opposite type to those present in the source and drain, dopants of the same type as those present in the source and drain of these first transistors, which differentiates them from other transistors. 102 whose channels contain only dopants of the opposite type to those present in the source and drain.
    Thus, considering for example a set of transistors 102 of the bulk or FinFET type, the NMOS transistors (whether they correspond to first transistors 104 or to the other transistors) comprise a P-doped channel and N-doped sources and drain and the transistors PMOS (that they correspond to first transistors 104 or to other transistors) comprise an N-doped channel and P-doped sources and drain. Moreover, the channels of the first NMOS-type transistors 104 comprise, in addition to P-type dopants. predominantly present in these channels, N-type dopants added via a distinct doping step, and the channels of the first PMOS-type transistors 104 comprise, in addition to N-type dopants predominantly present in these channels, added P-type dopants via a separate doping step. This or these distinct doping steps can be implemented in a similar manner to the previous description relating to the realization of the FD-SOI transistors.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    An electronic device (100) comprising at least: a plurality of MOSFET transistors (102), among which first transistors (104) are such that each first transistor (104) comprises a channel (130) in which a dopant concentration of the same type as those present in the source and drain of said first transistor (104) is greater than that in the channel of each of the other transistors of said plurality of transistors (102) of the same conductivity type as said first transistor (104); and an identification circuit (106) capable of determining a unique identifier of the electronic device (100) from at least one intrinsic electrical characteristic of each of the first transistors (104) whose value depends at least in part on the conductance of said first transistor (104).
    [2" id="c-fr-0002]
    An electronic device (100) according to claim 1, wherein the transistors of said plurality of MOSFET transistors (102) are of FD-SOI type.
    [3" id="c-fr-0003]
    An electronic device (100) according to claim 1, wherein the transistors of said plurality of MOSFET transistors (102) are of bulk and / or FinFET type.
    [4" id="c-fr-0004]
    4. An electronic device (100) according to claim 1, wherein the identification circuit (106) is able to compare in pairs the current values flowing in the first transistors (104) polarized identically, the results of these comparisons being intended to form the unique identifier of the electronic device (100).
    [5" id="c-fr-0005]
    5. Electronic device (100) according to claim 4, wherein the identification circuit (106) comprises at least: a multiplexer (108) having a plurality of inputs each connected to the drain or the source of one of the first transistors ( 104), and two outputs; and a comparator (110) comprising two inputs connected to the two outputs of the multiplexer (108), and capable of outputting a signal the value of which depends on the result of the comparison between the values of the currents applied to the inputs of the comparator (110); ).
    [6" id="c-fr-0006]
    6. Electronic device (100) according to one of claims 1 to 3, wherein: - the first transistors (104) form a plurality of SRAM memory cells (134), and - the identification circuit (106) is readable an initial memory state of each of the SRAM memory cells (134) formed by the first transistors (104), the initial memory states of said SRAM memory cells (134) together forming the unique identifier of the electronic device (100).
    [7" id="c-fr-0007]
    7. Electronic device (100) according to one of the preceding claims, wherein said dopant concentration of the same type as those present in the source and drain of said first transistor (104) is between about 5.10 ^^ and 8.10 ^ ® at / cc.
    [8" id="c-fr-0008]
    8. Electronic device (100) according to one of the preceding claims, wherein the gate (124) of each of the first transistors (104) has a length less than that of the gate of each of the other transistors (102).
    [9" id="c-fr-0009]
    The electronic device (100) of claim 6, wherein said gate (124) of each of the first transistors (104) has a length of less than or equal to about 20 nm.
    [10" id="c-fr-0010]
    10. Electronic device (100) according to one of the preceding claims, wherein each of the first transistors (104) has an active area (122) of greater thickness than the active area of each of the other transistors (102).
    [11" id="c-fr-0011]
    The electronic device (100) of claim 10, wherein said active region (122) of each of the first transistors (104) has a thickness greater than or equal to about 10 nm.
    [12" id="c-fr-0012]
    12. A method of producing an electronic device (100), comprising at least the steps of: - producing a plurality of transistors (102) MOSFETs, among which first transistors (104) are such that each first transistor (104) ) comprises a channel (130) in which a concentration of dopants of the same type as those present in the source and drain of said first transistor (104) is greater than that in the channel of each of the other transistors of said plurality of transistors (102) of the same type of conductivity as said first transistor (104); - Realization of an identification circuit (106) able to determine a unique identifier of the electronic device (100) from at least one intrinsic electrical characteristic of each of the first transistors (104) whose value depends at least in part the conductance of said first transistor (104).
    [13" id="c-fr-0013]
    13. The method of claim 12, wherein the realization of the first transistors (104) comprises the implementation of a dopant implantation in the semiconductor (118) for forming the active areas (122) of each of the first transistors (104), with a dose of between about 5.10 ^^ and 5.10 ^^ at / cm ^ and an energy of between about 0.5 and 20 keV.
    [14" id="c-fr-0014]
    A method of identifying an electronic device (100) having a plurality of MOSFET transistors (102), among which first transistors (104) are such that each first transistor (104) includes a channel (130) in which a concentration of dopants of the same type as those present in the source and drain of said first transistor (104) is greater than that in the channel of each of the other transistors of said plurality of transistors (102) of the same conductivity type as said first transistor ( 104), comprising at least the steps of: - reading currents flowing in the first identically polarized transistors; two-to-two comparison of the values of said currents, the results of these comparisons forming the unique identifier of the electronic device.
    [15" id="c-fr-0015]
    A method of identifying an electronic device (100) having a plurality of MOSFET transistors (102), among which first transistors (104) are such that each first transistor (104) includes a channel (130) in which a concentration of dopants of the same type as those present in the source and drain of said first transistor (104) is greater than that in the channel of each of the other transistors of said plurality of transistors (102) of the same conductivity type as said first transistor ( 104), the first transistors (104) forming a plurality of SRAM memory cells (134), comprising at least one step of reading an initial memory state of each of the SRAM memory cells (134) formed by the first transistors (104), the initial memory states of said SRAM memory cells (134) together forming the unique identifier of the electronic device (100).
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    同族专利:
    公开号 | 公开日
    EP3246943B1|2022-02-16|
    FR3051600B1|2018-12-07|
    EP3246943A1|2017-11-22|
    US20170338819A1|2017-11-23|
    US9991892B2|2018-06-05|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    WO2000049538A1|1999-02-17|2000-08-24|Icid, Llc|A system for providing an integrated circuit with a unique identification|
    US20050275001A1|2002-08-15|2005-12-15|Koninklijke Philips Electronics N.V.|Integrated circuit and method of manufacturing same|
    US20120326752A1|2011-06-24|2012-12-27|International Business Machines Corporation|Design method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range|
    DE10105725B4|2001-02-08|2008-11-13|Infineon Technologies Ag|Semiconductor chip with a substrate, an integrated circuit and a shielding device|
    US7840803B2|2002-04-16|2010-11-23|Massachusetts Institute Of Technology|Authentication of integrated circuits|
    US9331012B2|2012-03-08|2016-05-03|International Business Machines Corporation|Method for fabricating a physical unclonable interconnect function array|
    US8759976B2|2012-08-09|2014-06-24|International Business Machines Corporation|Structure with sub-lithographic random conductors as a physical unclonable function|
    KR101332517B1|2012-08-21|2013-11-22|한양대학교 산학협력단|Apparatus and method for processing authentication information|
    FR3026253B1|2014-09-19|2016-12-09|Commissariat Energie Atomique|SYSTEM AND METHOD FOR SECURING AN ELECTRONIC CIRCUIT|
    US9576914B2|2015-05-08|2017-02-21|Globalfoundries Inc.|Inducing device variation for security applications|
    US10026648B2|2016-03-08|2018-07-17|International Business Machines Corporation|FDSOI with on-chip physically unclonable function|FR3066291A1|2017-05-10|2018-11-16|Commissariat A L'energie Atomique Et Aux Energies Alternatives|METHOD OF SECURING AN INTEGRATED CIRCUIT DURING ITS ACHIEVEMENT|
    US11044107B2|2018-05-01|2021-06-22|Analog Devices, Inc.|Device authentication based on analog characteristics without error correction|
    US10749694B2|2018-05-01|2020-08-18|Analog Devices, Inc.|Device authentication based on analog characteristics without error correction|
    US11245680B2|2019-03-01|2022-02-08|Analog Devices, Inc.|Garbled circuit for device authentication|
    US10769327B1|2019-06-13|2020-09-08|International Business Machines Corporation|Integrated circuit authentication using mask fingerprinting|
    法律状态:
    2017-05-30| PLFP| Fee payment|Year of fee payment: 2 |
    2017-11-24| PLSC| Publication of the preliminary search report|Effective date: 20171124 |
    2018-05-28| PLFP| Fee payment|Year of fee payment: 3 |
    2019-05-31| PLFP| Fee payment|Year of fee payment: 4 |
    2020-05-30| PLFP| Fee payment|Year of fee payment: 5 |
    2021-05-31| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1654544A|FR3051600B1|2016-05-20|2016-05-20|ELECTRONIC DEVICE WITH IDENTIFICATION OF PUF TYPE|
    FR1654544|2016-05-20|FR1654544A| FR3051600B1|2016-05-20|2016-05-20|ELECTRONIC DEVICE WITH IDENTIFICATION OF PUF TYPE|
    US15/600,331| US9991892B2|2016-05-20|2017-05-19|Electronic device having a physical unclonable function identifier|
    EP17171958.6A| EP3246943B1|2016-05-20|2017-05-19|Electronic device having puf-type identification|
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