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    • 专利摘要:
    A multiplier digital to analog converter (MDAC) comprising: first and second inputs (210, 240) for receiving first and second differential input signals (Vinp, Vinn); a differential amplifier (202) having first and second differential input nodes (204, 234) and first and second differential output nodes (VOUT +, VOUT-); a first capacitor (205) having one of its nodes coupled to the first differential input node (204) and its other node coupled to the first input (210) through a first switch (208) and at least one reference supply voltage node via one or more other switches (402); and second and third capacitors (406, 408) each having one of its nodes coupled to either the first differential input node (204); either at the first differential output node (VOUT-); either at the first input (210).
    公开号:FR3048317A1
    申请号:FR1651640
    申请日:2016-02-26
    公开日:2017-09-01
    发明作者:Mounir Boulemnakher；Tual Stephane Le
    申请人:STMicroelectronics SA；
    IPC主号:
    专利说明:

    - le cas VI : ainsi: - le cas V2 : - le cas V3 :
    La figure 4 illustre schématiquement un circuit mettant en oeuvre le MDAC 111 de la figure 1 plus en détail selon une variante de réalisation par rapport à la figure 2.
    En figure 4, les éléments qui sont les mêmes que ceux du circuit de la figure 2 portent les mêmes références et ne seront pas décrits de nouveau en détail.
    Dans le mode de réalisation de la figure 4, la circuiterie couplée au noeud d'entrée positive 204 de l'amplificateur différentiel 202 est modifiée de la façon suivante par rapport au circuit de la figure 2.
    Le circuit de sélection 224 est remplacé par un commutateur 402, couplant le noeud 206 à la masse. En outre, deux condensateurs additionnels 406, 408 sont par exemple prévus, chacun ayant l'un de ses noeuds couplé au noeud d'entrée positive 204 de l'amplificateur différentiel 202. Les condensateurs 406, 408 ont par exemple chacun une capacité égale à sensiblement la moitié de la capacité C du condensateur 205.
    Le condensateur 406 a son autre noeud couplé par l'intermédiaire d'un commutateur 410 à un circuit de sélection 412. Le circuit de sélection 412 permet par exemple de sélectionner l'une des tensions de référence +Vrejt et -Vjyrjr et de la coupler au condensateur 406, la sélection étant basée sur le signal de sortie de 1,5 bit provenant de l'ADC flash. Par exemple, le circuit de sélection 412 comprend un commutateur 414 couplé entre le commutateur 410 et le rail de tension de référence -VREp et un commutateur 416 couplé entre le commutateur 410 et le rail de tension de référence +Vp>£p. Un autre commutateur 418 est par exemple couplé entre le condensateur 406 et le rail de tension de masse.
    De façon similaire, le condensateur 408 a son autre noeud couplé par l'intermédiaire d'un commutateur 420 à un circuit de sélection 422. Le circuit de sélection 422 permet par exemple de sélectionner l'une des tensions de référence +VREp et et de la coupler au condensateur 408, la sélection étant basée sur le signal de sortie de 1,5 bit provenant de l'ADC flash. Par exemple, le circuit de sélection 422 comprend un commutateur 424 couplé entre le commutateur 420 et le rail de tension de référence -Vref et un commutateur 426 couplé entre le commutateur 420 et le rail de tension de référence +Vppp. Un autre commutateur 428 est par exemple couplé entre le condensateur 408 et le rail de tension de masse.
    De façon similaire, la circuiterie couplée au noeud d'entrée négative 234 de l'amplificateur différentiel 202 est modifiée de la façon suivante par rapport au circuit de la figure 2.
    Le circuit de sélection 254 est remplacé par un commutateur 432, couplant le noeud 236 à la masse. En outre, deux condensateurs additionnels 436, 438 sont par exemple prévus, chacun ayant l'un de ses noeuds couplé au noeud d'entrée négative 234 de l'amplificateur différentiel 202. Chacun des condensateurs 436, 438 a par exemple une capacité égale à sensiblement la moitié de la capacité C du condensateur 235.
    Le condensateur 436 a son autre noeud couplé par l'intermédiaire d'un commutateur 440 à un circuit de sélection 442. Le circuit de sélection 442 permet par exemple de sélectionner l'une des tensions de référence +Vppp et “Vppp et de la coupler au condensateur 436, la sélection étant basée sur le signal de sortie de 1,5 bit provenant de l'ADC flash. Par exemple le circuit de sélection 442 comprend un commutateur 444 couplé entre le commutateur 440 et le rail de tension de référence -Vppp et un commutateur 446 couplé entre le commutateur 440 et le rail de tension de référence +Vppp. Un autre commutateur 448 est par exemple couplé entre le condensateur 436 et le rail de tension de masse.
    De façon similaire, le condensateur 438 a son autre noeud couplé par l'intermédiaire d'un commutateur 450 à un circuit de sélection 452. Le circuit de sélection 452 permet par exemple de sélectionner l'une des tensions de référence +Vppp et -Vppp et de la coupler au condensateur 438, la sélection étant basée sur le signal de sortie de 1,5 bit provenant de l'ADC flash. Par exemple, le circuit de sélection 452 comprend un commutateur 454 couplé entre le commutateur 450 et la tension de référence -Vppp et un commutateur 456 couplé entre le commutateur 450 et la tension de référence +Vp£p. Un autre commutateur 458 est par exemple couplé entre le condensateur 438 et le rail de tension de masse.
    Les commutateurs 402, 410, 420, 432, 440 et 450 sont par exemple contrôlés par le signal de phase φ2. Les commutateurs 418, 428, 448 et 458 sont par exemple contrôlés par le signal de phase φΐ. Les signaux de phase φΐ et φ2 sont par exemple générés par un circuit de commande 458 sur la base d'un signal d'horloge CLK.
    En fonctionnement, pendant une première phase, le MDAC de la figure 4 est par exemple adapté à coupler les tensions d'entrée Vinp, Vinn, aux condensateurs 205, 216, 235 et 246, d'une façon similaire à ce qui est a été représenté en figure 3A décrite précédemment. Pendant cette phase, les condensateurs 406, 408, 436 et 438 sont par exemple couplés à la masse par l'intermédiaire des commutateurs 418, 428, 448 et 458 respectivement. Une deuxième phase est illustrée en figure 5.
    La figure 5 représente une phase de fonctionnement du MDAC de la figure 4 dans laquelle les condensateurs de 216, 246 sont couplés dans des chemins de rétroaction entre les noeuds de sortie/entrée de l'amplificateur différentiel 202, les condensateurs 205, 235 sont couplés par l'intermédiaire des commutateurs 402, 432 à la masse, et chacun des condensateurs 406, 408, 436, 438 est couplé à l'un des rails de tension de référence sur la base du résultat de la conversion ADC flash.
    Sur le côté gauche et le côté droit de la figure 5, certains exemples des tensions d'entrée Vinp et Vinn sont illustrés aux mêmes niveaux VI, V2 et V3 que dans l'exemple de la figure 3B. Comme cela est représenté par des courbes en trait plein, dans le cas où la tension d'entrée Vinp est à un niveau VI compris entre -VrjtF/4 et + Vppp/4, les condensateurs 406 et 436 sont par exemple couplés au rail d'alimentation +Vreit et les condensateurs 408, 438 sont par exemple couplés au rail d'alimentation -V^p ; comme cela est représenté par des courbes en trait interrompu, si le signal d'entrée Vinp est à un niveau V2 supérieur à +Vj^pp/4 et le signal d'entrée Vinn est à ion niveau -V2 inférieur à -Vppp/4, les deux condensateurs 406, 408 sont par exemple couplés au rail d'alimentation +VREF, et les deux condensateurs 436, 438 sont par exemple couplés aü rail d'alimentation ; et comme cela est représenté par des courbes en pointillés, si le signal d'entrée Vinp est à un niveau -V3 inférieur à -Vj^pp/4 et le signal d'entrée Vinn est à un niveau V3 supérieur à V^pp/4, les deux condensateurs 406, 408 sont par exemple couplés au rail d'alimentation et les deux condensateurs 436, 438 sont par exemple couplés au rail d'alimentation +VREF.
    Un avantage du mode de réalisation du MDAC de la figure 4 est que la demande de charge sur les rails de tension de référence -Vppp et +Vppp et sur le rail de tension de masse est constante quels que soient les niveaux des signaux d'entrée Vinp, Vinn. Par exemple, la demande de charge peut être calculée de la façon suivante pour les rails de tension d'alimentation GND, +Vppp et -VREF : - la demande de charge sur le rail GND est toujours nulle : SAQ(GND gauche et droite) = -(0-V).C-(0-(-V)).C = 0 ; - demande de charge sur +VREF : SAQ (+VREF gauche et droite) = -2(+VREF-0) ; - demande de charge sur -VREF : SAQ (-VREF gauche et droite) = -2(-VREF-0).
    La figure 6 illustre le MDAC 111 de la figure 1 selon un exemple de variante de réalisation par rapport à la figure 4. Le circuit de la figure 6 est similaire au circuit de la figure 2, et les éléments similaires portent les mêmes références et ne seront pas décrits de nouveau en détail.
    Dans le mode de réalisation de la figure 6, le condensateur 205 est remplacé par deux condensateurs 602 et 604 ayant chacun une capacité C/2, en d'autres termes une capacité sensiblement égale à la moitié de la capacité C du condensateur 216. Le condensateur 602 est couplé entre le noeud 204 et un nœud 606, qui est à son tour couplé au noeud d'entrée 210 par l'intermédiaire d'un commutateur 608 contrôlé par le signal de phase φΐ. Le noeud 606 est aussi couplé par l'intermédiaire d'un commutateur 610 à un circuit de sélection 611, qui est par exemple similaire au circuit de sélection 412 de la figure 4. Le condensateur 604 est couplé entre le noeud 204 et un noeud 616, qui est à son tour couplé au noeud d'entrée 210 par l'intermédiaire d'un commutateur 618 contrôlé par le signal de phase φΐ. Le noeud 616 est aussi couplé par l'intermédiaire d'un commutateur 620 à un circuit de sélection 621, qui est aussi similaire au circuit de sélection 412 de la figure 4. Les commutateurs 610 et 620 sont par exemple contrôlés par le signal de phase φ2.
    Le circuit de la figure 6 comprend en outre une charge fictive sur le noeud d'entrée 210 formée par une autre paire de condensateurs 622, 624, comme on va le décrire maintenant. Le condensateur 622 a une capacité sensiblement égale à C/2 et est par exemple couplé entre la masse et un noeud 626. Le noeud 626 est par exemple couplé au noeud d'entrée 210 par l'intermédiaire d'un commutateur 628, et par l'intermédiaire d'un commutateur 630 à un circuit de sélection 631, qui est similaire au circuit de sélection 412 ou 442 de la figure 4. Le condensateur 624 a une capacité sensiblement égale à C/2 et est par exemple couplé entre la masse et un noeud 636. Le noeud 636 est par exemple couplé au noeud d'entrée 210 par l'intermédiaire d'un commutateur 638, et par l'intermédiaire d'un commutateur 640 à un circuit de sélection 641, qui est similaire au circuit de sélection 412 ou 422 de la figure 4. Les commutateurs 628 et 638 sont par exemple contrôlés par le signal de phase φΐ et les commutateurs 630 et 640 sont par exemple contrôlés par le signal de phase φ2.
    De façon similaire, le condensateur 235 est remplacé par deux condensateurs 642 et 644 ayant chacun une capacité C/2, en d'autres termes une capacité sensiblement égale à la moitié de la capacité C du condensateur 246. Le condensateur 642 est couplé entre le noeud 234 et un noeud 646, qui est à son tour couplé au noeud d'entrée 240 par l'intermédiaire d'un commutateur 648 contrôlé par le signal de phase φΐ. Le noeud 646 est aussi couplé par l'intermédiaire d'un commutateur 650 à un circuit de sélection 651, qui est par exemple similaire au circuit de sélection 412 de la figure 4. Le condensateur 644 est couplé entre le noeud 234 et un noeud 656, qui est à son tour couplé au noeud d'entrée 240 par l'intermédiaire d'un commutateur 658 contrôlé par le signal de phase φΐ Le noeud 656 est aussi couplé par l'intermédiaire d'un commutateur 660 à un circuit de sélection 661, qui est aussi par exemple similaire au circuit de sélection 412 de la figure 4. Les commutateurs 650 et 660 sont par exemple contrôlés par le signal de phase φ2.
    Le circuit de la figure 6 comprend en outre une charge fictive sur le noeud d'entrée 240 formée par deux autres condensateurs 662 et 664, comme on va le décrire maintenant. Le condensateur 662 a une capacité sensiblement égale à C/2 et est par exemple couplé entre la masse et un noeud 666. Le noeud 666 est par exemple couplé au noeud d'entrée 240 par l'intermédiaire d'un commutateur 668, et par l'intermédiaire d'un commutateur 670 à un circuit de sélection 671, qui est similaire au circuit de sélection 412 ou 442 de la figure 4. Le condensateur 664 a une capacité sensiblement égale à C/2 et est par exemple couplé entre la masse et un noeud 676. Le noeud 676 est par exemple couplé au noeud d'entrée 240 par l'intermédiaire d'un commutateur 678, et par l'intermédiaire d'un commutateur 680 à un circuit de sélection 681, qui est similaire au circuit de sélection 412 ou 442 de la figure 4. Les commutateurs 668 et 678 sont par exemple contrôlés par le signal de phase φΐ et les commutateurs 670 et 680 sont par exemple contrôlés par le signal de phase φ2. Les signaux de phase φΐ et φ2 sont par exemple générés par un circuit de commande 684 sur la base d'un signal d'horloge CLK.
    On va maintenant décrire plus en détail le fonctionnement du circuit de la figure 6 en faisant référence aux figures 7A et 7B.
    La figure 7A illustre une première phase dans laquelle le signal de phase φΐ est activé de telle sorte que les condensateurs 216, 602 et 604 sont couplés en parallèle entre l'entrée positive de l'amplificateur différentiel 202 et le noeud d'entrée 210. De façon similaire, les condensateurs 246, 642 et 644 sont couplés entre l'entrée négative de l'amplificateur différentiel 202 et le noeud d'entrée 240. En outre, les condensateurs 622 et 624 sont couplés en parallèle entre la masse et le noeud d'entrée 210, et les condensateurs 662 et 664 sont couplés en parallèle entre la masse et le noeud d'entrée 240. Ainsi, pendant cette phase, la charge fictive formée par les condensateurs 622, 624, 662 et 664 est couplée aux noeuds d'entrée 210, 240 et chargée sur la base des signaux d'entrée Vinp, Vinn de façon similaire aux condensateurs 602, 604, 642 et 644.
    La figure 7B illustre une phase dans laquelle le signal de phase φ2 est activé de telle sorte que les condensateurs 216 et 246 sont couplés entre les entrées et les sorties de l'amplificateur différentiel 202. En outre, les noeuds 606, 616, 626, 636, 646, 656, 666 et 676 sont couplés par l'intermédiaire des circuits de sélection correspondants (non illustrés en figure 7B) à l'une des tensions de référence sur la base du signal de données d'entrée. Par exemple : si les signaux d'entrée Vinp et Vinn sont compris entre -Vp>£F/4 et +VreF/4, les noeuds 606, 626, 646 et 666 sont couplés à +VRFF et les noeuds 616, 636, 656 et 676 sont couplés à _V^gF ; si le signal d'entrée Vinp est supérieur à +VRFF/4 et le signal d'entrée Vinn est inférieur à -V^gp/4, les noeuds 606, 616, 666 et 676 sont couplés à +Vr£F, et les noeuds 626, 636, 646 et 656 sont couplés à -VREF ; et si le signal d'entrée Vinp est inférieur à -Vjyrp/4 et le signal d'entrée Vinn est supérieur à V^p/4, les noeuds 606, 616, 666 et 676 sont couplés à -VRjrjr et les noeuds 626, 636, 646 et 656 sont couplés à +VREF·
    Sur le côté gauche et le côté droit de la figure 7B, certains exemples des tensions appliquées aux noeuds 606, 616, 626, 636, 646, 656, 666 et 676 sont illustrés dans le cas où les signaux d'entrée Vinp, Vinn sont aux mêmes niveaux VI, V2 et V3 que dans l'exemple de la figure 3B. On peut voir que, quel que soit le niveau du signal d'entrée, il y aura une demande de charge constante sur les rails de tension de référence ~VREF et +VREF et sur le rail de tension de masse. Par exemple, la demande de charge peut être calculée de la façon suivante pour les rails de tension d'alimentation GND, +VRgp et : - la demande de charge sur les rails GND est toujours nulle, puisque GND n'est pas utilisé du tout dans ce mode de réalisation ; - demande de charge sur +Vgpp :
    Cas VI : SAQ(+VREF) = -(+VREF-V1).C-(+VREF-(-
    VI)).C-(+VREF-Vl).C-(+VREF-Vl).C = -4.VREF.C
    Cas V2 : SAQ (+VREF) = -2.(+VREF-V2).C-2.(+VREF-(-V2)).C = -4.VREF.C
    Cas V3 : SAQ (+VREF) = -2. (+VREF-V3) . C-2. (+VREF- (-V3)).C = -4.VREF.C - on peut calculer de façon similaire que la demande de charge sur -Vppp est constante et égale à 4.VREF.C quel que soit le cas.
    Un avantage du mode de réalisation de la figure 6 par rapport à celui de la figure 4 est que les condensateurs fictifs 622, 624, 662 et 664 ne s'ajoutent pas à la capacité des noeuds d'entrée de l'amplificateur différentiel 202, ce qui signifie que le facteur de contre-réaction ne sera pas affecté.
    La figure 8A illustre le MDAC 111 de la figure 1 selon un exemple de variante de réalisation par rapport aux figures 4 et 6. Le circuit de la figure 8A est similaire au circuit de la figure 6, et les éléments similaires portent les mêmes références et ne seront pas décrits de nouveau en détail.
    La différence entre le mode de réalisation de la figure 8A et celui de la figure 6 est que, dans le MDAC 111 de la figure 8A, les noeuds 626 et 636 sont couplés respectivement par l'intermédiaire des commutateurs 628 et 638 au noeud de sortie Vqut- de l'amplificateur différentiel 202 plutôt qu'au noeud d'entrée 210, et les noeuds 666 et 676 sont couplés respectivement par l'intermédiaire des commutateurs 668 et 678 au noeud de sortie Vqut+ de l'amplificateur différentiel 202 plutôt qu'au noeud d'entrée 240. Les noeuds 606 et 616 sont aussi couplés au noeud de sortie VOUT- de l'amplificateur différentiel 202 par l'intermédiaire de commutateurs correspondants 802, 804 contrôlés par un signal de phase φΐ' . De façon similaire, les noeuds 646 et 656 sont aussi couplés au noeud de sortie Vqut+ de l'amplificateur différentiel 202 par l'intermédiaire de commutateurs correspondants 806, 808 contrôlés par le signal de phase φΐ' .
    En outre, dans le circuit de la figure 8A, les noeuds 626 et 636 sont par exemple couplés additionnellement au rail de tension de masse par l'intermédiaire de commutateurs 810 et 812 respectivement, et les noeuds 666 et 676 sont par exemple couplés additionnellement au rail de tension de masse par 1'intermédiaire de commutateurs 814 et 816 respectivement. Les commutateurs 810 à 816 sont par exemple contrôlés par le signal de phase Φ1, ce qui permet aux condensateurs 622, 624, 662 et 664 d'être réinitialisés à la masse pendant cette phase. Toutefois, dans une variante, les commutateurs 810 à 816 pourraient être omis.
    Les commutateurs 610, 620, 650 et 660 sont par exemple contrôlés par un signal de phase φ2' dans le mode de réalisation de la figure 8A.
    On va maintenant décrire le fonctionnement du MDAC de la figure 8A en faisant référence aux figures 8B, 9A et 9B.
    La figure 8B est un chronogramme illustrant des exemples des signaux de phase φΐ, φΐ', φ2 et φ2' dans le circuit de la figure 8A selon un exemple de réalisation.
    La figure 9Ά illustre une phase d'échantillonnage pendant laquelle le signal de phase φΐ est activé. Comme cela est représenté en figure 8B, le signal de phase φΐ est par exemple activé pendant une première période tl. Ainsi les noeuds 606, 616 et 212 sont couplés au noeud d'entrée 210, et les noeuds 646, 656 et 242 sont couplés au noeud d'entrée 240. Les noeuds 626, 636, 666 et 676 sont par exemple couplés à la masse. Ainsi, seuls les condensateurs 216, 246, 602, 604, 642 et 644 sont chargés sur la base des signaux d'entrée.
    La figure 9B illustre une deuxième phase pendant laquelle les signaux de phase φΐ et φ2 sont activés. Comme cela est représenté en figure 8B, le signal φΐ' est par exemple activé pendant une période t2, le signal φ2 est par exemple activé pendant une période t3 commençant en même temps que la période t2. Les signaux φΐ' et φ2 sont par exemple activés peu de temps après que le signal φΐ a été désactivé, de sorte qu'il n'y a pas de chevauchement entre la période tl et les périodes t2, t3. Ainsi, alors que dans le mode de réalisation de la figure 7A le pilote d'entrée chargeait les condensateurs fictifs 622, 624, 662 et 664 dans un mode de temps continu, c'est-à-dire un signal variable à haute fréquence, dans le mode de réalisation de la figure 9B l'amplificateur 202 pilote les condensateurs fictifs dans un mode à capacités commutées, c'est-à-dire que le signal s'établit. Ainsi, l'amplificateur différentiel 202 charge les condensateurs 622, 624 et 662, 664 sur la base des signaux d'entrée précédemment stockés sur les autres condensateurs, sans ajouter de charge capacitive additionnelle aux noeuds d'entrée 210, 240.
    Dans une phase finale, le signal de phase φΐ' est désactivé pendant que le signal de phase φ2 reste activé, et le signal de phase φ2' est activé, ce qui amène la même configuration que celle illustrée en figure 7B décrite précédemment, et qui ne va pas être décrite de nouveau en détail. En référence à la figure 8B, le signal de phase φ2' est par exemple activé pendant une période t4 commençant peu de temps après la fin de la période t2, de sorte qu'il n'y a pas de chevauchement entre les périodes t2 et t4. Les périodes t3 et t4 se terminent par exemple en même temps.
    Bien que les périodes tl, t2 et t4 soient représentées comme étant de durée égale en figure 8B, dans des variantes de réalisation elles pourraient avoir des durées différentes. Par exemple, les périodes tl et t2 pourraient être de durée sensiblement égale, et la période t4 égale sensiblement au double de la durée de la période tl.
    Un avantage du mode de réalisation de la figure 8A par rapport à celui de la figure 6 est que l'amplificateur d'entrée n'est pas chargé avec un signal en temps continu à haute fréquence. Un avantage du mode de réalisation de la figure 8A par rapport à celui de la figure 4 est que le facteur de contre-réaction n'est pas réduit.
    Un avantage des modes de réalisation du MDAC décrit ici est que la demande de charge à partir des niveaux de tension de référence ne dépend plus du signal. Cela signifie qu'il n'est plus nécessaire d'allouer un retard généreux entre les phases d'échantillonnage afin de permettre aux niveaux de référence de s'établir. En effet, même si les références ne sont pas complètement établies entre une phase d'échantillonnage et la suivante, puisque la demande de charge à partir de chaque référence est constante, cela va affecter chacune des références de la même façon, et ainsi ne va pas laisser de signature du signal d'entrée sur les niveaux de référence. Par exemple, chaque MDAC est par exemple capable de fonctionner à une fréquence de quelques centaines de MHz dans un ADC de 12 bits en pipeline et avec une consommation de courant de seulement quelques mA.
    Avec la description ainsi faite d'au moins un mode de réalisation illustratif, diverses altérations, modifications et améliorations apparaîtront facilement à l'homme de l'art. Par exemple, il apparaîtra clairement à l'homme de l'art que bien que des exemples particuliers aient été décrits dans lesquels le MDAC fait partie de l'étage d'un ADC en pipeline, le circuit décrit pourrait avoir d'autres applications.
    En outre, il sera clair pour l'homme de l'art que, dans le mode de réalisation de la figure 2, les commutateurs 222, 252 pourraient être omis si les commutateurs 226, 228, 230, 256, 258 et 260 sont contrôlés par le signal de phase φ2. De façon similaire, dans le mode de réalisation de la figure 4, les commutateurs 410, 420, 440, 450 pourraient être omis si les commutateurs 414, 416, 424, 426, 444, 446, 454 et 456 sont contrôlés par le signal de phase φ2. De façon similaire, dans les modes de réalisation des figures 6 et 8A, les commutateurs 610, 620, 630, 640, 650, 660, 670 et 680 pourraient être omis si les commutateurs des circuits de sélection 611, 621, 631, 641, 651, 661, 671 et 681 sont contrôlés par le signal de phase φ2 en figure 6 ou par le signal de phase φ2' en figure 8A.
    ADC IN PIPELINE WITH CONSTANT LOAD REQUEST
    Field of invention
    The present disclosure relates to the field of analog-to-digital pipeline converters (ADCs) and in particular to a pipeline ADC having a constant load demand.
    Statement of Prior Art
    An ADC (analog-to-digital converter) pipeline includes a number of pipeline conversion stages. Each stage generates one or a few output bits, typically 1.5 bits, and amplifies the signal so that the next stage operates on a sub-range of the voltage range seen by the previous stage. Each stage typically includes an analog-to-digital flash converter which generally compares the input signal with two or more threshold voltages for generating the output bits, and an MDAC (digital-to-analog multiplier converter), which converts the output generated to return them to a voltage level to be subtracted from the input voltage, the resulting residual voltage level having passed to the next stage. In particular, the MDAC generally amplifies the residue, which relaxes the noise constraints of the previous stages, leading to reduced power consumption and size. Advantageously, the MDAC maintains the residue, which means that subsequent stages see an established input.
    To implement the MDAC of each stage of a pipeline converter, it has been proposed to use a switched capacitor solution in which, during a first phase, the input voltage is sampled by capacitors while the ADC flash quantizes the input voltage, then during another phase, the residual voltage is established at its final level. In particular, the residue is generated by coupling the capacitor to one of a number of reference voltages selected on the basis of flash quantization.
    A difficulty with such an approach is that the load demand from the reference voltages depends on the signal. In other words, depending on the result of the flash quantization, a greater or lesser amount of charge will be drawn from each reference voltage rail. Thus, an appropriate time must be left between each sampling phase to allow reference voltages to return to their correct levels, since otherwise the signature left on the reference voltage rails may cause interference sampling phase and the next, thus introducing errors in the residual voltage levels generated. However, the fact of providing a suitable setup time implies a slowdown of the bit rate of the converter. summary
    An object of embodiments of the present disclosure is to at least partially solve one or more difficulties of the prior art.
    According to one embodiment, there is provided a digital-to-analog multiplier converter (MDAC) comprising: first and second inputs for receiving first and second differential input signals; a differential amplifier having first and second differential input nodes and first and second differential output nodes; a first capacitor having one of its nodes coupled to the first differential input node and its other node coupled to the first input via a first switch and at least one reference power supply node by via one or more other switches; and second and third capacitors, each having one of its nodes coupled to either the first differential input node, the first differential output node, or the first input.
    According to one embodiment, the other node of the first capacitor is coupled to a first reference supply voltage node through a first other switch; the second capacitor has one of its nodes coupled to the first differential input node and its other node coupled to second and third reference supply voltage nodes via a first selection circuit; and the third capacitor has one of its nodes coupled to the first differential input node and its other node coupled to the second and third reference supply voltage nodes through a second selection circuit.
    According to one embodiment, the MDAC further comprises a control circuit adapted to control, during a second phase: the first other switch for coupling the first capacitor to the first reference voltage; the first selection circuit for coupling the second capacitor to one of the second and third reference supply voltage nodes selected on the basis of a digital conversion of the first and second differential input signals; and the second selection circuit for coupling the second capacitor to one of the second and third reference supply voltage nodes selected based on the digital conversion.
    According to one embodiment, the MDAC further comprises: a fourth capacitor having one of its nodes coupled to the second differential input node and its other node coupled to the second input via a first switch and to the first reference voltage via a second other switch; and fifth and sixth capacitors, wherein: the fifth capacitor has one of its nodes coupled to the second differential input node and its other node coupled to the second and third reference voltages through a third circuit of selection; and the sixth capacitor has one of its nodes coupled to the second differential input node and its other node coupled to the second and third reference voltages through a fourth selection circuit.
    According to one embodiment, the second capacitor has one of its nodes coupled to the first reference supply voltage node, and its other node is coupled to either the first input or the first differential output node; and the third capacitor has one of its nodes coupled to the first reference supply voltage node and its other node coupled to either the first input or the first differential output node.
    According to one embodiment, the first capacitor has its other node coupled to at least one reference supply voltage rail via a fifth selection circuit, the MDAC further comprising: a seventh capacitor having one of its nodes coupled to the first differential input node and its other node coupled to the first input via a second switch and to at least one reference supply voltage node via a sixth selection circuit.
    According to one embodiment, the second capacitor has one of its nodes coupled to the first reference voltage rail, and its other node coupled to the first input via a third switch and to second and third nodes. reference supply voltage via a seventh selection circuit; and the third capacitor has one of its nodes coupled to the first reference supply voltage node, and its other node coupled to the first input via a fourth switch and the second and third voltage nodes of the first reference power supply via an eighth selection circuit.
    According to one embodiment, the MDAC further comprises a control circuit adapted to: control, during a first phase, the first, second, third and fourth switches for coupling the first, second, third and seventh capacitors to the first input; and controlling, during a second phase, the fifth, sixth, seventh, and eighth selection circuits for coupling each of the first, second, third, and seventh capacitors to one of the first, second, and third reference supply voltage nodes on the basis of a digital conversion of the first and second differential input signals.
    According to one embodiment, the MDAC further comprises an eighth capacitor having one of its nodes coupled to the second differential input node and its other node coupled to the second input via a fifth switch and to the second minus one reference supply voltage node through one or more other switches; a ninth capacitor having one of its nodes coupled to the second differential input node and its other node coupled to the second input via a sixth switch and at least one reference supply voltage node per via one or more other switches; a tenth capacitor having one of its nodes coupled to the first reference supply voltage node, and its other node coupled to the second input via a seventh switch and the second and third voltage nodes of reference power supply via a ninth selection circuit; and an eleventh capacitor having one of its nodes coupled to the first reference supply voltage node, and its other node coupled to the second input via an eighth switch and the second and third voltage nodes. reference power supply via a tenth selection circuit.
    According to one embodiment, the second capacitor has one of its nodes coupled to a first reference supply voltage node, and its other node coupled to the first differential output node and second and third voltage nodes. reference power supply via a seventh selection circuit; and the third capacitor has one of its nodes coupled to the first reference supply voltage node, and its other node coupled to the first differential output node and the second and third reference supply voltage nodes by the intermediate of an eighth selection circuit.
    According to one embodiment, the MDAC further comprises a control circuit further adapted to: control, during an initial phase, said one or more other switches for coupling the first and seventh capacitors to the first input and the sixth and seventh circuits selecting means for coupling the second and third capacitors to the first reference voltage.
    According to one embodiment, the MDAC further comprises an eighth capacitor having one of its nodes coupled to the second differential input node and its other node coupled to the second input via a fifth switch and to the second minus one reference supply voltage node via one or more other switches; a ninth capacitor having one of its nodes coupled to the second differential input node and its other node coupled to the second input via a sixth switch and at least one reference supply voltage node per via one or more other switches; a tenth capacitor having one of its nodes coupled to the first reference supply voltage node, and its other node coupled to the second differential output node via a seventh switch and the second and third voltage nodes. reference power supply via a ninth selection circuit; and an eleventh capacitor having one of its nodes coupled to the first reference supply voltage node, and its other node coupled to the second differential output node via an eighth switch and the second and third nodes of reference supply voltage via a tenth selection circuit.
    According to one embodiment, the first, second, third and seventh capacitors each have half the capacity of a twelfth capacitor coupled between the input and differential output nodes of the differential amplifier.
    In another aspect, there is provided a pipeline analog-to-digital converter comprising a plurality of pipeline-coupled conversion stages, each conversion stage including the aforementioned MDAC, and an analog-to-digital converter of r bits adapted to generate r bits on the base of the output signals of a last stage of the plurality of conversion stages.
    Brief description of the drawings
    The foregoing and other features and advantages will become apparent upon reading the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings in which: FIG. 1 schematically illustrates a pipeline ADC according to an exemplary embodiment; FIG. 2 schematically illustrates a digital-analog multiplier converter (MDAC) of a conversion stage of FIG. 1 in more detail according to an example embodiment; FIGS. 3 and 3B represent operating phases of the MDAC of FIG. 2 according to an example embodiment; Figure 4 schematically illustrates an MDAC of the pipeline ADC of Figure 1 in more detail according to an exemplary embodiment of the present disclosure; FIG. 5 represents an operating phase of the MDAC of FIG. 2 according to an exemplary embodiment; Fig. 6 schematically illustrates an MDAC of the pipeline ADC of Fig. 1 in more detail according to another embodiment of the present disclosure; FIGS. 7A and 7B show phases of operation of the MDAC of FIG. 6 according to an example embodiment of the present description; Figure 8A schematically illustrates an MDAC of the pipeline ADC of Figure 1 in more detail according to yet another embodiment of the present disclosure; Fig. 8B is a timing diagram illustrating examples of control signals in the circuit of Fig. 8A according to an exemplary embodiment; and FIGS. 9A and 9B show operating phases of the MDAC of FIG. 8A according to yet another embodiment of the present description.
    detailed description
    In the present description, the term "connected" is used to denote a direct electrical connection between one element and another, while the term "coupled" is used to designate an electrical connection which may be direct, or may be intermediate of one or more other components such as resistors, capacitors, or switches. The term "substantially" is used to mean a tolerance of plus or minus 10% with respect to the value in question.
    FIG. 1 schematically illustrates an N-bit pipeline ADC 100 according to an exemplary embodiment. The pipelined ADC 100 comprises, for example, an n-bit ADC (nBIT ADC) 102), and Nn series-coupled pipeline conversion stages (STAGE 1, STAGE 2, STAGE Nn) 104 and generating the input signal of the ADC of n bits 102.
    A first of the conversion stages 104 receives for example an analog input signal IN to be converted, and a reference voltage and generates one or more output bits and an output analog signal to serve as an input signal IN of the next floor. Each subsequent stage 104 includes a similar circuit. A clock driver (CLK DRIVER) 105 receives for example a clock signal CLK, and generates time signals for controlling the stages of the pipeline ADC and also for controlling an error correction and output register 106 The register 106 receives, for example, the output bit (s) generated by each of the conversion stages 104 and the ADC 102 of the pipeline ADC 100, and generates, on the basis of these bits, the digital output signal. of N bits OUT (N: 1) of the converter.
    In one embodiment, each conversion stage has a 1.5 bit flash ADC, and thus provides 1.5 bits of output data to the error correction and output register 106. After the error correction, the Nn stages of the pipeline generate, for example, Nn bits of output data. Thus, in an example of a 12-bit converter, there are for example 11 stages 104, and a final ADC 102 of 1 bit. An exemplary implementation of the first of the conversion stages 104 is illustrated in FIG. 1. The other conversion stages comprise, for example, similar circuits.
    The input line receiving the input signal IN is referenced 108 and is coupled to a flash ADC 110, which for example compares the input signal with first and second thresholds equal to + Vreit / 4 and -Vref / 4 to generate an output signal of 1.5 bit D (2: 1). The input line 108 is also for example coupled to an MDAC 111, which also receives the output bits from the flash ADC 110, and generates an output signal OUT forming the input signal of the next stage. The MDAC 111 comprises for example a sample-and-hold circuit (S / H) 112, which samples the input signal, and supplies the result to an adder 114. The adder 114 subtracts from this signal a residual value generated by a DAC of 1.5 bit 116 based on the output bits generated by the flash ADC 110. The output of the adder 114 is amplified by an amplifier 118, for example having a gain of 2, to generate the signal. OUT output.
    The operation of the floor is for example the following. It is assumed that the input signal IN of the stage is a differential input signal having Vinp and Vinn components. Each of the stages 104 compares the input signal with voltage thresholds equal to + V ^ gp / 4 and "Vreit / 4. The 1.5-bit flash ADC of each stage will compare the input voltages to these threshold voltages.
    As illustrated on the left-hand side of FIG. 1, if the Vinp and Vinn signals are between these threshold voltages, it will be assumed that the input signal must be in a central portion 120 between Vr £ 1/2 and "Vrejt / 2, and thus a gain of 2 is applied to this portion of the input signal, and the result is provided to the next stage. For this, the analog output voltages are for example equal to 2Vinp and 2Vinn respectively.
    Otherwise, if the flash ADC finds that Vinp is greater than VREF / 4 and Vinn is less than -VREF / 4, it will be assumed that the input signal is in an upper portion 122 between 0 V and + Vjy P , and thus a gain of 2 is applied to this input signal portion, and the result is supplied to the next stage. For this, the analog output voltages are for example equal to 2Vinp-VREp and 2Vinn + Vj ^ gp respectively.
    Otherwise, if the flash ADC finds that Vinp is less than -VREF / 4 and Vinn is greater than Vrejt / 4, it will be assumed that the input signal must be in a lower portion 124 between -Vrejt and 0V, and thus a gain of 2 is applied to this portion of the input signal, and the result is provided to the next stage. For this, the analog output voltages are for example equal to 2Vinnp + VREp and 2Vinnn-Vj ^ rp respectively.
    An advantage of implementing pipeline stages in this manner is that it provides a high tolerance for incorrect quantization by the flash ADC, and thus the flash ADC can have a relatively low accuracy.
    Although in the example of FIG. 1, the flash ADC 110 is coupled directly to the input line receiving the analog input signal IN, in alternative embodiments it could be coupled to the output of the sample-and-hold circuit 112. Such an implementation is for example described in more detail in the publication of I. Ahmed et al. entitled "A High Bandwidth Power Scalable Sub-Sampling 10-bit Pipelined ADC With Embedded Sample and Hold," IEEE Journal of Solid-state Circuits, Vol. 43, No.7, July 2008, the content of which is considered to be included here within the limits permitted by law. An exemplary implementation of the MDAC 111 of Figure 1 modified based on such an approach will now be described with reference to Figure 2.
    FIG. 2 diagrammatically illustrates the MDAC 111 of the converter stage of FIG. 1 in more detail according to an exemplary embodiment in which the input and output signals IN, OUT are differential signals. The MDAC 111 comprises for example a differential amplifier 202 having differential inputs and outputs. The positive input of the differential amplifier 202 is coupled to a node 204. A capacitor 205 is coupled between the node 204 and another node 206. The node 206 is coupled via a switch 208 to a node 202. input 210 of the MDAC 111 for receiving a component Vinp of the differential input signal IN. The input node 210 is also coupled to another node 212 via a switch 214. Another capacitor 216 is coupled between the nodes 212 and 204. The node 212 is further coupled to the negative output of the second node 212. differential amplifier 202 via a switch 218. The node 206 is for example coupled to a node 220 via a switch 222. The node 220 is coupled to three reference levels -Vggp, mass and + Vggp via a selection circuit 224, which selects one of the reference voltages on the basis of the 1.5-bit signal generated by the ADC 110 of FIG. 1. For example, the circuit of FIG. selection 224 comprises a switch 226 coupled between the node 220 and the ground, a switch 228 coupled between the node 220 and the reference voltage rail + Vppp and a switch 230 coupled between the node 220 and the reference voltage rail - Vref ·
    The positive and negative outputs of the differential amplifier 202 are for example coupled together via another switch 232. The negative input of the differential amplifier 202 is coupled to a node 234. A capacitor 235 is coupled between the node 234 and another node 236. The node 236 is coupled through a switch 238 to an input node 240 of the MDAC 111 to receive a component Vinn of the differential input signal IN. The input node 240 is also coupled to another node 242 through a switch 244. Another capacitor 246 and coupled between the nodes 242 and 234. The node 242 is further coupled to the positive output of 1 differential amplifier 202 via a switch 248. The node 236 is for example coupled to a node 250 via a switch 252. The node 250 is coupled to the three levels of reference -V ^ pp, and + VRpp through a selection circuit 254, which selects one of the reference voltages based on the 1.5-bit signal generated by the ADC 110 of FIG. 1. For example, the selection circuit 254 comprises a switch 256 coupled between the node 250 and the ground, a switch 258 coupled between the node 250 and the reference voltage rail + Vppp and a switch 260 coupled between the node 250 and the reference voltage rail -Vppp.
    The differential input nodes 204, 234 of the amplifier 202 are for example coupled together by a switch 262. In addition, the positive input node 204 is for example coupled to a reference supply voltage node Vj by means of a switch 264, and the negative input node 234 is for example coupled to the reference supply voltage node Vj- through a switch 266. The voltage Vj- is, for example, at the mass level, although it may be at another level.
    The capacitors 205, 235, 216 and 246 for example have capacitors C which are substantially equal.
    The switches 208, 238, 214, 244, 232, 262, 264 and 266 are for example controlled by a phase signal φΐ, although in some embodiments the switches 262, 264 and 266 can be made non-conductive just before the Switches 208 and 238. Switches 218, 248, 232 and 252 are for example controlled by a phase signal φ2.
    The selection circuits 224, 254 are, for example, controlled by the flash ADC 110, which for example has its inputs coupled to the differential amplifier outputs 202 and 204.
    The operation of the circuit of Fig. 2 will now be described in more detail with reference to Figs. 3A and 3B.
    FIG. 3A shows the connection of the MDAC 111 of FIG. 2 during a phase in which the signal φΐ is activated but not the signal φ2. Thus, the positive input of the differential amplifier 202 is coupled to the input node 210 through the parallel connection of the capacitors 205 and 216. Similarly, the negative input of the differential amplifier 202 is coupled to the input node 240 through the parallel connection of the capacitors 235 and 246. The inputs of the differential amplifier are also for example coupled to the reference supply voltage node V ^. The outputs of the differential amplifier 202 are coupled together, thereby resetting the output of the differential amplifier 202 to the common mode level.
    FIG. 3B shows the connection of the MDAC 111 of FIG. 2 during a phase in which the signal φ2 is activated but not the signal φΐ. Thus, the outputs of the differential amplifier 202 are coupled via the capacitors 216 and 246 to the respective inputs of the differential amplifier 202. In addition, the capacitors 205 and 235 are coupled via the control circuits. selecting 224, 254 (not shown in FIG. 3B) at one of the selected reference voltages based on the level of the input signal. For example: if the input signals Vinp and Vinn are between -VREf / 4 and + VREE / 4, the capacitors 205 and 235 are coupled to the ground voltage; if the input signal Vinp is greater than + vref / 4 and the input signal Vinn is less than ~ VREE / 4, the capacitor 205 is coupled to and the capacitor 235 is coupled to -Vref; and if the input signal Vinp is less than -VREE / 4 and the input signal Vinn is greater than VREE / 4, the capacitor 205 is coupled to -Vj ^ pp and the capacitor 235 is coupled to + VREp.
    On the left side and the right side of FIG. 3B are illustrated respectively examples of the connections of the nodes 206 and 236.
    According to a first example, as illustrated by curves in solid lines 302 and 304, the input signal Vinp is at a level VI between 0 and VREp / 4 and the node 206 is thus coupled to ground, and the signal Vinn input is at a level -VI between 0 and -Vj ^ pp / 4 and the node 236 is thus also coupled to ground. In this example, the MDAC generates the 2Vinp and 2Vinn signals on its output nodes. The load demand on the power supply rails and on the supply rails + VREF '-VREF is for example zero in this case.
    In another example, as illustrated by dashed lines 306 and 308, the input signal Vinp is at a level V2 between VREp / 4 and VREp, and the node 206 is thus coupled to VREp, and the signal Vinn input is at a -V2 level between -VREp / 4 and -VREp, and the node 236 is thus coupled to -VREp. In this example, the MDAC generates the signals 2Vinp-VREE and 2Vinn + VREE, and so there will be a positive charge request on the supply voltage + VREE rail based on the signal
    Vinp and a negative charge demand on the supply voltage rail -νρρρ on the basis of the Vinn signal.
    According to yet another example, as illustrated by dotted curves 310 and 312, the input signal Vinp is at a level -V3 between -VRpp / 4 and -ν ^ ρρ, and the node 206 is thus coupled to -Vppp, and the input signal Vinn is at a level V3 between VRpp / 4 and VRpp, and the node 236 is thus coupled to + Vp> pp. In this example, the MDAC generates the signals 2Vinp + Vppp and 2Vinn-Vref, and so there will be a positive charge request on the + Vppp supply voltage rail based on the Vinn signal and a negative charge demand on the supply voltage rail -V ^ pp based on the Vinp signal.
    Thus, it can be seen that in such a circuit, the load demand on the reference voltage rails + Vppp and -Vrpf depends on the level of the input signal, which leads to the drawbacks previously described in the prior art section. . For example, the load demand that depends on the input can be calculated as follows for the three voltage cases of Figure 3B:
    - case VI: thus: - case V2: - case V3:
    FIG. 4 schematically illustrates a circuit implementing the MDAC 111 of FIG. 1 in more detail according to an alternative embodiment with respect to FIG. 2.
    In FIG. 4, the elements which are the same as those of the circuit of FIG. 2 bear the same references and will not be described again in detail.
    In the embodiment of FIG. 4, the circuitry coupled to the positive input node 204 of the differential amplifier 202 is modified in the following manner with respect to the circuit of FIG. 2.
    The selection circuit 224 is replaced by a switch 402, coupling the node 206 to ground. In addition, two additional capacitors 406, 408 are for example provided, each having one of its nodes coupled to the positive input node 204 of the differential amplifier 202. The capacitors 406, 408, for example, each have a capacitance equal to substantially half of capacitor C of capacitor 205.
    The capacitor 406 has its other node coupled via a switch 410 to a selection circuit 412. The selection circuit 412 allows for example to select one of the reference voltages + Vrejt and -Vjyrjr and to couple it. to the capacitor 406, the selection being based on the 1.5-bit output signal from the flash ADC. For example, the selection circuit 412 comprises a switch 414 coupled between the switch 410 and the reference voltage rail -VREp and a switch 416 coupled between the switch 410 and the reference voltage rail + Vp> p. Another switch 418 is for example coupled between the capacitor 406 and the ground voltage rail.
    Similarly, the capacitor 408 has its other node coupled via a switch 420 to a selection circuit 422. The selection circuit 422 makes it possible, for example, to select one of the reference voltages + VREp and and coupling it to the capacitor 408, the selection being based on the 1.5 bit output signal from the flash ADC. For example, the selection circuit 422 includes a switch 424 coupled between the switch 420 and the reference voltage rail -Vref and a switch 426 coupled between the switch 420 and the reference voltage rail + Vppp. Another switch 428 is for example coupled between the capacitor 408 and the ground voltage rail.
    Similarly, the circuitry coupled to the negative input node 234 of the differential amplifier 202 is modified in the following manner with respect to the circuit of FIG.
    The selection circuit 254 is replaced by a switch 432, coupling the node 236 to ground. In addition, two additional capacitors 436, 438 are for example provided, each having one of its nodes coupled to the negative input node 234 of the differential amplifier 202. Each of the capacitors 436, 438, for example, has a capacitance equal to substantially half of capacitor C of capacitor 235.
    The capacitor 436 has its other node coupled via a switch 440 to a selection circuit 442. The selection circuit 442 makes it possible for example to select one of the reference voltages + Vppp and "Vppp and to couple it. to the capacitor 436, the selection being based on the 1.5-bit output signal from the flash ADC. For example, the selection circuit 442 includes a switch 444 coupled between the switch 440 and the reference voltage rail -Vppp and a switch 446 coupled between the switch 440 and the reference voltage rail + Vppp. Another switch 448 is for example coupled between the capacitor 436 and the ground voltage rail.
    Similarly, the capacitor 438 has its other node coupled through a switch 450 to a selection circuit 452. The selection circuit 452 allows for example to select one of the reference voltages + Vppp and -Vppp and coupling it to the capacitor 438, the selection being based on the 1.5-bit output signal from the flash ADC. For example, the selection circuit 452 comprises a switch 454 coupled between the switch 450 and the reference voltage -Vppp and a switch 456 coupled between the switch 450 and the reference voltage + Vp £ p. Another switch 458 is for example coupled between the capacitor 438 and the ground voltage rail.
    The switches 402, 410, 420, 432, 440 and 450 are for example controlled by the phase signal φ2. The switches 418, 428, 448 and 458 are for example controlled by the phase signal φΐ. The phase signals φΐ and φ2 are for example generated by a control circuit 458 on the basis of a clock signal CLK.
    In operation, during a first phase, the MDAC of FIG. 4 is for example adapted to couple the input voltages Vinp, Vinn, to the capacitors 205, 216, 235 and 246, in a manner similar to what has been represented in FIG. 3A described above. During this phase, the capacitors 406, 408, 436 and 438 are, for example, coupled to ground via the switches 418, 428, 448 and 458 respectively. A second phase is illustrated in Figure 5.
    FIG. 5 represents an operating phase of the MDAC of FIG. 4 in which the capacitors of 216, 246 are coupled in feedback paths between the output / input nodes of the differential amplifier 202, the capacitors 205, 235 are coupled through the switches 402, 432 to ground, and each of the capacitors 406, 408, 436, 438 is coupled to one of the reference voltage rails based on the result of the flash ADC conversion.
    On the left and right sides of FIG. 5, some examples of the input voltages Vinp and Vinn are illustrated at the same levels VI, V2 and V3 as in the example of FIG. 3B. As represented by curves in solid line, in the case where the input voltage Vinp is at a level VI between -VrjtF / 4 and + Vppp / 4, the capacitors 406 and 436 are for example coupled to the rail. supply + Vreit and the capacitors 408, 438 are for example coupled to the supply rail -V ^ p; as represented by dashed lines, if the input signal Vinp is at a level V2 greater than + Vj ^ pp / 4 and the input signal Vinn is at ion level -V2 less than -Vppp / 4 , the two capacitors 406, 408 are for example coupled to the supply rail + VREF, and the two capacitors 436, 438 are for example coupled to a supply rail; and as shown by dotted curves, if the input signal Vinp is at a level -V3 less than -Vj ^ pp / 4 and the input signal Vinn is at a level V3 greater than V ^ pp / 4, the two capacitors 406, 408 are for example coupled to the supply rail and the two capacitors 436, 438 are for example coupled to the supply rail + VREF.
    An advantage of the MDAC embodiment of FIG. 4 is that the load demand on the reference voltage rails -Vppp and + Vppp and on the ground voltage rail is constant regardless of the levels of the input signals. Vinp, Vinn. For example, the load demand can be calculated as follows for the GND, + Vppp and -VREF supply voltage rails: - the load demand on the GND rail is always zero: SAQ (left and right GND) = - (0-V) .C- (0 - (- V)); C = O; - load request on + VREF: SAQ (+ VREF left and right) = -2 (+ VREF-0); - load request on -VREF: SAQ (-VREF left and right) = -2 (-VREF-0).
    FIG. 6 illustrates the MDAC 111 of FIG. 1 according to an exemplary variant embodiment with respect to FIG. 4. The circuit of FIG. 6 is similar to the circuit of FIG. 2, and the similar elements bear the same references and do not will not be described again in detail.
    In the embodiment of FIG. 6, the capacitor 205 is replaced by two capacitors 602 and 604 each having a capacitance C / 2, in other words a capacitance substantially equal to half the capacitor C of the capacitor 216. The capacitor 602 is coupled between node 204 and node 606, which in turn is coupled to input node 210 through a switch 608 controlled by the phase signal φΐ. The node 606 is also coupled via a switch 610 to a selection circuit 611, which is for example similar to the selection circuit 412 of FIG. 4. The capacitor 604 is coupled between the node 204 and a node 616. which in turn is coupled to the input node 210 via a switch 618 controlled by the phase signal φΐ. The node 616 is also coupled via a switch 620 to a selection circuit 621, which is also similar to the selection circuit 412 of FIG. 4. The switches 610 and 620 are for example controlled by the phase signal φ2.
    The circuit of Figure 6 further comprises a dummy load on the input node 210 formed by another pair of capacitors 622, 624, as will now be described. The capacitor 622 has a capacity substantially equal to C / 2 and is for example coupled between ground and a node 626. The node 626 is for example coupled to the input node 210 via a switch 628, and by through a switch 630 to a selection circuit 631, which is similar to the selection circuit 412 or 442 of Figure 4. The capacitor 624 has a capacitance substantially equal to C / 2 and is for example coupled between the mass and a node 636. The node 636 is for example coupled to the input node 210 via a switch 638, and via a switch 640 to a selection circuit 641, which is similar to the circuit 412 or 422 of Figure 4. The switches 628 and 638 are for example controlled by the phase signal φΐ and the switches 630 and 640 are for example controlled by the phase signal φ2.
    Similarly, the capacitor 235 is replaced by two capacitors 642 and 644 each having a capacitance C / 2, in other words a capacitance substantially equal to half the capacitance C of the capacitor 246. The capacitor 642 is coupled between the capacitor node 234 and a node 646, which is in turn coupled to the input node 240 through a switch 648 controlled by the phase signal φΐ. The node 646 is also coupled through a switch 650 to a selection circuit 651, which is for example similar to the selection circuit 412 of FIG. 4. The capacitor 644 is coupled between the node 234 and a node 656. which in turn is coupled to the input node 240 through a switch 658 controlled by the phase signal φΐ The node 656 is also coupled through a switch 660 to a selection circuit 661 , which is also for example similar to the selection circuit 412 of FIG. 4. The switches 650 and 660 are for example controlled by the phase signal φ2.
    The circuit of Figure 6 further comprises a dummy load on the input node 240 formed by two other capacitors 662 and 664, as will now be described. The capacitor 662 has a capacity substantially equal to C / 2 and is for example coupled between ground and a node 666. The node 666 is for example coupled to the input node 240 via a switch 668, and by through a switch 670 to a selection circuit 671, which is similar to the selection circuit 412 or 442 of Figure 4. The capacitor 664 has a capacitance substantially equal to C / 2 and is for example coupled between the mass and a node 676. The node 676 is for example coupled to the input node 240 via a switch 678, and via a switch 680 to a selection circuit 681, which is similar to the circuit 412 or 442 of Figure 4. The switches 668 and 678 are for example controlled by the phase signal φΐ and the switches 670 and 680 are for example controlled by the phase signal φ2. The phase signals φΐ and φ2 are for example generated by a control circuit 684 on the basis of a clock signal CLK.
    The operation of the circuit of FIG. 6 will now be described in more detail with reference to FIGS. 7A and 7B.
    FIG. 7A illustrates a first phase in which the phase signal φΐ is activated so that the capacitors 216, 602 and 604 are coupled in parallel between the positive input of the differential amplifier 202 and the input node 210. Similarly, the capacitors 246, 642 and 644 are coupled between the negative input of the differential amplifier 202 and the input node 240. In addition, the capacitors 622 and 624 are coupled in parallel between the ground and the node. input 210, and the capacitors 662 and 664 are coupled in parallel between the ground and the input node 240. Thus, during this phase, the dummy load formed by the capacitors 622, 624, 662 and 664 is coupled to the nodes. input 210, 240 and loaded on the basis of the input signals Vinp, Vinn similarly to the capacitors 602, 604, 642 and 644.
    FIG. 7B illustrates a phase in which the phase signal φ2 is activated so that the capacitors 216 and 246 are coupled between the inputs and the outputs of the differential amplifier 202. In addition, the nodes 606, 616, 626, 636, 646, 656, 666 and 676 are coupled via the corresponding selection circuits (not shown in FIG. 7B) to one of the reference voltages on the basis of the input data signal. For example: if the input signals Vinp and Vinn are between -Vp> £ F / 4 and + VreF / 4, the nodes 606, 626, 646 and 666 are coupled to + VRFF and the nodes 616, 636, 656 and 676 are coupled to V gF; if the input signal Vinp is greater than + VRFF / 4 and the input signal Vinn is less than -V ^ gp / 4, the nodes 606, 616, 666 and 676 are coupled to + Vr £ F, and the nodes 626, 636, 646 and 656 are coupled to -VREF; and if the input signal Vinp is less than -Vjyrp / 4 and the input signal Vinn is greater than V ^ p / 4, the nodes 606, 616, 666 and 676 are coupled to -VRjrjr and the nodes 626, 636, 646 and 656 are coupled to + VREF ·
    On the left and right sides of FIG. 7B, some examples of the voltages applied to the nodes 606, 616, 626, 636, 646, 656, 666 and 676 are illustrated in the case where the Vinp, Vinn input signals are at the same levels VI, V2 and V3 as in the example of Figure 3B. It can be seen that regardless of the level of the input signal, there will be a constant load demand on the reference voltage rails ~ VREF and + VREF and on the ground voltage rail. For example, the load demand can be calculated as follows for the GND supply voltage rails, + VRgp and: - the load demand on the GND rails is always zero, since GND is not used at all in this embodiment; - load request on + Vgpp:
    Case VI: SAQ (+ VREF) = - (+ VREF-V1) .C - (+ VREF - (-
    VI)) C - (+ VREF-VI) .C - (+ VREF-VI) .C = -4.VREF.C
    Case V2: SAQ (+ VREF) = -2 (+ VREF-V2) .C-2 (+ VREF - (- V2)) C = -4.VREF.C
    Case V3: SAQ (+ VREF) = -2. (+ VREF-V3). C-2. (+ VREF- (-V3)) C = -4.VREF.C - we can similarly calculate that the load demand on -Vppp is constant and equal to 4.VREF.C whatever the case.
    An advantage of the embodiment of FIG. 6 with respect to that of FIG. 4 is that the dummy capacitors 622, 624, 662 and 664 do not add to the capacity of the input nodes of the differential amplifier 202, which means that the feedback factor will not be affected.
    FIG. 8A illustrates the MDAC 111 of FIG. 1 according to an exemplary variant embodiment with respect to FIGS. 4 and 6. The circuit of FIG. 8A is similar to the circuit of FIG. 6, and the similar elements bear the same references and FIG. will not be described again in detail.
    The difference between the embodiment of Fig. 8A and that of Fig. 6 is that in MDAC 111 of Fig. 8A, the nodes 626 and 636 are coupled respectively via switches 628 and 638 to the output node. V4- of the differential amplifier 202 rather than the input node 210, and the nodes 666 and 676 are respectively coupled via the switches 668 and 678 to the output node VQT + of the differential amplifier 202 rather than at the input node 240. The nodes 606 and 616 are also coupled to the output node VOUT- of the differential amplifier 202 through corresponding switches 802, 804 controlled by a phase signal φΐ '. Similarly, the nodes 646 and 656 are also coupled to the Vqut + output node of the differential amplifier 202 via corresponding switches 806, 808 controlled by the phase signal φΐ '.
    In addition, in the circuit of FIG. 8A, the nodes 626 and 636 are for example additionally coupled to the ground voltage rail via switches 810 and 812 respectively, and the nodes 666 and 676 are for example coupled in addition to the mass voltage rail through switches 814 and 816 respectively. The switches 810 to 816 are for example controlled by the phase signal Φ1, which allows the capacitors 622, 624, 662 and 664 to be reset to ground during this phase. However, in one variant, switches 810 to 816 could be omitted.
    The switches 610, 620, 650 and 660 are for example controlled by a phase signal φ2 'in the embodiment of FIG. 8A.
    The operation of the MDAC of Fig. 8A will now be described with reference to Figs. 8B, 9A and 9B.
    FIG. 8B is a timing diagram illustrating examples of the phase signals φΐ, φΐ ', φ2 and φ2' in the circuit of FIG. 8A according to an exemplary embodiment.
    Figure 9Ά illustrates a sampling phase during which the phase signal φΐ is activated. As shown in FIG. 8B, the phase signal φΐ is for example activated during a first period t1. Thus the nodes 606, 616 and 212 are coupled to the input node 210, and the nodes 646, 656 and 242 are coupled to the input node 240. The nodes 626, 636, 666 and 676 are for example coupled to ground . Thus, only the capacitors 216, 246, 602, 604, 642 and 644 are loaded based on the input signals.
    FIG. 9B illustrates a second phase during which the phase signals φΐ and φ2 are activated. As shown in FIG. 8B, the signal φΐ 'is for example activated during a period t2, the signal φ2 is for example activated during a period t3 beginning at the same time as the period t2. The signals φΐ 'and φ2 are for example activated shortly after the signal φΐ has been deactivated, so that there is no overlap between the period t1 and the periods t2, t3. Thus, while in the embodiment of FIG. 7A the input driver was loading the dummy capacitors 622, 624, 662 and 664 in a continuous time mode, i.e. a high frequency variable signal, in the embodiment of FIG. 9B, the amplifier 202 drives the fictitious capacitors in a switched capacitor mode, i.e. the signal is established. Thus, the differential amplifier 202 charges the capacitors 622, 624 and 662, 664 based on the input signals previously stored on the other capacitors, without adding additional capacitive load to the input nodes 210, 240.
    In a final phase, the phase signal φΐ 'is deactivated while the phase signal φ2 remains on, and the phase signal φ2' is activated, which leads to the same configuration as that illustrated in FIG. 7B described previously, and which will not be described again in detail. With reference to FIG. 8B, the phase signal φ2 'is for example activated during a period t4 beginning shortly after the end of the period t2, so that there is no overlap between the periods t2 and t4. The periods t3 and t4 end for example at the same time.
    Although the periods t1, t2 and t4 are represented as being of equal duration in FIG. 8B, in alternative embodiments they could have different durations. For example, the periods t1 and t2 could be of substantially equal duration, and the period t4 is substantially twice the duration of the period t1.
    An advantage of the embodiment of Figure 8A with respect to that of Figure 6 is that the input amplifier is not loaded with a high frequency continuous time signal. An advantage of the embodiment of FIG. 8A with respect to that of FIG. 4 is that the feedback factor is not reduced.
    An advantage of the embodiments of the MDAC described herein is that the charge demand from the reference voltage levels no longer depends on the signal. This means that it is no longer necessary to allocate a generous delay between the sampling phases in order to allow reference levels to be established. Indeed, even if the references are not completely established between one sampling phase and the next, since the load demand from each reference is constant, this will affect each of the references in the same way, and so will not leave no signature of the input signal on the reference levels. For example, each MDAC is for example capable of operating at a frequency of a few hundred MHz in a 12-bit ADC pipeline and with a current consumption of only a few mA.
    With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example, it will be apparent to those skilled in the art that although particular examples have been described in which the MDAC is part of the stage of a pipeline ADC, the described circuit could have other applications.
    Furthermore, it will be clear to those skilled in the art that, in the embodiment of FIG. 2, the switches 222, 252 could be omitted if the switches 226, 228, 230, 256, 258 and 260 are controlled. by the phase signal φ2. Similarly, in the embodiment of Figure 4, the switches 410, 420, 440, 450 could be omitted if the switches 414, 416, 424, 426, 444, 446, 454 and 456 are controlled by the signal. phase φ2. Similarly, in the embodiments of FIGS. 6 and 8A, the switches 610, 620, 630, 640, 650, 660, 670 and 680 could be omitted if the switches of the selection circuits 611, 621, 631, 641, 651, 661, 671 and 681 are controlled by the phase signal φ2 in FIG. 6 or by the phase signal φ2 'in FIG. 8A.
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    A digital-to-analog multiplier converter (MDAC) comprising: first and second inputs (210, 240) for receiving first and second differential input signals (Vinp, Vinn); a differential amplifier (202) having first and second differential input nodes (204, 234) and first and second differential output nodes (VQT + 'vOUT') a first capacitor (205, 602) having one of its nodes coupled to the first differential input node (204) and its other node coupled to the first input (210) through a first switch (208, 608) and at least one supply voltage node reference (+ Vrejt, 0, -Vp ^ p) through one or more other switches (402, 610); and second and third capacitors (406, 408, 622, 624) each having one of its nodes coupled to either: - the first differential input node (204); either - at the first differential output node (Vqut-) * or - at the first input (210).
    [2" id="c-fr-0002]
    The MDAC according to claim 1, wherein: the other node of the first capacitor (205) is coupled to a first reference supply voltage node (GND) through a first other switch (402) ; the second capacitor (406) has one of its nodes coupled to the first differential input node (204) and its other node coupled to second and third reference supply voltage nodes (+ Vppp, -Vref) by via a first selection circuit (412); and the third capacitor (408) has one of its nodes coupled to the first differential input node (204) and its other node coupled to the second and third reference supply voltage nodes (Vj ^ p, -Vppp) via a second selection circuit (422).
    [3" id="c-fr-0003]
    3. MDAC according to claim 2, further comprising a control circuit (458) adapted to control, during a second phase: the first other switch (402) for coupling the first capacitor (205) to the first reference voltage (GND ); the first selection circuit (412) for coupling the second capacitor (406) to one of the second and third reference supply voltage nodes (Vppp, -Vref) selected on the basis of a digital conversion of the first and second differential input signal (Vinp, Vinn); and the second selection circuit (422) for coupling the second capacitor (408) to one of the second and third reference supply voltage nodes (Vrejt, -Vref) selected on the basis of the digital conversion.
    [4" id="c-fr-0004]
    The MDAC according to claim 2 or 3, further comprising: a fourth capacitor (235) having one of its nodes coupled to the second differential input node (234) and its other node coupled to the second input (240) via a first switch (238) and to the first reference voltage (GND) through a second other switch (432); and fifth and sixth capacitors (436, 438), wherein: the fifth capacitor (436) has one of its nodes coupled to the second differential input node (234) and its other node coupled to the second and third voltages of reference (VREF '-VREF) via a third selection circuit (442); and the sixth capacitor (438) has one of its nodes coupled to the second differential input node (234) and its other node coupled to the second and third reference voltages (VREF / -VREF) via a fourth selection circuit (452).
    [5" id="c-fr-0005]
    The MDAC according to claim 1, wherein: the second capacitor (622) has one of its nodes coupled to the first reference supply voltage node (GND), and its other node is coupled to the first input ( 210) to the first differential output node (Vqut-); and the third capacitor (624) has one of its nodes coupled to the first reference supply voltage node (GND) and its other node coupled to either the first input (210) or the first differential output node (VQT). -) ·
    [6" id="c-fr-0006]
    The MDAC according to claim 1, wherein the first capacitor (602) has its other node coupled to at least one reference supply voltage rail (+ VREF 'GND, -VrEF) through a fifth selection circuit (611), the MDAC further comprising: a seventh capacitor (604) having one of its nodes coupled to the first differential input node (204) and its other node coupled to the first input (210) by via a second switch (618) and at least one reference supply voltage node (+ VREF 'GND, -vref) via a sixth selection circuit (621).
    [7" id="c-fr-0007]
    The MDAC according to claim 6, wherein: the second capacitor (622) has one of its nodes coupled to the first reference voltage rail (GND), and its other node coupled to the first input (210) by the first intermediate third switch (628) and second and third reference supply voltage nodes (Vr E, -Vref) via a seventh selection circuit (631); and the third capacitor (624) has one of its nodes coupled to the first reference supply voltage node (GND), and its other node coupled to the first input (210) via a fourth switch (638) and at the second and third reference supply voltage nodes (Vrejt, -Vref) through an eighth selection circuit (641).
    [8" id="c-fr-0008]
    The MDAC of claim 7, further comprising a control circuit (684) adapted to: control, during a first phase, the first, second, third and fourth switches (608, 618, 628, 638) for coupling the first second, third and seventh capacitors (602, 604, 622, 124) at the first input (210); and controlling, during a second phase, the fifth, sixth, seventh and eighth selection circuits (611, 621, 631, 641) for coupling each of the first, second, third and seventh capacitors to one of the first, second and third reference supply voltage nodes (+ V ^ gp, GND, -Vjyrp) based on a digital conversion of the first and second differential input signals (Vinp, Vinn).
    [9" id="c-fr-0009]
    The MDAC according to any one of claims 6 to 8, further comprising: an eighth capacitor (642) having one of its nodes coupled to the second differential input node (234) and its other node coupled to the second input (240) via a fifth switch (648) and at least one reference supply voltage node (+ Vjyrp, 0, -VREp) through one or more other switches ( 651); a ninth capacitor (644) having one of its nodes coupled to the second differential input node (234) and its other node coupled to the second input (240) via a sixth switch (658) and at least one reference supply voltage node (+ V ^ gp, 0, -Vj ^ rp) through one or more other switches (161); a tenth capacitor (662) having one of its nodes coupled to the first reference supply voltage node (GND), and its other node coupled to the second input (240) via a seventh switch ( 668) and the second and third reference supply voltage nodes (Vppp, -Vref) via a ninth selection circuit (671); and an eleventh capacitor (644) having one of its nodes coupled to the first reference supply voltage node (GND), and its other node coupled to the second input (240) via an eighth switch (678) and the second and third reference supply voltage nodes (Vref / -Vref) via a tenth selection circuit (681).
    [10" id="c-fr-0010]
    The MDAC according to claim 1, wherein the second capacitor (622) has one of its nodes coupled to a first reference supply voltage node (GND), and its other node coupled to the first differential output node. (Vqut-) and has second and third reference supply voltage nodes (Vref ^ -vREF) via a seventh selection circuit (631); and the third capacitor (624) has one of its nodes coupled to the first reference supply voltage node (GND), and its other node coupled to the first differential output node (Vout-) and the second and third nodes reference supply voltage (VREF / -VreeREF) via an eighth selection circuit (641).
    [11" id="c-fr-0011]
    The MDAC according to claim 10, further comprising a control circuit (684) further adapted to: control, during an initial phase, said one or more other switches for coupling the first and seventh capacitors to the first input and the sixth inputs. and seventh selection circuitry for coupling the second and third capacitors to the first reference voltage.
    [12" id="c-fr-0012]
    The MDAC according to claim 10 or 11, further comprising: an eighth capacitor (642) having one of its nodes coupled to the second differential input node (234) and its other node coupled to the second input (240) via a fifth switch (648) and at least one reference supply voltage node (+ Vref> -vREF) via one or more other switches (651); a ninth capacitor (644) having one of its nodes coupled to the second differential input node (234) and its other node coupled to the second input (240) via a sixth switch (658) and at least one reference supply voltage node (+ VreF '0, -Vref) via one or more other switches (661); a tenth capacitor (662) having one of its nodes coupled to the first reference supply voltage node (GND), and its other node coupled to the second differential output node (Vqut +) via a seventh switch (668) and the second and third reference supply voltage nodes (Vref1, -vREf) via a ninth selection circuit (671); and an eleventh capacitor (664) having one of its nodes coupled to the first reference supply voltage node (GND), and its other node coupled to the second differential output node (VQT +) via a eighth switch (678) and at the second and third reference supply voltage nodes (VreF '_vref) via a tenth selection circuit (681).
    [13" id="c-fr-0013]
    The MDAC according to any one of claims 6 to 12, wherein the first, second, third, and seventh capacitors (602, 604, 622, 124) each have half the capacity of a twelfth coupled capacitor (216). between the input and differential output nodes of the differential amplifier (202).
    [14" id="c-fr-0014]
    A pipeline analog-to-digital converter comprising a plurality of pipeline coupled conversion stages (104), each conversion stage comprising the MDAC of any one of claims 1 to 13, and an r-bit analog-to-digital converter adapted to generate r bits based on the output signals of a last stage of the plurality of conversion stages.
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    同族专利:
    公开号 | 公开日
    FR3048317B1|2019-06-28|
    US9698815B1|2017-07-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
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    法律状态:
    2017-01-23| PLFP| Fee payment|Year of fee payment: 2 |
    2017-09-01| PLSC| Publication of the preliminary search report|Effective date: 20170901 |
    2018-01-23| PLFP| Fee payment|Year of fee payment: 3 |
    2020-01-22| PLFP| Fee payment|Year of fee payment: 5 |
    2021-11-12| ST| Notification of lapse|Effective date: 20211005 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1651640|2016-02-26|
    FR1651640A|FR3048317B1|2016-02-26|2016-02-26|ADC IN PIPELINE WITH CONSTANT LOAD REQUEST|FR1651640A| FR3048317B1|2016-02-26|2016-02-26|ADC IN PIPELINE WITH CONSTANT LOAD REQUEST|
    US15/237,767| US9698815B1|2016-02-26|2016-08-16|Pipelined ADC with constant charge demand|
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