• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to an electronic chip comprising SOI-on-insulator type MOS transistors (TA, TB, TC) arranged on first boxes adapted to be polarized (52A, 52B, 52C), all doped with a first type of conductivity, each first box including under the insulation of each transistor a back gate region (68A, 68B, 68C) doped more strongly than the first box, the first boxes being disjoint and included in a second box adapted to be polarized (54), doped with a second type of conductivity.
    公开号:FR3048304A1
    申请号:FR1651576
    申请日:2016-02-25
    公开日:2017-09-01
    发明作者:Philippe Galy
    申请人:STMicroelectronics SA；
    IPC主号:
    专利说明:

    ELECTRONIC CHIP WITH FRONT AND REAR GRID TRANSISTORS
    Field
    The present application relates to electronic chips, and more particularly to electronic chips comprising memory points and semiconductor-on-insulator (SOI) type MOS transistors having front and rear gates.
    Statement of Prior Art
    In an electronic chip in operation, MOS transistors are successively in blocked and passing states to perform functions such as logic operations. The off state or on state of a transistor depends on the voltage applied between a gate disposed above a channel forming area, or front gate, and a source of the transistor. When the voltage is greater in absolute value than a forward gate threshold voltage, the transistor is on. The transistor is in a locked state when the voltage is below the threshold voltage.
    When the transistor has a Silicon On Insulator (SOI) structure, that is to say that the transistor is formed in and on a thin layer of silicon covering an insulating layer disposed on a support, a rear gate can be formed under the transistor. This back gate is a doped region separated from the transistor by the insulating layer. Characteristics such as the front gate threshold voltage of the transistor then depend on the thickness of the insulating layer, the doping type of the back gate and the potential applied to the back gate. The application of a potential on the back gate makes it possible to accelerate the operation of the transistor or to reduce its consumption. The rear gate can further enable the transistor to operate in memory point.
    Various solutions have been proposed for producing front and rear gate transistors. These solutions pose various problems of implementation. summary
    Thus, an embodiment provides an electronic chip comprising SOI-on-insulator MOS transistors arranged on first boxes adapted to be polarized, all doped with a first type of conductivity, each first box including under the insulator of each transistor. a back gate region doped more strongly than the first box, the first boxes being disjoint and included in a second box adapted to be polarized, doped with a second type of conductivity.
    According to one embodiment, one of the back gate regions is doped with the second conductivity type and is adjacent to an overdoped region of the first conductivity type located under the insulator of the MOS transistors.
    According to one embodiment, said rear gate region is fully disposed under a channel formation area.
    According to one embodiment, each of said back gate region and said overdoped region is partially disposed below a channel forming area.
    According to one embodiment, said overdoped region is surrounded by said back gate region and is located below a central portion of a channel formation area.
    According to one embodiment, said overdoped region is doped P-type at a doping level greater than 10-L9 atoms / cm ^ and said back gate region is N-doped at a doping level greater than 1C) 19 atoms / cm ^.
    According to one embodiment, the MOS on insulator transistors are of the FDSOI type.
    Another embodiment provides a method of producing an electronic chip, wherein said back gate region and said overdoped region are obtained by partially overlapping ion implantations.
    Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures among which: FIG. 1 represents a partial and schematic sectional view of an electronic chip with front and rear gate transistors; FIG. 2 is a partial diagrammatic sectional view of an embodiment of a front and back gate transistor electronic chip; FIG. 3 is a partial schematic sectional view of an embodiment of a chip comprising a front and rear gate transistor; Figure 4 is a partial and schematic sectional view of another embodiment of a chip comprising a front and rear gate transistor; and Figures 5A and 5B schematically illustrate another embodiment of a chip comprising a front and rear gate transistor.
    detailed description
    The same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed.
    In the following description, when referring to relative position qualifiers, such as dull "on", "under", "above", "below", "upper", "lower" , etc., reference is made to the orientation of the element concerned in the relevant figures.
    FIG. 1 represents a partial and schematic sectional view of front and rear gate transistors made in a portion of an electronic chip 1.
    In the upper part of a silicon wafer 3, P-type doped boxes 5 are juxtaposed with N-type doped boxes 7. Only one box 5 and one box 7 are shown in FIG. 1. The box 5 of the P type is provided with a contact zone 9 and the N-type well 7 is provided with a contact zone 11. The contact zones 9 and 11 are connected to respective nodes 13 and 15 for applying potentials Vp and Vjg .
    A more heavily doped P-type zone 17 than the well 5 is located in an upper part of the well 5. The doped zone 17 is situated below an SOI type N-channel MOS transistor T1. The transistor T1 comprises on an insulator 19 a source zone 21 and a drain zone 23 separated by a channel forming zone 25 disposed under a front gate stack 27. The doped zone 17 constitutes a rear gate of the transistor T1.
    A SOI-type P-channel MOS transistor T2 is located above the box 7 in a similar arrangement to that of the transistor T1 above the box 5. The box 7 includes, under the transistor T2, a doped zone 29 with a higher doping level. N-type as the box 7. The transistor T2 comprises on an insulator 31 a channel forming zone 33 which extends between a drain zone 35 and a source zone 37 under a front gate stack 39. The doped zone 29 constitutes a rear gate of transistor T2.
    The transistors T1 and T2 and the contact zones 9 and 11 are separated by isolation trenches 41 penetrating the caissons P and N, 5 and 7.
    Connections between the transistors T1 and T2 make it possible to constitute logic circuits. For example, a transistor T1 and a transistor T2 are combined into an inverter coupling two nodes A and B. The inverter is supplied between a high potential V DD and a reference potential such as GND ground.
    During the operation of the inverter, it is sought to optimize the potentials Vp and V ^ to accelerate the operation of the inverter or reduce its consumption. In particular, the application of a positive potential Vp on the box 5 associated with the transistor T1, that is to say on the back gate of this transistor, makes it possible to accelerate the operation of the N channel transistor T1. application of a negative potential Vn on the box 7 makes it possible to accelerate the operation of the P-channel transistor T2. The PN junction between the boxes 5 and 7 is then forward biased and a leakage current appears between the boxes 5 and 7. As a result, the voltage applied between the boxes 5 and 7 can not exceed about 0.3 V and the possible acceleration of the operation of the inverter is limited.
    Transistors T1 and T2 may be used as memory points. Such memory points are programmable and erasable by variations of the potentials Vp and V ^ applied to the caissons. The existence of the P-N junction between the caissons 5 and 7 limits the possibilities of applying these potentials between neighboring caissons 5 and 7.
    It is desired to produce an electronic chip comprising front and rear gate transistors arranged on boxes and to apply between neighboring boxes variable voltages of varying directions that can reach, for example, about ten volts.
    Figure 2 is a partial schematic sectional view of an embodiment of a chip portion 50 comprising front and rear gate transistors. Transistors of the SOI, TA, TB and TC type are represented, designed to operate as a logic transistor for the transistor TA and as memory points for the transistors TB and TC.
    First caissons 52A, 52B and 52C are all p-type doped. These caissons are disjoint and are included in the upper part of a second N type doped caisson 54. The caisson 54 is formed in an upper part of a slice. P-type doped semiconductor 55, for example of silicon. Portions 54A (N-type doped here) of the well 54 are disposed between the wells 52A and 52B and between the wells 52B and 52C. Two diodes head to tail are thus formed between two adjacent boxes. The box 54 is connected by a contact zone 56 (N +), more heavily doped N-type than the box 54, to an application node of a positive potential VMAX. Each of the boxes 52A, 52B and 52C is provided with a respective P-type contact zone 57A, 57B and 57C (P +), which is more strongly doped than the box, and is polarizable at a respective potential VBA, VBB and VBC.
    An N-channel MOS TA transistor is located on the box 52A. The transistor TA comprises, on an insulator 58A, a channel forming zone 60A which extends under a front gate 62A between a source zone 64A and a drain zone 66A. The box 52A comprises under the TA transistor a 68A more heavily P-type back gate region 68A than the box 52A.
    On the well 52B, the P-channel MOS transistor TB comprises, on an insulator 58B, a channel forming zone 60B which extends under a front gate 62B between source 64B and drain 66B regions. The box 52B comprises, below the transistor TB, a backbone region 68B that is more heavily doped with the P type than the box 52B.
    On the box 52C, the P-channel MOS transistor TC includes, on an insulator 58C, a channel forming area 60C under a front gate 62C between source 64C and drain 66C areas. The box 52C comprises, under the transistor TC, an N-type 68C backgrid gate region.
    The contact zones 56 and 57A are separated by an isolation trench 70. The contact zones 57A, 57B, 57C are respectively separated from the transistors TA, TB and TC by isolation trenches 70. realization without isolation trench between the transistors TA and TB and between the transistors TB and TC, the boxes 52A, 52B and 52C then being separated by the portions 54A of the box 54. By way of example, the transistors TA, TB and TC are SOI type completely depleted, said FDSOI (English "Fully Depleted SOI"), that is to say that the channel formation zone is intrinsic silicon thickness less than 15 nm. For example, the insulating layer has a thickness of between 10 and 30 nm.
    In operation, a reference potential, for example the GND mass, is applied to the semiconductor wafer 55. The VMAX potential applied to the N-doped well 54 is greater than, or equal to, 0.3 V to the potential potentials. to be applied to the caissons 52A, 52B and 52C. By way of example, the VMAX potential is greater than 5 V.
    When using the transistor TA, it is thus possible to apply on the box 52A and thus on the rear gate of the transistor TA any potential VBA of value less than or equal to 0.3 V, at the potential VMAX. In particular, a high potential, for example greater than 4 V, can be applied to the rear gate of the transistor TA, which allows a particularly fast operation of the transistor TA. A strongly negative potential, for example less than -4 V, can also be applied in order to reduce the consumption of the transistor TA.
    To program the transistor TB used in the memory point, a voltage is applied between the rear gate 68B and the source 64B, or back gate voltage, high. This makes it possible to store charges in the channel formation zone 60B.
    To clear the memory point, a zero or negative back gate voltage is temporarily applied.
    To program the transistor CT used in the memory point, a high voltage is applied between on the one hand the box 52C and on the other hand the source 64C and the drain 66C. The back gate region 68C acquires a load across the P-N junction between the well 52C and the region 68C. To erase the memory point, a strongly negative potential is applied to the box 52C, for example a potential lower than -8 V so that the voltage between the region 68C and the box 52C is greater than the avalanche voltage of the PN junction corresponding. One can also expect the elimination of the charges by leakage through this junction P-N.
    Thus, a high positive potential can be applied to the box located under one of the transistors regardless of the potential applied to the neighboring boxes.
    In the zone of the chip located above the N-well 54, the transistors are all formed above P type doped caissons. This makes it possible to apply a particularly high VMAX potential to the N-well and to obtain caissons. P particularly close. By way of example, the distances between adjacent caissons P are less than 200 nm.
    The transistor TC has been described in the context of a memory point operation. If it is desired to use in transistor logic a transistor of the type of the transistor TC, that is to say a transistor having an N-type doped back gate included in a box P, a problem arises when one varies. the potential of the box 52C between a high value and a lower value. Indeed, the P-N junction between the box 52C and the rear gate region 68C is reverse biased and the potential of the rear gate remains at the high value. It is therefore desired to make a transistor having an N-type back gate located above a doped P type box, in which the potential of the rear gate can be rapidly reduced.
    FIG. 3 is a partial schematic sectional view of a chip portion 80 similar to the portion of the chip 50 described in connection with FIG. 2, comprising a transistor provided with a doped back gate region of the type N located in a doped P type box.
    The chip 80 comprises a first P type doped box 52 included in the upper part of a second N type doped box 54. The box 54 is located in the upper part of a P-type doped semiconductor wafer 55, for example silicon. The box 54 is connected by a contact zone 56 (N +), more heavily doped N-type than the box 54, to an application node VMAX potential. The box 52 is connected by a contact zone 57 (P +), more heavily doped P-type than the box 57, to an application node of a potential VB. A SOI type P-channel MOS transistor T10, preferably FDSOI, comprises, on an insulator 58, a channel forming zone 60 that extends under a gate stack 62 between a source zone 64 and a drain 66. The contact zones 56 and 57 and the transistor T10 are separated by isolation trenches 70. A more heavily doped back gate region 68 of the N (N +) type than the box 52 is disposed in the upper part of the box 52 of the P type and is located under the insulator 58 below the transistor T10.
    A P-type overdoped region, P +, that is to say more heavily doped P-type than the box 52, adjacent to the rear gate region 68, is located under the insulator 58. The training zone of channel is entirely located above the back gate region 68, and the overdoped region 84 is located below a portion of the source zone 64 (as shown in Fig. 3) and / or the drain zone 66.
    When the transistor T10 is in operation, if a reduction of the potential VB applied on the box 52 is brought about between a high value and a lower value, as has been seen previously, in the absence of the overdoped region 84, the potential of the back gate 68 will retain a high value.
    Due to the presence of the overdoped region 84, charges can flow in both directions through the Ρ + -Ν + junction between regions 68 and 84. As a result, the potential of the N + 68 back gate region follows with a very low time constant the potential VB of the box 52. Thus, the prediction of an overdoped region 84 makes it possible to apply to the rear gate 68 of the transistor T10 any variable potential less than or equal to 0.3 V, at the VMAX potential applied to the box 54.
    The overdoped region P + 84 has, for example, a doping level of between 10 and 10 atoms / cm 2 and the N + backgrid region 68 has a doping level of between 10 and 1020 atoms / cm 2, or even 10 ^ 1 atoms / cm ^. Preferably, the implantations intended for the formation of the N + 68 region and of the P + region 84 are slightly overlapping. As a result, at the P + -N + junction, a degenerate region containing both N-type dopant atoms at a level greater than 10 ^ -9 atoms / cm 2 and P-type dopant atoms at a higher level. at 10 ^ 9 atoms / cm 2. This degenerate region has a very disturbed crystal structure that degrades the characteristics of the P + -N + junction and makes it passable in both directions.
    Moreover, by way of example, the casing P 52 may have a doping level of between 10 -3 and 10 -7 atoms / cm 2. The casing N 54 may have a doping level of between 1 ° C. 16 and 1017 atoms / cm 2.
    Note that the overdoped region 84 may act as a rear gate portion, as will be described by way of example in connection with the following figures.
    FIGS. 4 and 5A are diagrammatic partial sectional views of examples of chip portions comprising N-type doped back gate transistors. FIG. 5B is a sectional view of a rear gate region, along a BB plane. represented in FIG. 5A.
    The chip portion shown in FIG. 4 is similar to the partially sectioned chip portion in FIG. 3. Overdoped region 84 of transistor T10 has been replaced by an overdoped region 84D of different arrangement. The region 84D is located under the insulator 58 partly below the drain zone 66 and partly below the channel forming zone 60 of the transistor. The back gate region is located partly below the channel formation zone.
    The chip portion illustrated in FIG. 5A is similar to the visible part in partial section in FIG. 3. The overdoped region 84 has been replaced by an overdoped region 84E, surrounded in top view (FIG. 5B) of the doped region 68 of type N. The overdoped region 84E occupies a central portion below the visible dotted line formation zone 60 in FIG. 5A.
    The P-type N regions 68 of each of the transistors shown in FIGS. 4, 5A and 5B together form a back gate. Their arrangement determines the characteristics of the transistor such as the front gate threshold voltage, or how the current between drain and source varies depending on the potentials VB and VF applied to the front and rear gates. Thus, one can advantageously obtain transistors of optimized characteristics, particularly fast or of particularly low energy consumption.
    Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although, in the embodiments described, first disjoint caissons of type P are included in a second N type caisson polarized at a positive potential VMAX, the first disjoint caissons can be of type N included in a second subwoofer polarized type P at a negative potential VMIN. The potential VMIN is then lower, or equal to a voltage closely related to the voltage drop of a P-N junction, to the potentials applied to the first boxes.
    Although, in described embodiments, only one overdoped region 84 is juxtaposed with a back gate region 68, two or more overdoped regions may be disposed under the insulator in contact with the back gate region. By way of example, two overdoped regions may be arranged symmetrically under the drain and source zones of the transistor.
    In addition, although the transistors described are based on silicon, other semiconductors could be used.
    权利要求:
    Claims (8)
    [1" id="c-fr-0001]
    An electronic chip comprising SOI-on-insulator type MOS transistors (TA, TB, TC, T10) arranged on first boxes adapted to be polarized (52; 52A, 52B, 52C), all of which are doped with a first type of conductivity. each first box including under the insulator of each transistor a back gate region (68; 68A, 68B, 68C) doped more strongly than the first box, the first boxes being disjoint and included in a second box adapted to be polarized ( 54) doped with a second type of conductivity.
    [2" id="c-fr-0002]
    An electronic chip according to claim 1, wherein one of the back gate regions (68) is doped with the second conductivity type and is adjacent to an overdoped region (84) of the first conductivity type located under the insulator (58). MOS transistors.
    [3" id="c-fr-0003]
    An electronic chip according to claim 2, wherein said back gate region (68) is fully disposed under a channel forming area (60).
    [4" id="c-fr-0004]
    An electronic chip according to claim 2, wherein each of said back gate region and said overdoped region (84D) is partially disposed below a channel forming area (60).
    [5" id="c-fr-0005]
    An electronic chip according to claim 2, wherein said overdoped region (84E) is surrounded by said back gate region (68) and is located below a central portion of a channel forming zone (60). .
    [6" id="c-fr-0006]
    An electronic chip according to any one of claims 2 to 5, wherein said overdoped region (84; 84D; 84E) is doped P-type at a doping level of greater than 10 ^ -9 atoms / cm 2 and said region rear gate (68) is N-doped at a doping level of greater than 10 -9 atoms / cm 2.
    [7" id="c-fr-0007]
    7. An electronic chip according to any one of claims 1 to 6, wherein the MOS transistors on insulator are FDSOI type.
    [8" id="c-fr-0008]
    The method of producing an electronic chip according to any one of claims 2 to 7, wherein said back gate region (68) and said overdoped region (84) are obtained by partially overlapping ion implantations.
    类似技术:
    公开号 | 公开日 | 专利标题
    FR2993404A1|2014-01-17|INTEGRATED SOI CIRCUIT COMPRISING A THYRISTOR | FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES
    FR2953641A1|2011-06-10|HOMOGENEOUS TRANSISTOR CIRCUIT ON SEOI WITH REAR CONTROL CHANNEL BURED UNDER THE INSULATING LAYER
    EP2784817A1|2014-10-01|A method of controlling an integrated circuit
    FR3048304A1|2017-09-01|ELECTRONIC CHIP WITH FRONT AND REAR GRID TRANSISTORS
    EP2750180B1|2019-02-20|Integrated circuit including a clock tree cell
    FR2558010A1|1985-07-12|PROCESS FOR THE MANUFACTURE OF COMPLEMENTARY MOS TRANSISTORS WITH LOW THRESHOLD VOLTAGES IN INTEGRATED HIGH DENSITY CIRCUITS AND STRUCTURE RESULTING THEREFROM
    FR2930073A1|2009-10-16|METHOD FOR MANUFACTURING COMPLEMENTARY P AND N TYPE MOSFET TRANSISTORS, AND ELECTRONIC DEVICE COMPRISING SUCH TRANSISTORS, AND PROCESSOR COMPRISING AT LEAST ONE SUCH DEVICE.
    FR3005203A1|2014-10-31|INTEGRATED SINGLE CIRCUIT COMPRISING A PROTECTION TRANSISTOR AGAINST ELECTROSTATIC DISCHARGES
    EP2685501A1|2014-01-15|SOI integrated circuit comprising an underlying protection transistor
    EP2835825A1|2015-02-11|SOI integrated circuit provided with a device for protection against electrostatic discharges
    FR2957193A1|2011-09-09|SEOI SUBSTRATE DATA PATH CELL WITH REAR CONTROL GRID BURED UNDER THE INSULATING LAYER
    FR3007577A1|2014-12-26|TRANSISTORS WITH DIFFERENT LEVELS OF THRESHOLD VOLTAGES AND ABSENCE OF DISTORTIONS BETWEEN NMOS AND PMOS
    FR2993403A1|2014-01-17|INTEGRATED CIRCUIT ON ITS COMPRISING A TRIAC FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES
    WO2014057112A1|2014-04-17|Integrated circuit comprising transistors with different threshold voltages
    FR2689683A1|1993-10-08|Semiconductor device with complementary transistors
    EP2750179B1|2021-06-16|Integrated circuit including a clock tree cell
    FR2993406A1|2014-01-17|INTEGRATED SOI CIRCUIT COMPRISING A BIPOLAR TRANSISTOR WITH SEPARATE DEPTH SINGLE INSULATION TRENCHES
    FR2953062A1|2011-05-27|LOW VOLTAGE BIDIRECTIONAL PROTECTION DIODE
    FR2957457A1|2011-09-16|METHOD FOR MANUFACTURING MEMORY POINT ANTI-FUSE
    FR3001084A1|2014-07-18|TRANSISTOR WITH GRID AND MASS PLAN COUPLES
    FR2999802A1|2014-06-20|CMOS CELL REALIZED IN FD SOI TECHNOLOGY
    FR3021458A1|2015-11-27|PHOTONIC CMOS INVERTER
    EP3629380A1|2020-04-01|Diode structure
    FR2981503A1|2013-04-19|TRANSISTOR MOS NOT SUBJECT TO HUMP EFFECT
    EP2556533B1|2020-10-07|Ram memory cell comprising a transistor
    同族专利:
    公开号 | 公开日
    FR3048304B1|2019-03-15|
    US9660034B1|2017-05-23|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20120146147A1|2010-12-09|2012-06-14|International Business Machines Corporation|Pseudo Butted Junction Structure for Back Plane Connection|
    WO2012160071A1|2011-05-24|2012-11-29|Commissariat à l'énergie atomique et aux énergies alternatives|Self-contained integrated circuit including adjacent cells of different types|
    US20130001665A1|2011-06-23|2013-01-03|Huilong Zhu|Mosfet and method for manufacturing the same|
    US20130214356A1|2012-02-16|2013-08-22|International Business Machines Corporation|Mosfet with work function adjusted metal backgate|
    WO2014131461A1|2013-02-28|2014-09-04|Commissariat à l'énergie atomique et aux énergies alternatives|Dual sti integrated circuit including fdsoi transistors and method for manufacturing the same|
    JP2007242950A|2006-03-09|2007-09-20|Toshiba Corp|Semiconductor memory|
    US7759714B2|2007-06-26|2010-07-20|Hitachi, Ltd.|Semiconductor device|
    US8994085B2|2012-01-06|2015-03-31|International Business Machines Corporation|Integrated circuit including DRAM and SRAM/logic|
    US20150001623A1|2013-06-26|2015-01-01|Tsinghua University|Field effect transistor and method for forming the same|
    JP6076224B2|2013-09-05|2017-02-08|ルネサスエレクトロニクス株式会社|Semiconductor device and manufacturing method thereof|FR3053834B1|2016-07-05|2020-06-12|Stmicroelectronics Sa|TRANSISTOR STRUCTURE|
    US9941301B1|2016-12-22|2018-04-10|Globalfoundries Inc.|Fully depleted silicon-on-insulatortransistor device and self-aligned active area in FDSOI bulk exposed regions|
    US11107918B2|2019-05-13|2021-08-31|Mediatek Singapore Pte. Ltd.|Semiconductor structure for fully depleted silicon-on-insulatortransistor|
    法律状态:
    2017-01-23| PLFP| Fee payment|Year of fee payment: 2 |
    2017-09-01| PLSC| Publication of the preliminary search report|Effective date: 20170901 |
    2018-01-23| PLFP| Fee payment|Year of fee payment: 3 |
    2020-01-22| PLFP| Fee payment|Year of fee payment: 5 |
    2021-11-12| ST| Notification of lapse|Effective date: 20211005 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1651576A|FR3048304B1|2016-02-25|2016-02-25|ELECTRONIC CHIP WITH FRONT AND REAR GRID TRANSISTORS|
    FR1651576|2016-02-25|FR1651576A| FR3048304B1|2016-02-25|2016-02-25|ELECTRONIC CHIP WITH FRONT AND REAR GRID TRANSISTORS|
    US15/229,746| US9660034B1|2016-02-25|2016-08-05|Electronic chip comprising transistors with front and back gates|
    [返回顶部]