• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method of detecting a thinning of the semiconductor substrate of an integrated circuit from its rear face, comprising a measurement of a physical quantity representative of the resistance between the ends (EX11, EX21) of two electrically conductive contacts (C1, C2) located at the interface between an insulating region (RIS) and an underlying substrate region (CS), the two electrically conductive contacts (C1, C2) are at least partially in said insulating region (RIS).
    公开号:FR3048103A1
    申请号:FR1651424
    申请日:2016-02-22
    公开日:2017-08-25
    发明作者:Pascal Fornara；Christian Rivero
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    The invention relates to integrated circuits, and more particularly to the detection of a possible thinning of the substrate of an integrated circuit. from its back side.
    Integrated circuits, in particular those equipped with memories containing sensitive information, must as far as possible be protected against attacks, in particular intended to discover stored data.
    A possible attack can be carried out by a focused ion beam (FIB Focus Ion Beam), for example by means of a laser beam. The effectiveness of such an attack increases when the substrate of the integrated circuit is thinned by the attacker, from its rear face so as to be as close as possible to the components of the integrated circuit, made at its front face.
    According to a mode of implementation and of realization, it is therefore proposed a detection of a possible thinning of the substrate of an integrated circuit from its rear face, which is simple to implement and particularly compact in terms of size. surface.
    Thus, it is advantageously proposed to use the space occupied by the insulating regions, for example of the "shallow trench" (STI: Shallow Trench Isolation) type, of the integrated circuit to make electrically conductive contacts whose ends will lead to in the underlying substrate region so as to be able to measure a magnitude representative of the resistance between these two ends.
    The formation of these two contacts extending in an insulating region does not affect the surface area of the integrated circuit. And, a thinning of the substrate to come close to, or even reach, the insulating region will lead to an increase in the resistance between these two contacts that will be easily measured.
    It is also advantageously proposed to make such contacts by a method that is perfectly compatible with the conventional methods of manufacturing integrated circuits.
    According to one aspect, there is provided a method for detecting a thinning of the semiconductor substrate of an integrated circuit from its rear face, comprising a measurement of a physical quantity representative of the resistance between the ends of two electrically conductive contacts. located at the interface between an insulating region, for example a shallow trench, and an underlying substrate region, the two electrically conductive contacts extending at least partially in said insulating region.
    According to another aspect, there is provided an integrated circuit, comprising a semiconductor substrate, at least one insulating region, for example of the shallow trench type, formed in the substrate, and a detector comprising two electrically conductive contacts extending to at least partially in said insulating region, each having a first end located at the interface between the insulating region and an underlying substrate region, and a second end; the two second ends are intended to be connected to an electrical circuit, preferably incorporated in the integrated circuit, configured to deliver an electrical signal representative of a value of the resistance between the two first ends.
    According to one embodiment, the integrated circuit generally comprises a dielectric layer (known to those skilled in the art under the acronym PMD "Pre Metal Dielectric"), located above the substrate, and at least a first level metallization located above the dielectric layer. The two electrically conductive contacts then also extend into the dielectric layer, their second end opening on the first level of metallization. Generally, an integrated circuit comprises a plurality of protruding components above the substrate. This is the case for example for transistor gate regions. These transistors may be single-gate transistors with more or less significant gate oxide thicknesses, or double-gate transistors such as those used in non-volatile memories (FLASH or EEPROM memory).
    The integrated circuit then generally comprises an etch stop layer (called CESL layer: Etch Stop Layer contact) covering in particular the protruding portions of the components and situated between on the one hand said dielectric layer and on the other hand the substrate and said insulating region. Additional electrically conductive contacts then come to contact some of the protruding portions of the components and silicided areas (metal silicide areas) of the substrate through the etch stop layer.
    And, said two electrically conductive contacts used to identify any thinning of the substrate, also pass through said etch stop layer.
    According to another aspect, there is provided a method for producing the two electrically conductive contacts of the integrated circuit as defined above, in which the etching operations used to make these two contacts are identical to those used to make said additional contacts.
    More specifically, according to one embodiment in which the semiconductor substrate comprises silicon, said etching operations comprise a final etch, selective with respect to the silicon and metal silicide of the silicided regions, and intended to etch the layer. stopping etching, this final etching being a time etching also for etching the material of the insulating region, the etching time being determined as a function of the depth of said insulating region.
    The inventors have indeed observed that this final etching for etching the etch stop layer to allow future contacts to contact the silicided regions, also allowed without any modification, to etch the insulating region so as to form the orifices intended to receive future contacts to detect a possible thinning of the substrate. In this respect, it is sufficient to determine the etching time as a function of the depth of the insulating region so as to terminate the orifices at the interface with the underlying substrate region. And, since this etching is selective with respect to silicon and metal silicide, the silicided regions in particular will be only slightly impacted by the additional etching time.
    It should therefore be noted here that the making of these contacts in the insulating region is perfectly compatible with the conventional etching operations existing in an integrated circuit and require only a modification of the mask "contacts". Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and embodiments, in no way limiting, and the attached drawings in which: FIGS. 1 and 2 schematically illustrate various modes of implementation and realization of the invention.
    In FIG. 1, the reference CI denotes an integrated circuit comprising a semiconductor substrate SB, for example of conductivity type P, comprising at least one insulating region RIS, for example of the shallow trench type (STI), which in the example shown here, is located above a box CS of N conductivity type.
    The upper face (or front face) FS of the substrate is covered by an etch stop layer 1 (CESL layer) generally of silicon nitride SiN. This layer 1 is covered by a dielectric layer 2, commonly designated by those skilled in the art by the acronym PMD, and separates the etch stop layer 1 from the first level of metallization Ml of the interconnection portion. integrated circuit commonly designated by the skilled person under the acronym BEOL (Back End Of Line).
    In order to be able to detect any thinning of the substrate SB from its rear face FA, opposite to its upper face or front face FS, the integrated circuit CI comprises a detector DT here comprising two electrically conductive contacts C1, C2 extending across the dielectric layer 2, the etch stop layer 1 and the insulating region RIS.
    The two contacts C1 and C2 respectively have two first ends EX11 and EX21 located at the interface between the insulating region RIS and the underlying substrate region, here the caisson CS.
    The two contacts C1 and C2 also comprise respectively two second ends EX12 and EX22, opposite the first ends, and located at the interface between the dielectric layer 2 and the first level of metallization Ml.
    These two second ends EX12 and EX22 are in contact with two metallic tracks PST1 and PST2 of metallization level M1 which are connected to an electric circuit 3.
    This electrical circuit 3 is, although it is not essential, preferably incorporated within the integrated circuit CI.
    The electrical circuit 3 comprises, by way of nonlimiting example, a comparator 31 whose non-inverting input is connected to a voltage divider bridge 30 and whose inverting input is connected to the metal track PST2 and therefore to the contact C2. The other metal track PST1, and therefore the other contact Cl, is connected to a supply voltage, here the ground GND.
    The comparator 31 compares the voltage present on the metal track PST2 with the reference voltage supplied by the voltage divider 30 and delivers a signal S whose value is representative of whether the voltage present at the metal track PST2 is less than or less than the reference voltage.
    And, the voltage PST2 is a magnitude representative of the current flowing in the resistive path formed by the two contacts C1 and C2 and the underlying substrate region CS, and in particular the resistance of this underlying substrate region.
    If the substrate is not thinned, the resistance between the two first ends EX11 and EX21 is small, for example of the order of 10 kΩ, for, for example, a distance L between the two contacts of the order of 0, 8 microns and a width W equal to 0.8 pm (for a 90 nanometer technology).
    On the other hand, if an attacker thins the substrate SB to approach closer to, or even reach, the insulating region RIS, then the resistance between the first two ends EX11 and EX21 increases sharply to reach, for example, a value of 20 kΩ. , which then causes an increase in the voltage on the track PST2 and the switching of the comparator 31, the signal S then being representative of a thinning of the substrate.
    Of course in this case, processing means, for example a logic, not shown here, can inhibit the operation of the integrated circuit.
    Reference will now be made more particularly to FIG. 2 to describe an embodiment of the contacts C1 and C2.
    FIG. 2 diagrammatically shows other components of the integrated circuit, for example but not limited to two transistors T1 and T2.
    The transistor T1 is a transistor with a double gate region PI and P2, such as that used in non-volatile memories, for example of the FLASH or EEPROM type.
    The first gate region PI is isolated from the substrate by a first gate oxide OX1 and the two gate regions PI and P2 are mutually isolated by a second gate oxide OX2.
    The transistor T2 is a conventional transistor whose gate region PI is separated from the substrate by a gate oxide 0X3.
    The source, drain and gate regions of these transistors conventionally comprise in the vicinity of their surface, metal silicide zones (silicided zones) ZS1, ZS2, ZS3, ZS4 and ZS5.
    Some of these silicided zones are intended to be contacted by additional electrically conductive contacts, for example the silicified zones ZS3, ZS4 and ZS5.
    FIG. 2 shows the orifices ORD1, ORD2 and ORD3 intended to be filled with one or more electrically conductive materials, for example tungsten, so as to form the three electrically conductive additional contacts mentioned above, as well as the two orifices. OR1 and OR2 also intended to be filled by the same electrically conductive metal, so as to form the two electrically conductive contacts C1 and C2.
    These various orifices result from etching steps, here comprising four plasma etching operations, GV1, GV2, GV3 and GV4 having conventional characteristics in terms of the gas used in particular.
    Conventionally, the dielectric layer 2 is covered with an antireflection layer, generally known to those skilled in the art under the acronym BARC. This antireflection layer is surmounted by a layer of resin which undergoes a photolithography and insolation step so as to define the locations of the different orifices ORD 1-ORD3 and OR1-OR2.
    After the development of the resin, the first etching GV1, which is conventionally a plasma etching, is carried out so as to remove the portion of the antireflection layer located in the holes of the resin. By way of non-limiting example, in a 90 nanometer technology, it is possible to use CF4 gas at a pressure of the order of 80 millitorr.
    A second etching GV2 is then carried out which will make it possible to etch a first part of the dielectric layer 2.
    This second etching GV2 is a fairly aggressive plasma etching that uses for example as CH2F2 gas at a pressure of 100 millitorr.
    This being so, this aggressive engraving produces a "barrel" effect for the orifices, that is to say, the more we engrave, the more the diameter of the orifice will enlarge. This is the reason why this second etching GV2 is interrupted after a selected time to replace it with a third etching GV3 which will not only burn the remainder of the dielectric layer 2 but also polymerize the flanks of the orifice. in order to obtain in the end a virtually cylindrical orifice. By way of nonlimiting example, it will be possible to choose for such a third GV3 plasma etching of C4F6 at a pressure of the order of 45 millitorr. At the end of these etching operations, the various orifices come to lead to the etching stop layer 1.
    A fourth GV4 plasma etching is then performed so as to etch the layer 1 to lead to the silicified zones ZS4, ZS5 and ZS3. By way of non-limiting example, this time it is possible to use CHF3 gas at a pressure of the order of 120 millitorr.
    This fourth etching GV4 is a time etching which also allows, as illustrated in FIG. 2, to etch the insulating material, for example silicon silicide, from the insulating region RIS.
    The etching time depends on the height h of the insulating region and the skilled person will adjust the etching time depending on the characteristics of the etching so that the orifices OR1 and OR2 reach the underlying substrate region CS.
    And, this lengthening of the etching time has almost no impact on the silicided regions ZS3, ZS4 and ZS5 because this etching chemistry is selective with respect to metal silicide and silicon.
    As a result, the production of the two contacts C1 and C2 only required a local modification of the mask "contacts" and an increase in the time of the etching GV4 compared with a conventional etching GV4.
    权利要求:
    Claims (8)
    [1" id="c-fr-0001]
    1. A method for detecting a thinning of the semiconductor substrate of an integrated circuit from its rear face, comprising a measurement of a physical quantity representative of the resistance between the ends (EX11, EX21) of two electrically conductive contacts ( C1, C2) located at the interface between an insulating region (RIS) and an underlying substrate region (CS), the two electrically conductive contacts (C1, C2) extending at least partially in said insulating region (RIS). ).
    [2" id="c-fr-0002]
    An integrated circuit, comprising a semiconductor substrate (SB), at least one insulating region (RIS) formed in the substrate, and a detector (DT) having two electrically conductive contacts (C1, C2) extending at least partially in said insulating region, each having a first end (EX11, EX21) located at the interface between the insulating region (RIS) and an underlying substrate region (CS), and a second end (EX12, EX22), both second ends (EX11, EX21) being intended to be connected to an electrical circuit (3) configured to deliver an electrical signal (S) representative of a value of the resistance between the two first ends (EX11, EX21).
    [3" id="c-fr-0003]
    The integrated circuit of claim 2, further comprising a dielectric layer (2) above the substrate and at least a first metallization level (M1) located above the dielectric layer, and the two electrically conductive contacts. (Cl, C2) also extend in the dielectric layer, their second end opening on the first level of metallization.
    [4" id="c-fr-0004]
    An integrated circuit according to claim 3, further comprising a plurality of components (T1, T2) protruding above the substrate, an etch stop layer (1) covering the protruding portions of the components and located between on the one hand said dielectric layer (2) and secondly the substrate (SB) and said insulating region (RIS), additional electrically conductive contacts coming to contact said protruding parts of the components and silicided zones (ZS3, ZS4, ZS5) of the substrate through said etch stop layer (1), and said two electrically conductive contacts (C1, C2) also pass through said etch stop layer (1).
    [5" id="c-fr-0005]
    An integrated circuit according to one of claims 2 to 4, wherein said at least one insulating region (RIS) is a shallow trench.
    [6" id="c-fr-0006]
    6. Integrated circuit according to one of claims 2 to 5, wherein said electric circuit (3) is incorporated in the integrated circuit.
    [7" id="c-fr-0007]
    7. A method of producing the two electrically conductive contacts of the integrated circuit according to claim 4 or 5, wherein the etching operations (GV1, GV2, GV3, GV4) used to make these two contacts are identical to those used to make said contacts. additional.
    [8" id="c-fr-0008]
    8. The method of claim 7, wherein said semiconductor substrate comprises silicon, said etching operations comprise a final etching (GY4), selective with respect to the silicon and metal silicide of the silicide regions, and intended to etch the etching stop layer (1), this final etching being a time etching also for etching the material of the insulating region, the etching time being determined as a function of the height (h) of said insulating region.
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    引用文献:
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    法律状态:
    2017-01-23| PLFP| Fee payment|Year of fee payment: 2 |
    2017-08-25| PLSC| Publication of the preliminary search report|Effective date: 20170825 |
    2018-01-23| PLFP| Fee payment|Year of fee payment: 3 |
    2020-01-22| PLFP| Fee payment|Year of fee payment: 5 |
    2021-01-20| PLFP| Fee payment|Year of fee payment: 6 |
    2022-01-19| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1651424|2016-02-22|
    FR1651424A|FR3048103B1|2016-02-22|2016-02-22|METHOD FOR DETECTING A SLIMMING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM THE BACK SIDE AND THE CORRESPONDING INTEGRATED CIRCUIT|FR1651424A| FR3048103B1|2016-02-22|2016-02-22|METHOD FOR DETECTING A SLIMMING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM THE BACK SIDE AND THE CORRESPONDING INTEGRATED CIRCUIT|
    CN201610579779.6A| CN107104062B|2016-02-22|2016-07-21|Method for thinning a semiconductor substrate for testing an integrated circuit from the rear side thereof and corresponding integrated circuit|
    CN201620774874.7U| CN205828352U|2016-02-22|2016-07-21|Integrated circuit|
    US15/218,261| US9916902B2|2016-02-22|2016-07-25|Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face and corresponding integrated circuit|
    DE102016116228.0A| DE102016116228A1|2016-02-22|2016-08-31|A method of detecting a thinning of the semiconductor substrate of an integrated circuit from its backside and corresponding integrated circuit|
    US15/886,243| US10580498B2|2016-02-22|2018-02-01|Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face and corresponding integrated circuit|
    US16/747,995| US10878918B2|2016-02-22|2020-01-21|Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face and corresponding integrated circuit|
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