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    • 专利摘要:
    The invention relates to a normally blocked type high electron mobility field effect transistor (1), comprising: a first P-doped GaN layer (14); a second N-doped GaN layer (15) formed on the first GaN layer; a third layer of GaN (16) unintentionally doped and formed on the second layer of GaN; a semiconductor layer (17) formed to form an electron gas layer (18); a cavity formed through said third layer of GaN, without reaching the bottom of the second layer of GaN; a gate (3) including a conductive gate material (31) and a gate insulator layer (32) disposed in said cavity, said gate insulator layer electrically insulating said conductive gate material (31) relative to said second and third layers of GaN.
    公开号:FR3047608A1
    申请号:FR1650901
    申请日:2016-02-04
    公开日:2017-08-11
    发明作者:Erwan Morvan
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Avec un dopage P réalisé avec du Magnésium, l’énergie d’ionisation de l’accepteur Mg dans le GaN est d’environ 180meV. L’ionisation est donc partielle à la température RT. Il faut donc en tenir compte par l’inégalité Na- < Na à la température RT.
    Avec ni * 1.9 e-10 cm 3 à la température de 298K, Vbi prend des valeurs de 3.1 +/- 0.1 V pour des valeurs utiles de Nd+ et Na'. Vbi reste peu sensible aux variations de Na- et Nd+ en raison du logarithme dans la relation. La tension de seuil Vth du transistor 1 (formule détaillée par la suite) est donc relativement peu sensible à la concentration de dopants dans les couches 14 et 15.
    Pour garantir l’absence de conduction dans le canal lorsque la différence de potentiel Vgs entre grille et source est nulle, on fait en sorte que les charges positives développées dans la couche GaN 15 soient insuffisantes pour équilibrer les charges négatives développées dans la couche GaN 14. Cette condition peut notamment être remplie au moyen d’une couche GaN 15 relativement peu épaisse.
    Cette condition peut par exemple s’exprimer par l’inégalité suivante, avec WnO, l’épaisseur de GaN à dopage N pouvant être déplétée par la couche de GaN 14 à dopage P.
    Le diagramme de la figure 4 illustre en trait plein la bande de conduction du transistor 1 détaillé auparavant en fonction de la profondeur, au niveau du canal et sous la grille 3. Le diagramme de la figure 4 illustre également en pointillés la bande de valence en fonction de la profondeur sous la grille 3. La figure 4 illustre également en trait discontinu la densité d’électrons en fonction de la profondeur sous la grille, en l’absence de différence de potentiel Vgs. La densité d’électrons sous la grille 3 est ainsi extrêmement réduite (au maximum de 5,5 e'6cnr2).
    Par application d’une différence de potentiel Vgs supérieure à Vth, on peut obtenir un canal conducteur par apparition d’une couche d’accumulation d’électrons dans la couche 15 sous l’isolant de grille 32.
    La tension de seuil Vth peut se calculer par la formule suivante :
    Avec <pMS la différence de travail de sortie entre la couche de GaN 15 et le matériau conducteur de grille 31, d’une valeur d’environ 1eV dans le cas présent. Cette contribution φΜ5 à la tension de seuil peut s’exprimer comme la déplétion par la grille.
    Le second terme correspond à l’effet du potentiel de diffusion Vbi sur la jonction P/N. Le troisième terme correspond à la charge d’espace positive développée dans la couche 15 sous la grille 3.
    On conçoit par ailleurs que la tension de seuil Vth est d’autant plus élevée que la valeur Wn (épaisseur de la couche 15 sous la grille 3) est faible. Avec Wn« WnO, le troisième terme devient quasiment négligeable par rapport au second terme.
    On voit aussi que dans la formule de Vth approximée, le coefficient de pondération du Vbi est le rapport des épaisseurs effectives de l’oxyde et de la couche n 15.
    Dans le cas particulier du AI2O3 choisi comme isolant de grille 32, avec tox>Wn, on obtient un décalage de tension de seuil d’au moins 3,1V. Donc Vth>ç>M5 + 3,1V
    Par conséquent, on peut aisément obtenir une valeur Vth supérieure à 3V. La valeur de Vth peut aisément être ajustée industriellement en choisissant par exemple des valeurs appropriées de Wn et tox.
    Les zones d’accès au canal côté source et drain sont formées par la couche de gaz d’électron 18 et présentent une résistance à l’état passant réduite. La concentration et surtout la mobilité effective des électrons dans le canal lorsque Vgs > Vth restent inférieures à celles des électrons dans la couche de gaz d’électrons 18 au niveau des accès. Par conséquent, pour réduire autant que possible la résistance Ron du transistor à l’état passant, il est souhaitable de réduire la longueur de grille autant que possible par rapport à la distance drain-source Lds. Par exemple, pour des applications où Lds est de l’ordre de 20pm, il est souhaitable d’utiliser une longueur de grille Lg inférieure à 1pm.
    Pour calculer la résistance à l’état passant du transistor, on prend en compte une longueur de grille effective Lgeff, définie approximativement comme la longueur Lg de la grille de commande 3 augmentée des zones de transition côté source et drain, soit Lgeff « Lg+ 2Wt. La longueur de grille Lg sera moins contrainte pour des applications à haute tension (par exemple des tensions supérieures à 600V).
    Pour conserver une résistance de canal faible à l’état passant, on respectera de préférence la relation suivante :
    Pour des valeurs courantes de Nsc et pc, on peut déduire la condition Lgeff < 1pm et donc Lg < 0,8pm. On pourra par exemple choisir une valeur Lg comprise entre 0,25 et 0,5pm. On conserve de préférence une valeur Lg au moins égale à 0,25, tox devant être suffisamment élevée pour conserver une plage de variation de Vgs de +/-15V ou +/-20V, similaire à ce qui est obtenu avec une grille pour un transistor de type Silicium.
    Au niveau des accès, la capacité à tenir la tension en mode bloqué est élevée, grâce au champ électrique critique élevé du matériau du GaN.
    La barrière de potentiel formée entre la couche de gaz d’électrons 18 et la couche tampon 13 (empêchant l’injection et le piégeage des électrons dans les couches profondes de la couche tampon 13) atteint un niveau élevé et apparaît grâce au potentiel de diffusion Vbi, et inclut : -en partie une barrière de potentiel aux bornes de la jonction P/N déplétée formée entre les couches 14 et 15 :
    -en partie une barrière de potentiel aux bornes de la couche GaN 16 :
    Dans la zone de charge d’espace de la jonction p/n, toutes les accepteurs et donneurs sont ionisés et c’est donc leur concentration totale qui intervient dans les calculs (cad Na et Nd).
    Avec Wnepi =80nm et Wp = 50nm et Na = 1 e17cnrr3, on obtient une barrière de potentiel d’environ 1,3eV dont 0,9eV aux bornes de la jonction et 0,3eV aux bornes de la couche 16.
    La barrière de potentiel obtenue par la combinaison des couches 14 et 15 atteint un niveau plus élevé que celui d’une éventuelle couche d’AIGaN qui serait placée sous la couche 16 de formation du gaz d’électrons (comme l’exemple détaillé dans ‘Characteristics of AIGaN/GaN/AIGaN double heterojunction HEMTs with an improved breakdown voltage’ cité en introduction).
    On fournit par la suite des exemples de règles de conception d’un tel transistor 1.
    Lorsque le dopant de la couche 14 est du Magnésium les limites extrêmes pour Na sont fixée par : - les capacités de la technologie d’épitaxie à incorporer et activer le Magnésium dans la couche 14 de GaN (en prenant en compte une limite de solubilité et la passivation par des complexes de type Mg-H notamment). La valeur maximale utilisable pour Na est à ce jour a priori de 1e19cnr3 - La valeur nécessaire pour avoir un Vbi>3V, soit NA>3e16cnr3
    On peut théoriquement concevoir un transistor 1 selon l’invention dans cette plage de valeurs. En pratique, on utilisera avantageusement une concentration 1e17cnrr3 < Na < 1e18cnrr3. NA>1e17cnv3 permet d’obtenir une barrière de potentiel enterrée (Back Barrier en langue anglaise) significative (>1.3V) et Na < 1 e18cnrr3 permet d’obtenir une épaisseur robuste pour la couche p 14 (Wp>15nm).
    Pour la couche 15, on peut sélectionner par exemple une valeur Nd comprise entre 2e16cnrr3 (pour NA=1e17cnrr3) et 2e17cnv3 (pour Na=1 e18cnv3). La valeur maximale de Nd est par exemple limitée par la perte de mobilité des électrons du canal qui détériorerait alors Ron, en particulier si Nd > 2e17cnrr3. La valeur minimale de Nd est déterminée par la valeur de Na : Plus Na est grand, plus Nd doit être grand, sinon WpO (et donc Wp) est trop faible pour permettre la formation de la couche p-GaN 14. Les courbes WpO et WnO en fonction de Nd pour les valeurs extrêmes de Na synthétisent cet aspect (comme illustré aux figures 8 et 9). Une fois Na choisi, la zone en pointillé délimite les possibilités pour Nd.
    Exemplel : si NA =1 e17 on peut choisir ND entre 2e16 et 1 e17. On choisira 2e16 si on veut privilégier la mobilité dans le canal.
    Exemple 2 : si NA =1 e18 on peut choisir ND =2e17 pour éviter une valeur de Wp trop petite.
    La valeur minimale de Nd est aussi définie par la capacité de réalisation de faibles dopages de type N dans du GaN, et par la diminution de la valeur φΜ5 (et donc de la valeur Vth) si Nd est trop faible. Donc, de préférence, Nd > 2e16cnrr3.
    On peut ensuite calculer le potentiel de diffusion Vbi selon la relation détaillée précédemment. On peut alors calculer une épaisseur correspondante WnO de déplétion totale dans une couche GaN-n 15 de dopage Nd (par exemple 375 nm avec des paramètres détaillés auparavant) et une épaisseur correspondante WpO de déplétion totale dans une couche GaN-p 14 (par exemple 75nm avec des paramètres détaillés auparavant et la relation suivante).
    On peut ensuite déterminer les épaisseurs du canal et des couches GaN 15 et GaN 14 à réaliser pour que ceux-ci soient complètement dépiétés, en respectant seulement les inégalités suivantes :
    WnO £ Wnepi ;
    WnO > Wn ; et
    WpO > Wp
    La couche de GaN 14 est avantageusement complètement déplétée, pour éviter de conserver une couche conductrice de trous qui empêcherait le champ électrique de se développer dans l’épaisseur de la couche de GaN 13, ce qui induirait une forte dégradation de la tenue en tension du transistor.
    Avec Vbi = 3V, Na = 1 * 1017 cm'3 et Nd = 2 * 1016 cm'3, on obtient une valeur de Wpo de 75nm. On utilise avantageusement une valeur Wp suffisamment élevée pour pouvoir être réalisée par épitaxie avec robustesse (par exemple Wp > 15nm). Une diminution de la valeur Wp abaisse le niveau de la barrière de potentiel. Par contre, une diminution de la valeur Wp garantit la déplétion de la couche de GaN 14. Avantageusement, Wp est compris entre 30 et 50nm, et de préférence égal à 50nm.
    Au niveau des accès, l’épaisseur de la couche de GaN 15 est définie comme Wnepi. Les règles de dimensionnement suivantes visent à dépléter complètement la couche de GaN 15, que ce soit au niveau des accès ou du canal. Par simplification, on pourra considérer que l’épaisseur de la couche de GaN 15 correspond à son épaisseur au niveau des accès.
    Avantageusement, Wnepi > 0,2 * WnO ou Wnepi > 75nm, afin d’éviter que la déplétion n’ait un impact sur la couche de gaz d’électrons 18. En effet, la couche 15 doit absorber une proportion non négligeable du potentiel de diffusion Vbi. Une épaisseur Wnepi suffisamment élevée est en outre utilisée pour que la barrière de potentiel générée par la jonction soit suffisante pour empêcher l’injection d’électrons avec une charge d’espace suffisante développée dans la couche 15. Par ailleurs, pour permettre une gravure de la cavité de la grille 3 dans la couche 15 avec suffisamment de marge, on vérifie de préférence l’inégalité Wnepi > Wn + 20nm. Une valeur Wnepi de 80 nm est par exemple satisfaisante.
    Par ailleurs, il est souhaitable de limiter la résistance des zones de transition entre la couche de gaz d’électrons 18 et le canal. Pour éviter d’augmenter la longueur de grille effective, l’épaisseur Wnepi est avantageusement minimisée.
    Avantageusement, Wn est très inférieur à WnO (par exemple WnO > 4* Wn), de sorte que le canal dans la couche de GaN 15 soit complètement dépiété sous les électrodes du transistor 1 et de sorte que la tension de seuil Vth détaillée auparavant ne soit pas dégradée. Par exemple, pour une valeur WnO de 373nm, on peut choisir une valeur Wn inférieure à 93nm. Par ailleurs, si les permittivités de l’isolant 32 et du GaN sont proches, pour obtenir un Vth élevé, il est souhaitable de respecter la relation 50nm > tox > Wn. Par exemple, on peut choisir la valeur Wn entre 20 et 50nm. Une valeur de 40nm s’avère par exemple appropriée. La valeur minimale de Wn est par exemple définie par des contraintes de procédé de fabrication. Ainsi, pour graver la couche 17 d’AIGaN, la couche 16 de GaN et une partie de la couche 15 de GaN, il faut envisager une gravure d’environ 150nm pour ménager la cavité de la grille 3. En l’absence de couche d’arrêt, il est préférable de conserver un canal d’une épaisseur Wn d’au moins 20 nm pour tenir compte de l’imprécision sur la profondeur de la gravure. La valeur minimale de Wn est également fixée par la valeur maximale de Vth. Comme Vth est dépendant du rapport tox/Wn, avec une valeur maximale de Vth de 6V et une valeur plafonnée de tox, on en déduit que Wn doit par exemple être au moins égal à 20nm.
    La profondeur d’implantation Wt de la grille 3 dans la couche 15 est de préférence non nulle, avantageusement d’au moins 20nm, voire d’au moins 30nm. Une profondeur d’implantation de 40 nm s’avère par exemple appropriée.
    Pour une valeur de Vth souhaitée, en ayant défini les valeurs Wn et φΜ5, on peut déduire la valeur tox pour la couche d’isolant 32, à partir de la relation fournie précédemment pour Vth. L’épaisseur de la couche 16 est avantageusement suffisamment épaisse pour éviter toute perturbation de la couche de gaz d’électrons 18 au niveau des électrodes du transistor 1 par l’influence chimique (le dépôt de la couche dopée au Magnésium induisant un effet mémoire du Magnésium dans les couches déposées par la suite par épitaxie) et électrique des dopants des couches 14 et 15. Ainsi, avantageusement, 60 nm > Wnid ^ 20nm (par exemple obtenu avec Wnepi=80nm et Wnepi+Wnid > 10Onm pour limiter l’influence du magnésium sur la couche de gaz d’électrons 18). Pour limiter la résistivité des zones de transition entre le gaz d’électrons 18 et le canal, avantageusement, on respecte l’inégalité 100nm > Wnepi -Wn -i-Wnid.
    Avantageusement, Wnid = 50nm.
    Les couches 12 à 18 peuvent être formées successivement dans une même machine d’épitaxie en phase vapeur (MOCVD), en changeant bien entendu les conditions d’épitaxie pour chacune des couches. Les paramètres d’épitaxie pour la formation de chacune des couches sont connus en soi de l’homme du métier. L’épaisseur tox peut être limitée par le procédé de fabrication de l’isolant 32. Par exemple, une couche d’Al203 déposée par une technique ALD (pour Atomic Layer Déposition en langue anglaise) est délicate à réaliser sur une épaisseur dépassant 50nm. L’épaisseur tox minimale est imposée par la tenue en tension de la grille 3 à l’état passant et à l’état bloqué. Pour un isolant 32 en AI2O3, une épaisseur tox au moins égale à 40nm peut s’avérer nécessaire pour des tensions au moins égales à 600V et une plage de variation de Vgs de +/-20V. Une valeur tox de 40 nm s’avère généralement appropriée pour de ΓΑΙ2Ο3. D’autres matériaux pour l’isolant de grille 92 peuvent être utilisés, par exemple (et non limitativement) du SiN, du Si02, du AIN, un AlOxN ou du HfC>2.
    Pour obtenir une valeur de Vth maximale, on peut utiliser un métal comme matériau conducteur 31 présentant un travail de sortie élevé, par exemple du Ni. D’autres métaux compatibles avec les technologies CMOS peuvent également être utilisés, dont des exemples non exhaustifs sont le W, le Ti, le polysilicium dopé P+ ou le TiN. On peut également envisager une grille en diamant p+ avec un contact ohmique sur le diamant réalisé à partir de Ti recuit, pour obtenir une valeur <pMS particulièrement élevée.
    La figure 5 est une vue en coupe schématique d’une variante de transistor 1 destinée à accroître sa tenue en tension. Cette variante s’avère particulièrement appropriée lorsque la longueur de grille est réduite, par exemple inférieure à 0,5pm. Cette variante inclut une grille de commande 3 comprenant une électrode de champ ou FPG (pour Field Plate Gâte).
    La grille 3 du transistor 1 comporte ici un débordement latéral 33 au-dessus de la couche 17 (et en l’occurrence au-dessus des couches 19 et 20). Ce débordement latéral s’étend d’environ une longueur fpg par rapport à la cavité de la grille 3. Ainsi, le matériau conducteur de grille 31 et l’isolant de grille 32 s’étendent latéralement d’une longueur fpg par rapport à la cavité de la grille 3. La géométrie de l’électrode de champ est avantageusement optimisée (longueur, hauteur) de façon connue en soi de l’homme du métier afin de réduire le pic de champ électrique au pied de la grille.
    La figure 6 est une vue en coupe schématique d'une structure cascode 4 incluant un transistor de type normalement bloqué selon l'invention. La figure 7 est un schéma électrique équivalent de cette structure cascode 4. Une telle structure s'avère également particulièrement appropriée pour un transistor de type normalement bloqué dont la longueur de grille est réduite dans la cavité traversant la couche de gaz électrons, par exemple inférieure à 0,2 pm. Une telle structure cascode 4 permet d'accroître la tenue en tension malgré l'utilisation d'un transistor normalement bloqué à grille courte.
    La structure cascode 4 inclut des transistors 41 et 42 à heterojonction à haute mobilité électronique connectés en série. Le transistor 41 est de type normalement bloqué, le transistor 42 étant de type normalement passant. La grille de commande 415 du transistor 41 est pilotée de façon connue en soi par un circuit de commande 7, par l'intermédiaire d'une connexion non illustrée à la figure 6. La source 51 du transistor 41 est connectée à la grille de commande 425 du transistor 42. Le drain 52 du transistor 42 constitue une électrode de sortie de la structure cascode 4.
    La couche 20 est recouverte d'une couche d'isolant 23. Cette couche 23 est par exemple réalisée en oxyde de silicium et peut par exemple présenter une épaisseur d'environ 400 nm.
    La grille de commande 415 est notamment formée dans une cavité traversant les couches 16 et 17, et s'étendant jusque dans la couche 15. La cavité est recouverte d'une couche d'isolant 412 et remplie par un matériau conducteur de grille 411. La grille 415 traverse par ailleurs la couche d'isolant 23.
    La grille 415 du transistor 41 comporte ici un débordement latéral 413 au-dessus de la couche 17 (et en l'occurrence au-dessus des couches 19 et 20). La grille de commande 415 comprend ainsi une électrode de champ ou FPG (pour Field Plate Gâte). Ce débordement latéral 413 s’étend d’environ une longueur fpg par rapport à la cavité de la grille 415. Ainsi, le matériau conducteur de grille 411 et l’isolant de grille 412 s’étendent latéralement d’une longueur fpg par rapport à la cavité de la grille 415. La géométrie de l’électrode de champ est avantageusement optimisée (longueur, hauteur) de façon connue en soi de l’homme du métier afin de réduire le pic de champ électrique au pied de la grille. Comme dans l'exemple illustré à la figure 5, le matériau conducteur de grille 411 et l'isolant de grille 412 s'étendent latéralement par rapport à la cavité de la grille 415.
    La grille 415 comporte en outre un débordement latéral 414 au-dessus de la couche 23. Le matériau conducteur 411 et l'isolant 412 s'étendent latéralement par rapport au débordement 413.
    La grille de commande 425 est formée dans une cavité traversant la couche 23 et s'étendant jusqu'à la couche 20. La cavité est recouverte d'une couche d'isolant 422 et remplie par un matériau conducteur de grille 421. La combinaison de l'isolant de grille 422 et de la couche 20 présente ici un fond en contact avec la couche 19. La grille 425 comporte un débordement latéral 424 au-dessus de la couche 23. Le matériau conducteur 421 et l'isolant 422 s'étendent latéralement par rapport à la cavité de la grille 425. Les grilles 415 et 425 sont ici recouvertes d'une couche d'isolant 24. Cette couche d'isolant 24 présente par exemple une épaisseur de 200 nm et peut par exemple être réalisée en oxyde de silicium. Du métal d'interconnexion 25 connecte ici la grille de commande 425 à la source 51.
    Les grilles 415 et 425 sont réalisées sans étape supplémentaire dans le procédé de fabrication du transistor 1, ce qui est intéressant pour son coût de fabrication.
    Le drain du transistor 41 et la source du transistor 42 sont avantageusement confondus, leur connexion étant réalisée dans la couche de gaz d'électrons 18. La structure cascode 4 obtenue est ainsi particulièrement compacte et présente une résistance à l'état passant relativement réduite. Le drain du transistor 41 et la source du transistor 42 forment un nœud flottant.
    The invention relates to electron mobility high-mobility transistors based on the presence of heterojunctions, and in particular HEMT transistors of normally-blocked type.
    Numerous electronic applications now require performance improvements, especially in on-board electronics for the automotive and land transport industries, in aeronautics, in medical systems or in home automation solutions, for example. Most of these applications require high power switches operating in frequency ranges frequently greater than megahertz.
    Historically, power switches have long relied on field effect transistors based on a semiconductor channel, most often silicon. For lower frequencies, junction transistors are preferred because they support higher current densities. However, because of the relatively limited breakdown voltage of each of these transistors, the power applications require the use of a large number of series transistors, or longer transistors, which results in a higher throughput resistance. high. The losses through these series transistors are considerable, both in steady state and in commutation.
    An alternative for power switches, particularly at high frequencies, is the use of high electron mobility field effect transistors, also referred to as heterostructure field effect transistors. Such a transistor includes the superposition of two semiconductor layers having different forbidden bands and have a polarization which leads to the formation of a bidimensional electron gas with high mobility and high density. For reasons of resistance to high voltage and temperature, these transistors are manufactured using type III-N semiconductor materials, wide bandgap.
    For certain applications, in particular safety applications for isolating a circuit in the event of a malfunction of a control system, normally-blocked type HEMT transistors are used, that is to say that their threshold voltage of switching to the on state is positive, so that the transistor remains blocked in the absence of a control signal.
    Because of the inherently conductive nature of the electron gas layer formed between a source and a drain, it is technologically easier to provide a normally-passed heterojunction transistor.
    However, several manufacturing processes have been developed to form normally open or normally blocked heterojunction transistors.
    It is known to produce Schottky type control gates for heterojunction transistors of normally blocked type. However, such transistors are unsuitable for power electronics due to current leakage levels between gate and drain and due to the sensitivity of the current / voltage curve to temperature. Various manufacturing methods have also been developed for producing MIS type grids for heterojunction transistors of normally blocked type. This structure also makes it possible to control the gate in positive and in negative to remain compatible with the control electronics used for the silicon power components.
    According to one approach, a binary type III nitride binary layer and a ternary type III nitride layer are superimposed to form a layer of electron gas at the interface between these nitrides. A recess is made by etching in the ternary nitride layer in order to locally reduce the thickness of this ternary layer. When the local thickness of the ternary layer of nitride is sufficiently low, for example from 2 to 3 nm for AIGaN, the electron gas disappears at the recess. Then, the grid is formed at the recess.
    The process of etching the recess is still insufficiently controlled to ensure a satisfactory thickness of the ternary nitride layer in the recess.
    According to an alternative described in particular in the document 'over 100A operation normally-off AIGaN / GaN hybrid MOS-HFET on Si substrate with high-breakdown voltage' by Hiroshi Kambayashi et al., Published in 'Solid-State Electronics', Volume 54, number 6, in June 2010, pages 660-664, the etching is carried out up to the nitride binary layer. Such a structure makes it possible to obtain a threshold voltage greater than 3V. Such a structure, on the other hand, has the disadvantage of locally having a MOSFET type operation with a density and, above all, a mobility of degraded charges, and therefore a resistance in the raised state. The invention aims to solve one or more of these disadvantages. The invention thus relates to a normally-blocked type high-mobility electronic field effect transistor comprising: a first Ga-doped GaN layer; a second N-type doped GaN layer formed on the first GaN layer so as to form a depleted p / n junction; a third layer of GaN unintentionally doped and formed on the second layer of GaN; a semiconductor layer formed perpendicular to the third layer of GaN unintentionally doped to form a layer of electron gases; a cavity formed through said third GaN layer, and extending to the second GaN layer without reaching the bottom of this second GaN layer; a gate including a conductive gate material and a gate insulator layer disposed in said cavity, said gate insulator layer electrically insulating said conductive gate material with respect to said second and third GaN layers.
    Alternatively, said first GaN layer is formed on a fourth GaN layer having a higher carbon concentration than the first and second GaN layers.
    According to a variant, which first GaN layer includes magnesium forming a P-type dopant.
    According to another variant, the activated magnesium concentration in the first layer of GaN is at least 1 * 1017 cm-3 and / or at most equal to 1 * 1018 cm-3.
    According to yet another variant, said first layer of GaN has a thickness of between 10 and 50 nm.
    Alternatively, the second layer of GaN includes silicon forming an N-type dopant.
    According to another variant, the concentration of silicon in the second GaN layer is at least 2 * 1016 cm 3 and / or at most equal to 2 * 10 17 cm 3.
    According to another variant, said second layer of GaN has a thickness of between 50 and 100 nm.
    According to yet another variant, the concentration of N-type dopants in the second GaN layer is less than the concentration of P-type dopants in the first GaN layer.
    According to a variant, said third layer has a dopant concentration at least two times lower than the dopant concentration of the second GaN layer.
    According to another variant, said third layer has a thickness of between 20 and 60 nm.
    According to another variant, said gate insulator layer has a thickness of at least 20 nm.
    According to yet another variant, said cavity extends in the second layer of GaN to a depth of at least 20 nm.
    According to one variant, the thickness of a channel formed in the second GaN layer between said cavity and the first GaN layer is at least 20 nm.
    According to another variant, said semiconductor layer includes a type III-N alloy.
    According to yet another variant, said grid has a length at most 0.8pm.
    According to a variant, said grid has an overflow with respect to said cavity, the overflow extending vertically above said semiconductor layer. Other features and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the accompanying drawings, in which: FIG. 1 is a sectional view of FIG. an example of a transistor has been rojo notion high electron mobility according to the invention; FIGS. 2 and 3 are conduction band diagrams of a transistor according to the invention and a transistor according to the state of the art; FIG. 4 is a diagram illustrating an electron density, a conduction band and a valence band under the gate of an example transistor according to the invention; FIG 5 is a sectional view of a variant of a transistor according to the invention; FIG. 6 is a sectional view of a cascode structure including a transistor according to the invention; FIG. 7 is an equivalent electrical diagram of the cascode structure of FIG. 6; FIGS. 8 and 9 illustrate thickness values of certain layers as a function of their dopant concentrations.
    FIG. 1 is a diagrammatic sectional view of an example of a normally-blocked type high mobility electron heterojunction transistor according to one embodiment of the invention. The transistor 1 comprises a substrate 11, a nucleation layer 12 disposed on the substrate 11, a GaN buffer layer 13 disposed on the nucleation layer 12, a P-doped GaN layer 14 disposed on the GaN 13 buffer layer, a N-doped GaN layer 15 disposed on the GaN layer 14, and a non-intentionally doped GaN layer 16 disposed on the layer 15. The transistor 1 further comprises a layer of AIGaN 17 disposed on the layer 16. A gas of Electrons are inherently heterojunctional at the interface between layer 17 and layer 16. For the sake of readability, the electron gas is illustrated as a layer 18 at the interface between layer 16 and layer 17 An unillustrated interlayer may be interposed between layers 16 and 17, for example to increase the electron density in the electron gas and to improve the confinement of electrons in GaN. Such an intermediate layer is typically extremely thin (for example 1 nm) and can be made of AlN (particularly suitable for the interface between a layer 16 of GaN and a layer 17 of AlGaN).
    In the example illustrated in FIG. 1, the transistor 1 advantageously comprises a layer 19 of GaN formed in a manner known per se on the layer 17. The layer 19 makes it possible to prevent an oxidation of the layer 17 in AIGaN in the present example . The layer 19 has for example a thickness of between 1 and 3 nm. The layer 19 is advantageously covered with a passivation layer 20, for example made of silicon oxide or silicon nitride.
    It is also possible to have a silicon nitride layer 20 on the layer 17, instead of the layer 19, deposited in situ in the frame used for the epitaxial steps, in order to have a SiN / AIGaN interface and a layer SiN of very good quality.
    In a manner known per se, the transistor 1 comprises a source 21, a drain 22 and a control gate 3. The source 21 and the drain 22 are formed on the AIGaN layer 17 and have a linear current-voltage electrical characteristic ( ohmic). The source contact resistance 21 / electron gas layer 18 and the drain contact resistance 22 / electron gas layer 18 are low and typically between 0.5 and 1 Ohm.mm. The source 21, the drain 22 and the control gate 3 are illustrated only schematically, their dimensions and their structures being able to differ strongly from the illustration of FIG.
    A cavity is formed through the AIGaN layer 17 and through the GaN layer 16. The cavity extends into, but does not pass through, the GaN layer. N-doped GaN thus delimits the bottom of this cavity. In the present example, the cavity also passes through layers 19 and 20.
    The control gate 3 includes a gate insulator layer 32 and a conductive gate material 31 (whose output work is advantageously high). The gate insulator 32 electrically insulates the gate conductor 31 from the layers 15, 16 and 17 in particular. The gate insulator 32 covers here the bottom and the side walls of the cavity. The gate insulator 32 is thus in contact with the layer 15 in the bottom of the cavity, and in contact with the layers 15, 16 and 17 at the side walls of the cavity. The gate insulator 31 may for example be made of Al 2 O 3.
    The gate material 31 is disposed in the cavity, in a space not occupied by the gate insulator 32. The gate material is separated from the layers 15, 16 and 17 via the gate insulator 32. The gate material 31 is in contact with the gate insulator 32. The gate material 31 is, for example, metal, including, for example, TiN, W, or Ni (high work output metals).
    The channel will subsequently be designated as the area of the GaN layer 15 in which the conduction is controlled by the gate 3. The accesses of the transistor 1 include the zones between the control gate 3 and the drain 22, and between the control gate 3 and source 21, including the electron gas layer 18. The transistor 1 according to the invention aims to provide an electron gas conduction at the accesses and an operation of the field effect transistor type accumulation at the level of the canal.
    The superposition of the P-doped GaN layer 14 to the N-doped GaN layer 15 makes it possible to form a depleted P / N junction, so as to form a particularly high potential barrier under the electron gas layer. Thus, at the access level, the junction formed makes it possible to confine the electrons in the layer 16 and thus avoid their entrapment in lower layers, in particular the layer 13 which may comprise a large number of traps due to a potential high concentration of carbon.
    The formed P / N junction can be completely depleted with appropriate dopant thicknesses and concentrations in the layers 14 and 15. In addition, such a junction is formed with materials compatible with the unintentionally doped GaN 16 layer for forming the layer of electron gas. Such a junction can be obtained as soon as the layers 14 and 15 are formed by epitaxial growth.
    The N-doped layer 15 makes it possible to separate the design of the accesses and the channel. The layer 15 absorbs the potential Vbi (detailed later) at the ports, and allows the channel to be manufactured independently of the electron gas 18.
    In addition, such a potential barrier makes it possible to avoid the formation of an AIGaN layer under this unintentionally doped GaN layer 16, which makes it possible to limit the mechanical stresses at the interface with this layer of GaN 16.
    Furthermore, under the gate 3, the depletion of the channel-doped GaN N is used, which makes it possible to form a normally-blocked type transistor with a high threshold voltage, easily greater than 3V. As detailed later, the channel-doped GaN of the channel is depleted under the action of the P-doped GaN and the conductive gate material 31. To make the channel conductive, it is necessary to accumulate enough electrons in the channel under the gate 3 , via a potential difference between source and gate greater than the threshold voltage. As detailed below, the threshold voltage Vth of the transistor 1 can be adjusted by playing in particular on various technological parameters. In the conducting state, the electron density and their mobility is greater than those obtained for an inversion channel. Moreover, by dissociating the channel and accesses, it avoids deteriorating the performance of the transistor 1 in the on state.
    The substrate 11 may be an insulator or a semiconductor of intrinsic or doped silicon type, SiC or sapphire (Al 2 O 3 monocrystalline). The substrate 11 may typically have a thickness of the order of 500 μm to 1 mm.
    The nucleation layer 12 deposited on the substrate 11 serves as an intermediate between this substrate and the buffer layer 13 of GaN, to promote epitaxial growth of the buffer layer 13. Such a nucleation layer 12 proves particularly advantageous in case severe misapplication of mesh parameters and CTE (coefficients of thermal expansion or expansion) between the layer 13 and the substrate 11, which could lead to an impossibility of achieving the heterostructure with sufficient quality to manufacture the components. The nucleation layer 12 is, for example, AlN. The nucleation layer 12 has, for example, a thickness of 100 nm.
    The GaN layer 13 is, for example, enriched with carbon in order to increase its electrical resistivity. A carbon enrichment may for example be carried out simultaneously with an epitaxial growth of the layer 13. The layer 13 typically has a thickness of 1 to 15 μm depending on the voltage range targeted for the transistor component 1.
    The P-doped GaN layer 14 has, for example, a thickness of 50 nm and a P dopant concentration of 1 * 1017 cm-3 at 1 * 1018 cm-3. The N-doped GaN layer has, for example, a thickness of 80 nm and a dopant concentration N of 2 * 1016 to 2 * 1017cnv3. The layers 14 and 15 have a carbon concentration lower than that of the layer 13. This concentration is for example of the order of 1016cnv3.
    The unintentionally doped GaN layer 16 has, for example, a thickness of 50 nm. In order to promote maximum electron mobility in the electron gas layer 18, the GaN layer 16 has as little doping as possible. For example, it will be considered that a layer 16 is unintentionally doped if the concentration of N and P dopants is less than 1 * 1016 cm -1. Another criterion for the unintentionally doped layer is that its concentration of N and P dopants is less than the concentration of doped dopants N of the layer 15. The AIGaN layer 17 has for example a thickness of 25 nm.
    In the example illustrated, the barrier layer 17 is formed of AIGaN. According to the invention, any other semiconductor layer may be disposed on the layer 16 of unintentionally doped GaN, if it is adapted to generate an electron gas at their interface. The layer 17 may for example be another ternary alloy of element III nitride. The layer 17 may also be a binary alloy of element III nitride, for example AlN.
    In the example the AIGaN of the layer 17 may comprise a mole fraction of AIN of between 15 and 25%, but other proportions may of course be used.
    Advantageously, the doping of the P-doped layer 14 is carried out with magnesium, a material which can easily be integrated in the layer 14 during a possible formation by epitaxy. In addition, Magnesium can easily be activated (ie play its acceptor function). Advantageously, the doping of the N-doped layer 15 is carried out with silicon, a material which can easily be integrated in the layer 15 during a possible formation by epitaxy.
    FIG. 2 is a conduction band diagram of transistor 1, previously detailed as a function of depth, at the access level. By way of comparison, Figure 3 provides a conduction band diagram of a prior art transistor as a function of depth at the accesses. The transistor of the state of the art taken into account comprises a 25 nm AIGaN layer formed on an unintentionally doped GaN layer with a thickness of 1.40 μm.
    It can be seen that the potential barrier for transistor 1 according to the invention is typically at least equal to 1.3 eV and beyond, depending on the doping concentrations p and n chosen. On the other hand, the potential barrier of the transistor according to the state of the art is approximately 0.15 eV. The transistor 1 according to the invention thus makes it possible to obtain a particularly high potential barrier in order to avoid the injection and consequently the trapping of the electrons of the electron gas layer 18 in the layer 13 for example. Simulations have made it possible to determine that the electron density in the respective electron gas layers of these transistors are substantially equivalent, about 8.5 × 10 12 cm 2 for the transistor of the example of FIG. 8.2 * 1012 cnr2 for the transistor of the example of Figure 2. The electron density of the electron gas layer 18 according to the invention therefore remains particularly high. The influence of various parameters of the layers 14, 15 and 16 on the formation of a potential barrier for the electron gas layer 18 and the GaN layer 16 will be further detailed later.
    In order to anticipate the influence of different parameters on the performance of transistor 1 according to the invention, the following notations will be used later:
    Ns: the density of electrons in the electron gas layer (in cm 2); P2deg: the mobility of electrons in the electron gas layer (in cm2 / Vs);
    Nd: the volume density of donors in the N-doped GaN layer (in cm 3);
    Na: the density of acceptors in the P-doped GaN 14 layer (in cm 3);
    NA: the density density of acceptors in a thick layer of P-doped GaN sufficiently thick to be non-depleted (in cm 3);
    Nd +: the volume density of donors in a thick layer of N-doped GaN sufficiently thick to be non-depleted (in cm '3); ni: the density of intrinsic carriers in a GaN layer at room temperature (in cm 3); RT: the ambient temperature taken into account of 298K; T: the temperature of the substrate in K;
    Ron: the resistance of transistor 1 in the on state;
    Nsc: the electron density in the channel of transistor 1 (in cm 2); pc: the mobility of electrons in the channel (in cm2 / Vs);
    Wn: the thickness of the N-doped GaN layer under the control gate;
    Wnepi: the thickness of the N-doped GaN layer;
    Wnid: the thickness of the GaN layer 16 unintentionally doped;
    Wp: the thickness of the P-doped GaN 14 layer;
    Wt: the thickness of the transition zone between the electron gas layer 18 and the channel portion in the GaN layer 16; tox: the thickness of the gate insulator;
    Vbi: the diffusion potential (referred to as the 'built-in' potential in English) of the P / N junction formed at the interface between layers 14 and 15;
    Vbbpn: the potential barrier across the depleted P / N junction;
    Vbbnid: the potential barrier across the unintentionally doped GaN 16 layer;
    Vbb: the total potential barrier;
    Lg: the length of the control gate 3;
    Lgeff: the length of the control gate 3 increased source and drain side transition zones (Lgeff "Lg + 2Wt);
    Lds: the drain-source distance of transistor 1; εο: the permittivity of the void; esc: the permittivity of GaN; ε0χ: the permittivity of the oxide or gate insulator used;
    k: the Boltzman constant = 1.3806488 E'23 J / K q: the electronic load «1.6 E19 C.
    The behavior of the junction between the layers 14 and 15 will be modeled in the absence of potential difference between the source 21 and the control gate 3. The diffusion potential of the junction between the layers 14 and 15 can be defined as follows:
    With a P doping carried out with magnesium, the ionization energy of the Mg acceptor in GaN is about 180 meV. The ionization is therefore partial at RT temperature. It must therefore be taken into account by the inequality <Na at RT temperature.
    With ni * 1.9 e-10 cm 3 at the temperature of 298K, Vbi takes values of 3.1 +/- 0.1 V for useful values of Nd + and Na '. Vbi remains insensitive to the variations of Na- and Nd + because of the logarithm in the relation. The threshold voltage Vth of transistor 1 (detailed formula below) is therefore relatively insensitive to the concentration of dopants in layers 14 and 15.
    To guarantee the absence of conduction in the channel when the potential difference Vgs between gate and source is zero, it is ensured that the positive charges developed in the GaN layer 15 are insufficient to balance the negative charges developed in the GaN layer 14. This condition can in particular be fulfilled by means of a relatively thin GaN layer 15.
    This condition can for example be expressed by the following inequality, with WnO, the N-doped GaN thickness being able to be depleted by the P-doped GaN 14 layer.
    The diagram of FIG. 4 illustrates in full line the conduction band of the transistor 1 previously detailed as a function of the depth, at the level of the channel and under the gate 3. The diagram of FIG. 4 also shows in dotted lines the valence band in FIG. 3. FIG. 4 also shows in dashed lines the density of electrons as a function of the depth below the gate, in the absence of a potential difference Vgs. The density of electrons under the gate 3 is thus extremely reduced (at most 5.5 e6cnr2).
    By applying a potential difference Vgs greater than Vth, a conductive channel can be obtained by the appearance of an electron accumulation layer in the layer 15 under the gate insulator 32.
    The threshold voltage Vth can be calculated by the following formula:
    With <pMS the difference in output work between the GaN layer 15 and the gate conductive material 31, of a value of about 1eV in the present case. This contribution φΜ5 to the threshold voltage can be expressed as the depletion by the grid.
    The second term corresponds to the effect of the Vbi diffusion potential on the P / N junction. The third term corresponds to the positive space charge developed in the layer 15 under the grid 3.
    It is also conceivable that the threshold voltage Vth is even higher than the value Wn (thickness of the layer 15 under the gate 3) is low. With Wn "WnO, the third term becomes almost negligible compared to the second term.
    It can also be seen that in the approximated Vth formula, the weighting coefficient of the Vbi is the ratio of the effective thicknesses of the oxide and the n-layer 15.
    In the particular case of Al2O3 chosen as gate insulator 32, with tox> Wn, a threshold voltage offset of at least 3.1V is obtained. So Vth>ç> M5 + 3,1V
    Therefore, one can easily obtain a Vth value higher than 3V. The value of Vth can easily be adjusted industrially by choosing for example appropriate values of Wn and tox.
    The source and drain side channel access areas are formed by the electron gas layer 18 and have reduced on-state resistance. The concentration and especially the effective mobility of the electrons in the channel when Vgs> Vth remain lower than those of the electrons in the electron gas layer 18 at the accesses. Therefore, to minimize the resistance Ron of the transistor in the on state, it is desirable to reduce the gate length as much as possible with respect to the drain-source distance Lds. For example, for applications where Lds is of the order of 20pm, it is desirable to use a gate length Lg less than 1pm.
    To calculate the on-state resistance of the transistor, an effective gate length Lgeff, approximately defined as the length Lg of the control gate 3 plus the source and drain side transition regions, is taken into account, ie Lgeff "Lg + 2Wt . The gate length Lg will be less constrained for high voltage applications (eg voltages greater than 600V).
    To maintain a low channel resistance in the on state, the following relationship is preferably respected:
    For current values of Nsc and pc, we can deduce the Lgeff condition <1pm and therefore Lg <0.8pm. For example, a value Lg of between 0.25 and 0.5 μm may be chosen. Preferably a value Lg of at least 0.25 is maintained, the tox to be high enough to maintain a range of Vgs of +/- 15V or +/- 20V, similar to what is obtained with a grid for a Silicon type transistor.
    At the access level, the ability to hold the voltage in blocked mode is high, thanks to the high critical electric field of the GaN material.
    The potential barrier formed between the electron gas layer 18 and the buffer layer 13 (preventing the injection and trapping of the electrons in the deep layers of the buffer layer 13) reaches a high level and appears thanks to the diffusion potential Vbi, and includes: -in part a potential barrier across the depleted P / N junction formed between layers 14 and 15:
    in part, a potential barrier across the GaN 16 layer:
    In the space charge area of the p / n junction, all the acceptors and donors are ionized and it is therefore their total concentration that is involved in the calculations (ie Na and Nd).
    With Wnepi = 80nm and Wp = 50nm and Na = 1 e17cnrr3, a potential barrier of about 1.3eV is obtained, of which 0.9eV at the terminals of the junction and 0.3eV at the terminals of the layer 16.
    The potential barrier obtained by the combination of the layers 14 and 15 reaches a higher level than that of a possible layer of AIGaN which would be placed under the layer 16 for forming the electron gas (as the example detailed in ' Characteristics of AIGaN / GaN / AIGaN double heterojunction HEMTs with an improved breakdown voltage quoted in the introduction).
    Examples of design rules of such a transistor 1 are provided below.
    When the dopant of layer 14 is magnesium the extreme limits for Na are set by: - the capabilities of the epitaxy technology to incorporate and activate magnesium in GaN layer 14 (taking into account a solubility limit and passivation with Mg-H type complexes in particular). The maximum usable value for Na is a priori of 1e19cnr3 - The value needed to have a Vbi> 3V, ie NA> 3e16cnr3
    It is theoretically possible to design a transistor 1 according to the invention in this range of values. In practice, it will be advantageous to use a concentration 1e17cnrr3 <Na <1e18cnrr3. NA> 1e17cnv3 allows to obtain a significant buried barrier (Back Barrier in English language) (> 1.3V) and Na <1 e18cnrr3 provides a robust thickness for p-layer 14 (Wp> 15nm).
    For the layer 15, it is possible to select for example a value Nd between 2e16cnrr3 (for NA = 1e17cnrr3) and 2e17cnv3 (for Na = 1 e18cnv3). The maximum value of Nd is for example limited by the loss of mobility of the electrons of the channel which would then deteriorate Ron, in particular if Nd> 2e17cnrr3. The minimum value of Nd is determined by the value of Na: More Na is larger, more Nd must be large, otherwise WpO (and thus Wp) is too weak to allow the formation of the p-GaN layer 14. The WpO curves and WnO versus Nd for the extreme values of Na synthesize this aspect (as shown in Figures 8 and 9). Once Na is chosen, the dotted area delimits the possibilities for Nd.
    Exemplel: if NA = 1 e17 we can choose ND between 2e16 and 1 e17. We will choose 2e16 if we want to favor mobility in the channel.
    Example 2: if NA = 1 e18 we can choose ND = 2e17 to avoid a value of Wp too small.
    The minimum value of Nd is also defined by the capacity to produce low dopings of type N in GaN, and by the decrease of the value φΜ5 (and thus of the value Vth) if Nd is too weak. Therefore, preferably, Nd> 2e16cnrr3.
    The diffusion potential Vbi can then be calculated according to the previously detailed relationship. It is then possible to calculate a corresponding total depletion WnO thickness in a GaN-n Nd doping layer (for example 375 nm with previously detailed parameters) and a corresponding total depletion WpO thickness in a GaN-β layer 14 (for example 75nm with previously detailed parameters and the following relationship).
    We can then determine the thicknesses of the channel and the GaN 15 and GaN 14 layers to achieve so that they are completely depleted, respecting only the following inequalities:
    WnO £ Wnepi;
    WnO>Wn; and
    WpO> Wp
    The GaN layer 14 is advantageously completely depleted, in order to avoid keeping a conductive layer of holes which would prevent the electric field from developing in the thickness of the GaN layer 13, which would induce a strong degradation of the voltage withstand of the transistor.
    With Vbi = 3V, Na = 1 * 1017 cm-3 and Nd = 2 * 1016 cm-3, a Wpo value of 75 nm is obtained. Advantageously, a sufficiently high Wp value is used so that it can be performed by epitaxy with robustness (for example Wp> 15 nm). A decrease in the Wp value lowers the level of the potential barrier. On the other hand, a decrease in the Wp value guarantees the depletion of the GaN layer. Advantageously, Wp is between 30 and 50 nm, and preferably equal to 50 nm.
    At the access level, the thickness of the GaN layer 15 is defined as Wnepi. The following sizing rules aim to completely deplete the GaN layer 15, whether at the access or the channel. For simplicity, it can be considered that the thickness of the GaN layer 15 corresponds to its thickness at the accesses.
    Advantageously, Wnepi> 0.2 * WnO or Wnepi> 75nm, in order to prevent the depletion from having an impact on the electron gas layer 18. Indeed, the layer 15 must absorb a significant proportion of the potential Vbi broadcast. A sufficiently high thickness Wnepi is furthermore used so that the potential barrier generated by the junction is sufficient to prevent the injection of electrons with a sufficient space charge developed in the layer 15. Moreover, to allow an etching of the cavity of the grid 3 in the layer 15 with sufficient margin, the inequality Wnepi> Wn + 20 nm is preferably checked. A Wnepi value of 80 nm is for example satisfactory.
    Furthermore, it is desirable to limit the resistance of the transition zones between the electron gas layer 18 and the channel. To avoid increasing the effective gate length, the thickness Wnepi is advantageously minimized.
    Advantageously, Wn is much smaller than WnO (for example WnO> 4 * Wn), so that the channel in the GaN layer 15 is completely depleted under the electrodes of transistor 1 and so that the threshold voltage Vth previously detailed does not not degraded. For example, for a WnO value of 373nm, a Wn value of less than 93nm can be chosen. On the other hand, if the permittivities of the insulator 32 and the GaN are close, to obtain a high Vth, it is desirable to respect the relation 50nm>tox> Wn. For example, one can choose the value Wn between 20 and 50nm. For example, a value of 40 nm is appropriate. The minimum value of Wn is for example defined by manufacturing process constraints. Thus, in order to etch the AIGaN layer 17, the GaN layer 16 and a part of the GaN layer 15, an etching of about 150 nm must be envisaged to protect the cavity of the grid 3. In the absence of a layer stopping, it is preferable to keep a channel with a thickness Wn of at least 20 nm to take into account the inaccuracy on the depth of the etching. The minimum value of Wn is also set by the maximum value of Vth. Since Vth is dependent on the ratio tox / Wn, with a maximum value of Vth of 6V and a capped value of tox, it follows that Wn must for example be at least 20 nm.
    The implantation depth Wt of the grid 3 in the layer 15 is preferably non-zero, advantageously at least 20 nm, or even at least 30 nm. For example, an implantation depth of 40 nm is appropriate.
    For a value of Vth desired, having defined the values Wn and φΜ5, we can deduce the value tox for the insulating layer 32, from the relationship previously provided for Vth. The thickness of the layer 16 is advantageously sufficiently thick to avoid any disturbance of the electron gas layer 18 at the level of the electrodes of the transistor 1 by the chemical influence (the deposition of the Magnesium-doped layer inducing a memory effect of Magnesium in the layers subsequently deposited by epitaxy) and electrical dopants of the layers 14 and 15. Thus, advantageously, 60 nm> Wnid ^ 20nm (for example obtained with Wnepi = 80nm and Wnepi + Wnid> 10Onm to limit the influence magnesium on the electron gas layer 18). To limit the resistivity of the transition zones between the electron gas 18 and the channel, advantageously, the inequality 100nm> Wnepi -Wn -i-Wnid is respected.
    Advantageously, Wnid = 50nm.
    The layers 12 to 18 can be formed successively in the same vapor phase epitaxy machine (MOCVD), of course changing the epitaxy conditions for each of the layers. The epitaxial parameters for the formation of each of the layers are known to those skilled in the art. The thickness tox may be limited by the manufacturing process of the insulator 32. For example, a layer of Al 2 O 3 deposited by an ALD technique (for Atomic Layer Deposition in English) is tricky to achieve over a thickness exceeding 50 nm. The minimum tox thickness is imposed by the voltage resistance of the gate 3 in the on state and in the off state. For an insulator 32 made of Al2O3, a thickness of at least 40nm may be necessary for voltages at least equal to 600V and a variation range of Vgs of +/- 20V. A toxicity value of 40 nm is generally appropriate for ΓΑΙ2Ο3. Other materials for gate insulator 92 may be used, for example (and not limited to) SiN, SiO 2, AlN, AlOxN or HfC> 2.
    To obtain a maximum value of Vth, a metal can be used as a conductive material 31 having a high output work, for example Ni. Other metals compatible with CMOS technologies can also be used, of which non-exhaustive examples are W, Ti, P + doped polysilicon or TiN. It is also possible to envisage a p + diamond grid with an ohmic contact on the diamond made from annealed Ti, to obtain a value <pMS particularly high.
    FIG. 5 is a schematic sectional view of a variant of transistor 1 intended to increase its voltage withstand. This variant is particularly suitable when the gate length is reduced, for example less than 0.5pm. This variant includes a control gate 3 comprising a field electrode or FPG (for Field Plate Gate).
    The gate 3 of the transistor 1 here comprises a lateral overflow 33 above the layer 17 (and in this case above the layers 19 and 20). This lateral overflow extends about a fpg length with respect to the cavity of the grid 3. Thus, the gate conductive material 31 and the gate insulator 32 extend laterally of a length fpg with respect to the The geometry of the field electrode is advantageously optimized (length, height) in a manner known per se to those skilled in the art in order to reduce the electric field peak at the foot of the gate.
    Figure 6 is a schematic sectional view of a cascode structure 4 including a normally blocked type transistor according to the invention. FIG. 7 is an equivalent electrical diagram of this cascode structure 4. Such a structure is also particularly suitable for a normally blocked type transistor whose gate length is reduced in the cavity passing through the electron gas layer, for example lower at 0.2 pm. Such a cascode structure 4 makes it possible to increase the voltage withstand despite the use of a normally closed transistor with a short gate.
    Cascode structure 4 includes electronically connected high mobility heterojunction transistors 41 and 42 connected in series. Transistor 41 is of normally off type, transistor 42 being of normal type. The control gate 415 of the transistor 41 is controlled in a manner known per se by a control circuit 7, via a connection not shown in FIG. 6. The source 51 of the transistor 41 is connected to the control gate 425 of the transistor 42. The drain 52 of the transistor 42 constitutes an output electrode of the cascode structure 4.
    The layer 20 is covered with an insulating layer 23. This layer 23 is for example made of silicon oxide and may for example have a thickness of about 400 nm.
    The control gate 415 is formed in particular in a cavity passing through the layers 16 and 17, and extending into the layer 15. The cavity is covered with a layer of insulator 412 and filled with a gate-conducting material 411. The gate 415 also passes through the insulating layer 23.
    The gate 415 of the transistor 41 here comprises a lateral overflow 413 above the layer 17 (and in this case above the layers 19 and 20). The control gate 415 thus comprises a field electrode FPG (for Field Plate Gat). This lateral overflow 413 extends about a fpg length relative to the cavity of the grid 415. Thus, the gate conductive material 411 and the gate insulator 412 extend laterally of a length fpg with respect to the cavity of the gate 415. The geometry of the field electrode is advantageously optimized (length, height) in a manner known per se to those skilled in the art in order to reduce the electric field peak at the foot of the gate. As in the example illustrated in FIG. 5, the gate conductive material 411 and the gate insulator 412 extend laterally with respect to the cavity of the gate 415.
    The gate 415 further comprises a lateral overflow 414 above the layer 23. The conductive material 411 and the insulator 412 extend laterally with respect to the overflow 413.
    The control gate 425 is formed in a cavity passing through the layer 23 and extending to the layer 20. The cavity is covered with a layer of insulator 422 and filled with a gate conductive material 421. The combination of the gate insulator 422 and the layer 20 here have a bottom in contact with the layer 19. The gate 425 has a lateral overflow 424 above the layer 23. The conductive material 421 and the insulator 422 extend laterally with respect to the cavity of the gate 425. The gates 415 and 425 are here covered with an insulating layer 24. This insulating layer 24 has for example a thickness of 200 nm and can for example be made of oxide of silicon. Interconnect metal 25 here connects control gate 425 to source 51.
    Grids 415 and 425 are made without any additional step in the manufacturing method of transistor 1, which is interesting for its manufacturing cost.
    The drain of the transistor 41 and the source of the transistor 42 are advantageously merged, their connection being made in the electron gas layer 18. The resulting cascode structure 4 is thus particularly compact and has a relatively reduced on-state resistance. The drain of transistor 41 and the source of transistor 42 form a floating node.
    权利要求:
    Claims (17)
    [1" id="c-fr-0001]
    1. Field effect transistor (1) with high electron mobility of normally blocked type, characterized in that it comprises: a first P-doped GaN layer (14); a second N-type doped GaN layer (15) formed on the first GaN layer so as to form a depleted p / n junction; a third layer of GaN (16) unintentionally doped and formed on the second layer of GaN; a semiconductor layer (17) formed vertically above the third GaN layer unintentionally doped to form an electron gas layer (18); a cavity formed through said third GaN layer and extending to the second GaN layer (15) without reaching the bottom of this second GaN layer; a gate (3) including a conductive gate material (31) and a gate insulator layer (32) disposed in said cavity, said gate insulator layer electrically insulating said conductive gate material (31) relative to said second and third layers of GaN.
    [2" id="c-fr-0002]
    A high electron mobility field effect transistor (1) according to claim 1, wherein said first GaN layer (14) is formed on a fourth layer of GaN (13) having a higher carbon concentration than the first layer of GaN (13). and second layers (14, 15) of GaN.
    [3" id="c-fr-0003]
    The heterojunction transistor according to claim 1 or 2, wherein the first GaN layer (14) includes magnesium forming a P-type dopant.
    [4" id="c-fr-0004]
    The heterojunction transistor according to claim 3, wherein the activated magnesium concentration in the first layer of GaN (14) is at least 1 * 1017 cm-3 and / or at most 1 * 1018 cm-3. .
    [5" id="c-fr-0005]
    A heterojunction transistor according to any one of the preceding claims, wherein said first GaN layer (14) has a thickness of between 10 and 50 nm.
    [6" id="c-fr-0006]
    A heterojunction transistor according to any one of the preceding claims, wherein the second GaN layer (15) includes N-type dopant-forming silicon.
    [7" id="c-fr-0007]
    The heterojunction transistor according to claim 6, wherein the silicon concentration in the second GaN layer (15) is at least 2 * 1016 cm-3 and / or at most 2 * 1017 cm-3.
    [8" id="c-fr-0008]
    8. heterojunction transistor according to any one of the preceding claims, wherein said second layer of GaN (15) has a thickness of between 50 and 100 nm.
    [9" id="c-fr-0009]
    A heterojunction transistor according to any one of the preceding claims, wherein the concentration of N-type dopants in the second GaN layer (15) is less than the concentration of P-type dopants in the first GaN layer (14). ).
    [10" id="c-fr-0010]
    A heterojunction transistor according to any one of the preceding claims, wherein said third layer (16) has a dopant concentration at least two times lower than the dopant concentration of the second GaN layer (15).
    [11" id="c-fr-0011]
    11. heterojunction transistor according to any one of the preceding claims, wherein said third layer (16) has a thickness of between 20 and 60nm.
    [12" id="c-fr-0012]
    A heterojunction transistor according to any one of the preceding claims, wherein said gate insulator layer (32) has a thickness of at least 20 nm.
    [13" id="c-fr-0013]
    A heterojunction transistor according to any one of the preceding claims, wherein said cavity extends in the second GaN layer (15) to a depth of at least 20 nm.
    [14" id="c-fr-0014]
    14. heterojunction transistor according to claim 13, wherein the thickness of a channel formed in the second GaN layer (15) between said cavity and the first layer of GaN (14) is at least 20 nm.
    [15" id="c-fr-0015]
    The heterojunction transistor (1) according to any one of the preceding claims, wherein said semiconductor layer (17) includes a III-N type alloy.
    [16" id="c-fr-0016]
    16. heterojunction transistor according to any one of the preceding claims, wherein said gate (3) has a length at most 0.8pm.
    [17" id="c-fr-0017]
    A heterojunction transistor according to claim 16, wherein said gate (3) has an overflow (33) with respect to said cavity, the overflow extending vertically above said semiconductor layer (17).
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    同族专利:
    公开号 | 公开日
    US20170229567A1|2017-08-10|
    FR3047608B1|2018-04-27|
    JP6967351B2|2021-11-17|
    US10050137B2|2018-08-14|
    JP2017152690A|2017-08-31|
    EP3203527A1|2017-08-09|
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    法律状态:
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    2017-08-11| PLSC| Publication of the preliminary search report|Effective date: 20170811 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1650901|2016-02-04|
    FR1650901A|FR3047608B1|2016-02-04|2016-02-04|HIGH ELECTRONIC MOBILITY HETEROJUNCTION TRANSISTOR OF ENHANCED NORMALLY BLOCK TYPE|FR1650901A| FR3047608B1|2016-02-04|2016-02-04|HIGH ELECTRONIC MOBILITY HETEROJUNCTION TRANSISTOR OF ENHANCED NORMALLY BLOCK TYPE|
    JP2017016437A| JP6967351B2|2016-02-04|2017-02-01|Enhanced Normal Off Type High Electron Mobility Heterojunction Transistor|
    EP17154327.5A| EP3203527A1|2016-02-04|2017-02-02|Heterojunction transistor having high electron mobility of the normally-off type|
    US15/424,000| US10050137B2|2016-02-04|2017-02-03|Enhanced normally-off high electron mobility heterojunction transistor|
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