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    • 专利摘要:
    The invention relates to a high electron mobility heterojunction transistor (1), comprising: a first GaN layer (13); a second P-doped GaN layer (14) formed on the first GaN layer; a third N-type doped GaN layer (15) formed on the second GaN layer so as to form a depleted p / n junction; a fourth layer of GaN (16) unintentionally doped and formed on the third layer of GaN; a semiconductor layer (17) formed vertically above the fourth GaN layer unintentionally doped to form an electron gas layer (18).
    公开号:FR3047607A1
    申请号:FR1650899
    申请日:2016-02-04
    公开日:2017-08-11
    发明作者:Erwan Morvan
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Avec un dopage P réalisé avec du Magnésium, l’énergie d’ionisation de l’accepteur Mg dans le GaN est d’environ 180meV. L’ionisation est donc partielle à la température RT. Il faut donc en tenir compte pour le calcul du Vbi par l’inégalité Na- < Na à la température RT.
    Avec ni = 1.9 e-10 cm-3 à la température RT, ND « Nd+ =1 e16cnv3 (avec un dopage Silicium) et Na- = 1e17cnv3, on obtient Vbi » 3.1 V. Vbi reste peu sensible aux variations de Na- et Nd+ en raison du logarithme dans la relation et de la faible valeur de ni.
    La barrière de potentiel formée entre la couche de gaz d’électrons 18 et la couche tampon 13 (empêchant l’injection et le piégeage des électrons dans les couches profondes de la couche tampon 13) apparaît grâce au potentiel de diffusion Vbi, et inclut : -en partie une barrière de potentiel aux bornes de la jonction P/N formée entre les couches 14 et 15 :
    -en partie une barrière de potentiel aux bornes de la couche GaN 16 :
    Dans la zone de charge d’espace de la jonction p/n, tous les accepteurs et donneurs sont ionisés et c’est donc leur concentration totale qui intervient dans les calculs (Na- =Na et Nd+ =Nd).
    La barrière de potentiel obtenue par la combinaison des couches 14 et 15 atteint un niveau plus élevé que celui d’une éventuelle couche d’AIGaN placée sous la couche 16 de formation du gaz d’électrons (comme l’exemple détaillé dans ‘Characteristics of AIGaN/GaN/AIGaN double heterojunction HEMTs with an improved breakdown voltage’ cité en introduction).
    On peut citer des règles de conception d’un tel transistor 1.
    Lorsque le dopant de la couche 14 est du Magnésium les limites extrêmes pour Na sont fixée par : - les capacités de la technologie d’épitaxie à incorporer et activer le Magnésium dans la couche 14 de GaN (en prenant en compte une limite de solubilité et la passivation par des complexes de type Mg-H notamment). La valeur maximale utilisable pour Na est à ce jour a priori de 1e19cnr3 - La valeur nécessaire pour avoir un Vbi>3V, soit NA>3e16cnrr3
    On peut théoriquement concevoir un transistor 1 selon l’invention dans cette plage de valeurs. En pratique, on utilisera avantageusement une concentration 1e17cnr3 < Na < 1e18cnr3. NA>1e17cnr3 permet d’obtenir une barrière de potentiel enterrée (Back Barrier en langue anglaise) significative (>1.3V) et Na < 1e18cnr3 permet d’obtenir une épaisseur robuste pour la couche p 14 (Wp>15nm).
    Pour la couche 15, on peut sélectionner par exemple une valeur Nd comprise entre 1e17cnr3 et Na, en particulier avec du Si comme dopant.
    On peut ensuite calculer le potentiel de diffusion Vbi selon la relation détaillée précédemment.
    On peut alors calculer une épaisseur correspondante WnO de déplétion totale dans une couche GaN n et une épaisseur correspondante WpO de déplétion totale dans une couche GaN P dans le cas où les couches N et P auraient des épaisseurs supérieures à WnO et WpO, respectivement.
    On peut ensuite déterminer les épaisseurs des couches GaN 15 et GaN 14 à réaliser pour que celles-ci soient complètement déplétées, en respectant seulement les inégalités suivantes :
    WnO > Wn ; et
    WpO > Wp
    La couche de GaN 14 est avantageusement complètement déplétée, pour éviter de conserver une couche conductrice de trous qui empêcherait le champ électrique de se développer dans l’épaisseur de la couche de GaN 13, ce qui induirait une forte dégradation de la tenue en tension du transistor.
    Avec Vbi = 3,1V, Na = 1 * 1018 cm'3 et Nd = 1 * 1018 cm'3, on obtient une valeur de Wpo de 41 nm. On utilise avantageusement une valeur Wp suffisamment élevée pour pouvoir être réalisée par épitaxie avec robustesse (par exemple Wp > 10nm). On peut choisir une valeur Wp de 28nm par exemple. Une diminution de la valeur Wp abaisse le niveau de la barrière de potentiel. Par contre, une diminution de la valeur WP garantit la déplétion de la couche de GaN 14. Avantageusement, Wp est compris entre 30 et 50nm, et de préférence égal à 50nm.
    Pour obtenir une déplétion complète de la couche GaN 15, on vérifie la relation suivante :
    Avec Να=Νο=1θ18οτγ3, Wno =41 nm, on peut choisir une valeur Wn de 28nm par exemple.
    Avantageusement, Wn > 0,2 * WnO ou Wn > 10nm, afin d’éviter que la déplétion n’ait un impact sur la couche de gaz d’électrons 18. En effet, la couche 15 doit absorber une proportion non négligeable du potentiel de diffusion. Une épaisseur Wn suffisamment élevée est en outre utilisée pour que la barrière de potentiel générée par la jonction soit suffisante pour empêcher l’injection d’électrons avec une charge d’espace suffisante développée dans la couche 15. Une valeur Wn de 28 nm est par exemple satisfaisante.
    Avantageusement, WnO est supérieur à Wn (par exemple WnO > Wn), de sorte que la couche de GaN 15 soit complètement déplétée sous les électrodes du transistor 1. Par exemple, pour une valeur WnO de 41 nm, on peut choisir une valeur Wn inférieure à41nm.
    Avec Wn =28nm et Wp = 28nm et Na = Nd =1e18crrr3, on obtient une barrière de potentiel d’environ 1,7eV dont 0,9eV aux bornes de la jonction et 0,3eV aux bornes de la couche 16. L’épaisseur de la couche 16 est avantageusement suffisamment épaisse pour éviter toute perturbation de la couche de gaz d’électrons 18 au niveau des électrodes du transistor par l’influence des dopants des couches 14 et 15. Ainsi, avantageusement, 100 nm > Wnid > 50nm (par exemple obtenu avec Wn=28nm et Wn+Wnid > 78nm pour limiter l’influence du magnésium sur la couche de gaz d’électrons 18). Avantageusement, Wnid = 50nm.
    Les couches 12 à 18 peuvent être formées successivement dans une même machine d’épitaxie en phase vapeur, en changeant bien entendu les conditions d’épitaxie pour chacune des couches. Les paramètres d’épitaxie pour la formation de chacune des couches sont connus en soi de l’homme du métier.
    Dans l’exemple illustré, la couche barrière 17 est formée en AIGaN. Selon l’invention, toute autre couche semiconductrice peut être disposée sur la couche 16 de GaN non intentionnellement dopée, si elle est adaptée pour générer un gaz d’électrons à leur interface. La couche 17 peut par exemple être un autre alliage ternaire de nitrure d'élément III. La couche 17 peut aussi être un alliage binaire de nitrure d’élément III, par exemple du AIN.
    Dans l’exemple l’AIGaN de la couche 17 peut comprendre une concentration en Aluminium comprise entre 6 et 9% mais d’autres proportions d’Aluminium peuvent bien entendu être utilisées.
    Dans les différentes variantes, on peut envisager d’interposer une couche d’AIN entre une couche d’AIGaN 17 et une couche de GaN 16, afin d’augmenter le confinement du gaz d’électrons et sa mobilité. Cette couche d’AIN présente avantageusement une épaisseur comprise entre 5Angstrom et 2nm.
    La couche 17 peut avantageusement être recouverte d’une couche de passivation, afin notamment d’améliorer l’isolation entre les électrodes du transistor 1. La couche de passivation peut par exemple être réalisée en SiN. Une couche de SiN peut être déposée par épitaxie, sans retirer le wafer de l’installation d’épitaxie après la formation des couches 16 et 17.
    The invention relates to high electron mobility transistors based on the presence of heterojunctions, and in particular to heterojunction transistors using semiconductor GaN layers.
    Numerous electronic applications now require performance improvements, especially in on-board electronics for the automotive and land transport industries, in aeronautics, in medical systems or in home automation solutions, for example. Most of these applications require high power switches operating in frequency ranges frequently greater than megahertz.
    Historically, power switches have long relied on field effect transistors based on a semiconductor channel, most often silicon. For lower frequencies, junction transistors are preferred because they support higher current densities. However, because of the relatively limited breakdown voltage of each of these transistors, the power applications require the use of a large number of series transistors, or longer transistors, which results in a higher throughput resistance. high. The losses through these series transistors are considerable, both in steady state and in commutation.
    An alternative for power switches, particularly at high frequencies, is the use of high electron mobility field effect transistors, also referred to as heterostructure field effect transistors. Such a transistor includes the superposition of two semiconductor layers having different forbidden bands which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional gas of electrons. For reasons of resistance to high voltage and temperature, these transistors are chosen so as to have a wide band of forbidden energy.
    Among the broadband HEMT transistors of forbidden energy, the transistors based on gallium nitride are very promising. Their forbidden energy bandwidth induces a higher critical electric field compared to conventional electronic materials, a high carrier saturation rate and good thermal and chemical stability. The breakdown field of the gallium nitride can thus be greater than 2 × 10 6 V / cm, which makes it easy to produce compact transistors with breakdown voltages greater than 600 V. Moreover, such transistors allow very high current densities. because of the very high electron mobility and the high electron density in the electron interface gas.
    The 'Characteristics of AIGaN / GaN / AIGaN dual heterojunction HEMTs with enhanced breakdown voltage' document published in the January 2012 issue, Volume 33, Issue 1 of Journal of Semiconductors, describes a first HEMT transistor structure. This structure comprises an SiC substrate, surmounted by a 100 nm AIN nucleation layer, surmounted by a 1.5 μm GaN buffer layer, surmounted by an AlN intermediate layer of 1 nm, surmounted by a 22 nm AIGaN barrier layer, surmounted by a GaN layer of 1 nm, on which the source, the gate and the drain of the transistor are formed. An electron gas layer is formed at the interface between the GaN buffer layer and the AIGaN barrier layer, the AIN intermediate layer being considered as belonging to this interface.
    In practice, the GaN buffer layer has a relatively low potential barrier, so that electrons in the electron gas layer can easily exit the potential well to be trapped in the GaN buffer layer, for example in the case the transistor is blocked. The conduction performance of the transistor is then strongly degraded because the electron density is reduced.
    It has been proposed to include carbon or magnesium in the buffer layer in a significant proportion in order to limit the output of the potential well by raising the conduction band. However, the electrons actually leaving the potential well are then trapped in the buffer layer where a high concentration of deep level is present.
    The document 'Characteristics of AIGaN / GaN / AIGaN dual heterojunction HEMTs with a improved breakdown voltage' describes a second HEMT transistor structure for forming an electrical barrier between the electron gas layer and the buffer layer, in order to prevent injection of electrons to this buffer layer. This structure comprises an SiC substrate, surmounted by a 100 nm AlN nucleation layer, surmounted by a 1.5 μm Alo, O7Gao, 93N buffer layer surmounted by a GaN channel layer of 10 nm. nm, surmounted by a 1 nm AIN intermediate layer, surmounted by a 22 nm AIGaN barrier layer, surmounted by a GaN layer of 1 nm, on which the source, the gate and the drain of the transistor are trained. An electron gas layer is formed at the interface between the GaN channel layer and the AIGaN barrier layer, the AIN intermediate layer being considered as belonging to this interface. This structure is referred to as HEMT with double heterojunction. The buffer layer is used to record the energy of the conduction band and confines the electrons in the channel layer.
    However, such a structure still has an insufficient electrical barrier. In addition, the presence of the barrier layer in AIGaN induces additional mechanical stresses in the structure of the transistor. The invention aims to solve one or more of these disadvantages. The invention thus relates to a heterojunction transistor with high electronic mobility, comprising: a first layer of GaN; a second Ga-doped GaN layer formed on the first GaN layer; a third N-type doped GaN layer formed on the second GaN layer so as to form a depleted p / n junction; a fourth layer of GaN unintentionally doped and formed on the third layer of GaN; a semiconductor layer formed perpendicular to the fourth layer of GaN unintentionally doped to form a layer of electron gas. The invention also relates to the following variants. Those skilled in the art will understand that each of the features of the following variants may be independently combined with the above features, without necessarily constituting an intermediate generalization.
    According to one variant, the second GaN layer includes magnesium forming a P-type dopant.
    According to another variant, the magnesium concentration in the second layer of GaN is at least 5 * 1016 cm-3.
    According to another variant, the magnesium concentration in the second layer of GaN is at most equal to 2 * 1018 cm-3.
    According to yet another variant, said second layer of GaN has a thickness of between 20 and 50 nm.
    According to one variant, the third layer of GaN includes silicon forming an N-type dopant.
    According to another variant, the concentration of silicon in the third layer of GaN is at least 1.5 * 1016 cm-3.
    According to yet another variant, the concentration of silicon in the third layer of GaN is at most equal to 2 * 1018 cm-3.
    According to another variant, said third layer of GaN has a thickness of between 10 and 100 nm.
    According to yet another variant, said fourth layer has a dopant concentration of less than 1 * 1016 cm-3.
    According to a variant, said fourth layer has a thickness of between 50 and 100 nm.
    According to another variant, said first GaN layer has a higher carbon concentration than the second and third GaN layers.
    According to another variant, said semiconductor layer includes AIGaN.
    According to yet another variant, the transistor comprises another semiconductor layer having a thickness of between 0.5 and 2 nm arranged between the fourth GaN layer and said semiconductor layer formed in line with the fourth GaN layer, this other layer semiconductor being an alloy having a common component with GaN and another common component with said semiconductor layer formed in line with the fourth GaN layer. Other features and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the accompanying drawings, in which: FIG. 1 is a sectional view of FIG. an example of heterojunction transistor with high electron mobility according to the invention; FIGS. 2 and 3 are conduction band diagrams of a transistor according to the invention and a transistor according to the state of the art; FIG. 4 is a sectional view of an example of another variant of heterojunction transistor with high electronic mobility according to the invention.
    FIG. 1 is a schematic sectional view of an example of a heterojunction transistor with high electronic mobility according to one embodiment of the invention. The transistor 1 comprises a substrate 11, an intermediate layer 12 disposed on the substrate 11, a GaN buffer layer 13 disposed on the intermediate layer 12, a P-doped GaN layer 14 disposed on the GaN buffer layer 13, a layer of N-doped GaN 15 disposed on the GaN layer 14, and a non-intentionally doped GaN layer 16 disposed on the layer 15. The transistor 1 further comprises a layer of AIGaN 17 disposed on the layer 16. An electron gas is intrinsically formed by heterojunction at the interface between the layer 17 and the layer 16. For the sake of readability, the electron gas is illustrated as a layer 18 at the interface between the layer 16 and the layer 17. intermediate layer not shown may be interposed between the layers 16 and 17, for example to increase the electron density and mobility in the electron gas. Such an intermediate layer is typically extremely thin (for example 1 nm) and may be made of AlN (particularly suitable for the interface between a layer 16 made of GaN and a layer 17 made of AlGaN).
    In a manner known per se, the transistor 1 comprises a source 21, a drain 22 and a control gate 23 formed on the AIGaN layer 17. The source 21, the drain 22 and the control gate 23 are illustrated only schematically, their dimensions and structures may differ greatly from the illustration in Figure 1.
    The substrate 11 may be an insulator or semiconductor of the intrinsic or doped silicon type, or of SiC or sapphire. The substrate 11 may typically have a thickness of the order of 650 μm to 1 mm.
    The intermediate layer 12 (which may be formed of a superposition of transition layers) is deposited on the substrate 11. The transition layer 12 makes it possible to adapt the crystal mesh parameters between the layers 11 and 13 of GaN. This makes it possible to manage the mechanical stresses between the substrate 11 and an active part of layers formed by the epitaxy. The layer 12 may include the superposition of a nucleation layer (typically ΓΑΙΝ with a thickness of about 100 nm) and several adaptation layers (for example, several layers of AIGaN with a decreasing molar fraction of AlN, or a superlattice comprising several AlxGa (1-x) N / GaN bilayers.
    Such an intermediate layer 12 proves particularly advantageous in the event of strong maladjustment of mesh parameters between the layer 13 and the substrate 11, which could lead to mechanical dislocations in these layers.
    The buffer layer 13 may have a thickness dependent on the target voltage for the transistor 1, for example a thickness of a few microns. A relatively large thickness of the buffer layer 13 limits the lateral and vertical leakage currents in the transistor 1 and also better confines the electron gas layer 18. The buffer layer 13 may for example be made of GaN-Si (Semi-insulating) doped with carbon or in the superposition of a layer of GaN-Si / AlxGa (1-x) N with weak x, for example between 4 to 8%.
    The P-doped GaN layer 14 has, for example, a thickness of 50 nm and a Na acceptor concentration of 1017 cm 3. The N-doped GaN layer 15 has, for example, a thickness of 80 nm and a concentration of Nd donors of 2 * 1016 cm-3. The layers 14 and 15 have a carbon concentration lower than that of the layer 13. This carbon concentration is, for example, less than 1 * 1016 cm-3.
    The unintentionally doped GaN layer 16 has, for example, a thickness of 50 nm. In order to promote maximum electron mobility in the electron gas layer 18, the GaN layer 16 has as little doping as possible. For example, it will be considered that a layer 16 is unintentionally doped if the concentration of N and P dopants is less than 1 * 1016 cm 3. The AIGaN layer 17 has, for example, a thickness of 25 nm.
    Advantageously, the doping of the P-doped layer 14 is carried out with magnesium, a chemical element which can easily be integrated into the layer 14 during a possible formation by epitaxy. In addition, Magnesium can easily be activated. Advantageously, the doping of the N-doped layer 15 is carried out with silicon, a chemical element that can easily be integrated in the layer 15 during a possible formation by epitaxy.
    The superposition of the P-doped GaN layer 14 to the N-doped GaN layer 15 makes it possible to form a depleted P / N junction, so as to form a particularly high potential barrier under the electron gas layer. The formed P / N junction can be completely depleted with appropriate dopant thicknesses and concentrations in the layers 14 and 15. In addition, such a junction is formed with materials compatible with the unintentionally doped GaN 16 layer for forming the layer of electron gas. In addition, such a potential barrier makes it possible to avoid the formation of an AIGaN layer under this unintentionally doped GaN layer 16, which makes it possible to limit the mechanical stresses at the interface with this layer of GaN 16.
    This technical solution of the invention can be applied for both a normally open type transistor or a normally closed type transistor.
    Figure 2 is a conduction band diagram of transistor 1 previously detailed as a function of depth. By way of comparison, Figure 3 provides a conduction band diagram of a prior art transistor as a function of depth. The transistor of the state of the art taken into account comprises a 25 nm AIGaN layer formed on an unintentionally doped GaN layer with a thickness of 1.40 μm.
    It can be seen that the potential barrier for transistor 1 according to the invention is approximately 1.3 eV. On the other hand, the potential barrier of the transistor according to the state of the art is approximately 0.15 eV. The transistor 1 according to the invention thus makes it possible to obtain a particularly high potential barrier in order to avoid the trapping of the electrons of the electron gas layer 18 in the layer 13 for example. Simulations have made it possible to determine that the electron density in the respective electron gas layers of these transistors are substantially equivalent, about 8.5 × 10 12 cm 2 for the transistor of the example of FIG. 8.2 * 1012 cnr2 for the transistor of the example of Figure 2. The electron density of the electron gas layer 18 according to the invention therefore remains particularly high. The influence of various parameters of the layers 14, 15 and 16 on the formation of a potential barrier for the electron gas layer 18 and the GaN layer 16 will be further detailed later.
    According to a variant illustrated in FIG. 4, a layer 19 of GaN is formed in a manner known per se on the AIGaN layer 17, in order to avoid oxidation of the AIGaN layer 17. The layer 19 is etched under the contacts to create a contact with the layer 17. The layer 19 has for example a thickness between 1 and 3nm.
    In order to anticipate the influence of different parameters on the performance of transistor 1 according to the invention, the following notations will be used later:
    Ns: the density of electrons in the electron gas layer (in cnr2); P2deg: the mobility of electrons in the electron gas layer (in cm2 / Vs);
    Nd: the volume density of donors in the N-doped GaN layer (in cm-3);
    Na: the density of acceptors in the P-doped GaN 14 layer (in cm 3);
    NA: the density density of acceptors in a P-doped GaN layer sufficiently thick to be non-depleted (in cm 3);
    Nd +: Density of donors in an N-doped GaN layer sufficiently thick to be non-depleted (in cm 3); nor: the density of intrinsic carriers in a GaN layer at room temperature (in cm-3); RT: (for Room Temperature in English) the ambient temperature taken into account of 300K; T: the temperature of the substrate in K;
    Nsc: the electron density in the layer 16 of the transistor 1 (in cm 2);
    Wn: the thickness of the N-doped GaN layer;
    Wnid: the thickness of the GaN layer 16 unintentionally doped;
    Wp: the thickness of the P-doped GaN 14 layer;
    Vbi: the diffusion potential (referred to as the 'built-in potential' in English) of the P / N junction formed at the interface between layers 14 and 15;
    Vbbpn: the potential barrier across the depleted P / N junction;
    Vbbnid: the potential barrier across the unintentionally doped GaN 16 layer;
    Vbb: the total potential barrier; εο: the permittivity of the void; esc: the permittivity of GaN;
    k: the Boltzman constant = 1.3806488 E-23 J / K q: the electronic load * 1.6 E'19 C.
    The accesses of the transistor 1 include the areas between the control gate 23 and the drain 22, and between the control gate 23 and the source 21, including the electron gas layer 18.
    The diffusion potential of the junction between the layers 14 and 15 can be defined as follows:
    With a P doping carried out with magnesium, the ionization energy of the Mg acceptor in GaN is about 180 meV. The ionization is therefore partial at RT temperature. It must therefore be taken into account for the calculation of Vbi by the inequality Na- <Na at temperature RT.
    With ni = 1.9 e-10 cm-3 at RT, ND "Nd + = 1 e16cnv3 (with silicon doping) and Na- = 1e17cnv3, we obtain Vbi" 3.1 V. Vbi remains insensitive to variations of Na- and Nd + because of the logarithm in the relation and the low value of ni.
    The potential barrier formed between the electron gas layer 18 and the buffer layer 13 (preventing the injection and trapping of the electrons in the deep layers of the buffer layer 13) appears thanks to the diffusion potential Vbi, and includes: part of a potential barrier across the P / N junction formed between the layers 14 and 15:
    in part, a potential barrier across the GaN 16 layer:
    In the space charge area of the p / n junction, all the acceptors and donors are ionized and it is therefore their total concentration that intervenes in the calculations (Na = Na and Nd + = Nd).
    The potential barrier obtained by the combination of the layers 14 and 15 reaches a higher level than that of a possible layer of AIGaN placed under the layer 16 for forming the electron gas (as the example detailed in 'Characteristics of AIGaN / GaN / AIGaN double heterojunction HEMTs with an improved breakdown voltage quoted in the introduction).
    We can cite design rules of such a transistor 1.
    When the dopant of layer 14 is magnesium the extreme limits for Na are set by: - the capabilities of the epitaxy technology to incorporate and activate magnesium in GaN layer 14 (taking into account a solubility limit and passivation with Mg-H type complexes in particular). The maximum value usable for Na is at present a priori of 1e19cnr3 - The value necessary to have a Vbi> 3V, ie NA> 3e16cnrr3
    It is theoretically possible to design a transistor 1 according to the invention in this range of values. In practice, it will be advantageous to use a concentration of 17cnr3 <Na <1e18cnr3. NA> 1e17cnr3 makes it possible to obtain a significant buried barrier (Back Barrier in English language) (> 1.3V) and Na <1e18cnr3 makes it possible to obtain a robust thickness for layer p 14 (Wp> 15nm).
    For the layer 15, it is possible to select, for example, a value Nd of between 17cnr3 and Na, in particular with Si as dopant.
    The diffusion potential Vbi can then be calculated according to the previously detailed relationship.
    It is then possible to calculate a corresponding total depletion WnO thickness in a GaN n layer and a corresponding total depletion WpO thickness in a GaN P layer in the case where the N and P layers have thicknesses greater than WnO and WpO, respectively.
    The thicknesses of GaN 15 and GaN 14 layers can then be determined so that they are completely depleted, respecting only the following inequalities:
    WnO>Wn; and
    WpO> Wp
    The GaN layer 14 is advantageously completely depleted, in order to avoid keeping a conductive layer of holes which would prevent the electric field from developing in the thickness of the GaN layer 13, which would induce a strong degradation of the voltage withstand of the transistor.
    With Vbi = 3.1V, Na = 1 * 1018 cm-3 and Nd = 1 * 1018 cm-3, a Wpo value of 41 nm is obtained. Advantageously, a sufficiently high Wp value is used so that it can be carried out epitaxially with robustness (for example Wp> 10 nm). We can choose a Wp value of 28nm for example. A decrease in the Wp value lowers the level of the potential barrier. On the other hand, a decrease in the value WP guarantees the depletion of the GaN layer. Advantageously, Wp is between 30 and 50 nm, and preferably equal to 50 nm.
    To obtain a complete depletion of the GaN layer 15, the following relation is verified:
    With Να = Νο = 1θ18οτγ3, Wno = 41 nm, one can choose a Wn value of 28nm for example.
    Advantageously, Wn> 0.2 * WnO or Wn> 10nm, in order to prevent the depletion from having an impact on the electron gas layer 18. Indeed, the layer 15 must absorb a significant proportion of the potential of diffusion. A sufficiently high thickness Wn is furthermore used so that the potential barrier generated by the junction is sufficient to prevent the injection of electrons with a sufficient space charge developed in the layer 15. A Wn value of 28 nm is satisfactory example.
    Advantageously, WnO is greater than Wn (for example WnO> Wn), so that the GaN layer 15 is completely depleted under the electrodes of transistor 1. For example, for a WnO value of 41 nm, it is possible to choose a value Wn less than 41nm.
    With Wn = 28nm and Wp = 28nm and Na = Nd = 1e18crrr3, a potential barrier of about 1.7eV is obtained, of which 0.9eV at the terminals of the junction and 0.3eV at the terminals of the layer 16. The thickness of the layer 16 is advantageously thick enough to avoid any disturbance of the electron gas layer 18 at the level of the electrodes of the transistor by the influence of the dopants of the layers 14 and 15. Thus, advantageously, 100 nm>Wnid> 50 nm ( for example obtained with Wn = 28 nm and Wn + Wnid> 78 nm to limit the influence of magnesium on the electron gas layer 18). Advantageously, Wnid = 50nm.
    The layers 12 to 18 may be formed successively in the same vapor phase epitaxy machine, of course changing the epitaxial conditions for each of the layers. The epitaxial parameters for the formation of each of the layers are known to those skilled in the art.
    In the example illustrated, the barrier layer 17 is formed of AIGaN. According to the invention, any other semiconductor layer may be disposed on the layer 16 of unintentionally doped GaN, if it is adapted to generate an electron gas at their interface. The layer 17 may for example be another ternary alloy of element III nitride. The layer 17 may also be a binary alloy of element III nitride, for example AlN.
    In the example the AIGaN of the layer 17 may comprise an aluminum concentration of between 6 and 9%, but other proportions of aluminum may of course be used.
    In the various variants, it is conceivable to interpose an AlN layer between a layer of AIGaN 17 and a layer of GaN 16, in order to increase the confinement of the electron gas and its mobility. This AlN layer advantageously has a thickness of between 5 Angstrom and 2 nm.
    The layer 17 may advantageously be covered with a passivation layer, in particular to improve the isolation between the electrodes of the transistor 1. The passivation layer may for example be made of SiN. A SiN layer may be epitaxially deposited without removing the wafer from the epitaxial plant after formation of layers 16 and 17.
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    1. Transistor (1) has been rojo concept high electron mobility, characterized in that it comprises: a first layer of GaN (13); a second P-doped GaN layer (14) formed on the first GaN layer; a third N-type doped GaN layer (15) formed on the second GaN layer so as to form a depleted p / n junction; a fourth layer of GaN (16) unintentionally doped and formed on the third layer of GaN; a semiconductor layer (17) formed vertically above the fourth GaN layer unintentionally doped to form an electron gas layer (18).
    [2" id="c-fr-0002]
    The heterojunction transistor of claim 1, wherein the second GaN layer (14) includes magnesium forming a P-type dopant.
    [3" id="c-fr-0003]
    The heterojunction transistor of claim 2, wherein the magnesium concentration in the second GaN layer (14) is at least 5 * 1016 cm-3.
    [4" id="c-fr-0004]
    A heterojunction transistor according to claim 2 or 3, wherein the magnesium concentration in the second GaN layer (14) is at most 2 * 1018 cm-3.
    [5" id="c-fr-0005]
    A heterojunction transistor according to any one of the preceding claims, wherein said second GaN layer (14) has a thickness of between 20 and 50 nm.
    [6" id="c-fr-0006]
    A heterojunction transistor according to any one of the preceding claims, wherein the third GaN layer (15) includes N-type dopant forming silicon.
    [7" id="c-fr-0007]
    The heterojunction transistor of claim 6, wherein the silicon concentration in the third GaN layer (15) is at least 1.5 * 1016 cm-3.
    [8" id="c-fr-0008]
    A heterojunction transistor according to claim 6 or 7, wherein the silicon concentration in the third GaN layer (15) is at most 2 * 1018 cm-3.
    [9" id="c-fr-0009]
    A heterojunction transistor according to any one of the preceding claims, wherein said third GaN layer (15) has a thickness of between 10 and 100 nm.
    [10" id="c-fr-0010]
    A heterojunction transistor according to any one of the preceding claims, wherein said fourth layer (16) has a dopant concentration of less than 1 * 1016 cm-3.
    [11" id="c-fr-0011]
    11. heterojunction transistor according to any one of the preceding claims, wherein said fourth layer (16) has a thickness between 50 and 100nm.
    [12" id="c-fr-0012]
    A heterojunction transistor according to any one of the preceding claims, wherein said first GaN layer (13) has a higher carbon concentration than the second and third GaN layers.
    [13" id="c-fr-0013]
    The heterojunction transistor (1) according to any one of the preceding claims, wherein said semiconductor layer (17) includes AIGaN.
    [14" id="c-fr-0014]
    A heterojunction transistor (1) according to any one of the preceding claims, comprising a further AlN semiconductor layer having a thickness of between 0.5 and 2 nm arranged between the fourth GaN layer and said semiconductor layer formed at the plumb with the fourth layer of GaN.
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    同族专利:
    公开号 | 公开日
    FR3047607B1|2018-04-27|
    JP2017183703A|2017-10-05|
    US10050112B2|2018-08-14|
    EP3203526A1|2017-08-09|
    US20170229550A1|2017-08-10|
    JP6910807B2|2021-07-28|
    引用文献:
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    US20110272708A1|2010-05-06|2011-11-10|Kabushiki Kaisha Toshiba|Nitride semiconductor device|FR3102610A1|2019-10-28|2021-04-30|Commissariat A L'energie Atomique Et Aux Energies Alternatives|ELECTRONIC COMPONENT WITH HETEROJUNCTION AND DOUBLE OHMIC CONTACT|
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    优先权:
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    FR1650899A|FR3047607B1|2016-02-04|2016-02-04|HETEROJUNCTION TRANSISTOR HAVING ENHANCED ELECTRON GAS CONTAINMENT|
    FR1650899|2016-02-04|FR1650899A| FR3047607B1|2016-02-04|2016-02-04|HETEROJUNCTION TRANSISTOR HAVING ENHANCED ELECTRON GAS CONTAINMENT|
    JP2017016424A| JP6910807B2|2016-02-04|2017-02-01|Improved electron gas confinement heterojunction transistor|
    EP17154326.7A| EP3203526A1|2016-02-04|2017-02-02|Heterojunction transistor with improved electron gas confinement|
    US15/423,968| US10050112B2|2016-02-04|2017-02-03|Electron gas confinement heterojunction transistor|
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