• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method for producing a transistor comprising the following steps: a) forming a semiconductor layer (52) extending over an insulating layer; b) thermally oxidizing the semiconductor layer throughout its thickness along two bars (38) extending in the direction of the gate width of the transistor; and c) forming isolation trenches oriented in the direction of the gate length of the transistor, the semiconductor layer being constrained before or after step a).
    公开号:FR3046492A1
    申请号:FR1563507
    申请日:2015-12-31
    公开日:2017-07-07
    发明作者:Remy Berthelon；Didier Dutartre；Pierre Morin；Francois Andrieu；Elise Baylac
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics SA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR PRODUCING TRANSISTORS MOS CONSTRAINTS
    Field
    The present application relates to the field of transistors, in particular a MOS transistor formed in and on a stressed active area.
    Presentation of the prior art
    The performance of certain types of MOS transistors can be improved by the presence of constraints in the channel region.
    In particular, in a P-channel MOS transistor having a SiGe silicon-germanium channel region oriented in the <100> crystal direction, the mobility of the holes is increased by compressional stresses oriented in the drain-source direction. that is, the direction of the transistor length. On the other hand, a compression stress oriented in the direction of the width of the transistor reduces the mobility of the holes. It is desirable to increase the mobility to increase the speed of the transistors.
    The known methods for producing constrained transistors pose various problems, particularly in the case of very small-sized transistors formed in and on active areas of length less than 400 nm. summary
    Thus, an embodiment provides a method for producing a transistor comprising the following steps: a) forming a semiconductor layer extending over an insulating layer; b) thermally oxidizing the semiconductor layer throughout its thickness along two bars extending in the direction of the gate width of the transistor; and c) forming isolation trenches oriented in the direction of the gate length of the transistor, the semiconductor layer being constrained before or after step a).
    One embodiment provides a method of making a transistor comprising the steps of: a ') forming a stressed semiconductor layer extending over an insulating layer; b ') thermally oxidizing the strained layer throughout its thickness in two bands extending in the direction of the gate width of the transistor; and c ') forming isolation trenches oriented in the direction of the gate length of the transistor.
    According to one embodiment, step b ') takes place after step a').
    According to one embodiment, step a ') takes place after step b').
    According to one embodiment, the strained layer is made of silicon-germanium, the stress being a compressive stress.
    According to one embodiment, the stressed layer has a thickness of between 5 and 8 nm.
    According to one embodiment, step a ') is carried out at a temperature of between 850 and 1000 ° C. for a duration of between 5 and 15 minutes.
    According to one embodiment, the strained layer is made of silicon, the constraint being an extension constraint.
    One embodiment provides a transistor formed in and on an active area of a semiconductor layer, the active area being delimited, in the length direction, by thermal oxide bars imposing in the active area a constraint in the direction the gate length of the transistor and, in the direction of the gate width of the transistor, by isolation trenches leaving the active area free of stress in the width direction.
    According to one embodiment, the constrained semiconductor layer is made of silicon-germanium and rests on an insulating layer made of silicon oxide, the oxide bars being made of silicon and germanium oxide, the stress being a compressive stress.
    According to one embodiment, the constrained semiconductor layer is made of silicon, the oxide bars being made of silicon oxide, the stress being an extension constraint.
    Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments given in a non-limiting manner in relation to the appended figures in which: FIG. 1 is a perspective view of a transistor MOS formed in and on an active area; Figures 2A to 2C illustrate a method of making a MOS transistor;
    FIG. 2D illustrates the mobility of the holes in P-channel MOS transistors obtained by the method illustrated in FIGS. 2A to 2C; FIGS. 3A to 8A and 3B to 6B, 7C and 8B illustrate an exemplary method for producing a MOS transistor; and Figs. 9A to 12A and 9B to 12B illustrate another example of a method of making a MOS transistor.
    detailed description
    The same elements have been designated with the same references in the various figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed. In particular, details of grid structures such as gate insulators and insulating spacers are not shown.
    In the following description, when reference is made to position qualifiers, such as the terms "low", "higher", etc., or to qualifiers for orientation, such as "horizontal", " vertical, etc., reference is made to the orientation of the element concerned in FIGS. 1, 2A to 2C and 3B to 8B. Unless otherwise specified, the expression "of the order of" means within 10%, preferably within 5%.
    Figure 1 is a perspective view of a MOS transistor fomed in and on a rectangular active area. The active zone formed in a semiconductor (Si) on insulator layer (S1O2) is delimited laterally by insulators (not shown). The transistor comprises a gate structure G separating a drain area D from a source area S. The gate has a length / between the drain and source areas and a width W in the orthogonal direction. Here, length L of the transistor will be called its dimension in the direction of the gate length, and width W of the transistor its dimension in the direction of the gate width.
    FIGS. 2A to 2C illustrate a method for producing a P-channel MOS transistor.
    Figure 2A is a sectional view of a wafer portion at an initial stage of manufacture. An insulating layer 1 of silicon oxide is disposed on a support 3. A stressed semiconductor layer 5, for example SiGe, extends over the insulating layer 1 and is covered with a layer of silicon oxide 7. For example, layers 5 and 7 have been formed from the upper silicon thin layer of a SOI silicon-on-insulator structure. To produce the layers 5 and 7, a SiGe epitaxy is first performed on the thin layer of silicon. In epitaxy, a mismatch causes horizontal biaxial compression stresses in the epitaxial layer. Thereafter, the upper surface of the assembly is thermally oxidized. Silicon is preferentially oxidized and germanium migrates downward while stresses 9 intensify. The SiGe layer 5 is then obtained on the insulating layer 1 and under the silicon oxide layer 7. By way of example, the SiGe layer 5 has a thickness of between 5 and 8 nm. The layer 7 of silicon oxide may have a thickness of between 3 and 6 nm. The proportion of germanium in the layer 5 may be between 10 and 40%. In the step illustrated in FIG. 2B, isolation trenches 10 have been etched using masking layers 11. The trenches 10 pass through the entirety of the SiGe layer 5 and surround active zones 12. The trenches 10 Isolation 10 can pass entirely through the insulating layer 1. For the sake of clarity, only two trenches 10 and an active zone 12 are shown, the distance between the trenches corresponding in the view of FIG. 2B to the length of the transistor to be produced. The digging of the trenches has freed the edges of the active zone 12. As a result, only a residual portion 13 of the initial stresses 9 persists in a central part of the active zone 12. At the stage illustrated in FIG. a P-channel MOS transistor. The isolation trenches 10 have been filled with an insulator 14, for example silicon oxide. A gate structure 15 has been formed on a central portion of the active zone 12. Drain and source zones 17, for example made of boron-doped silicon-germanium, have been epitaxially formed on either side of the grid structure 15.
    FIG. 2D illustrates the mobility of holes in arbitrary units in transistors obtained by the method of FIGS. 2A to 2C, as a function of the length L of the transistors. The constraints in the direction of the width were released during the digging of the isolation trenches, this width being for example 170 nm. The residual stresses 13 in the direction of the length are even lower than the length of the transistor is small. In a transistor less than 180 nm in length, the mobility of the holes is 65% less than the mobility of the holes in a transistor of more than 500 nm in length.
    It is therefore desired to have a method making it possible to form a transistor from a stressed semiconductor layer without releasing in this layer the constraints in the direction of the length.
    FIGS. 3A to 8A are top views illustrating successive steps of an exemplary method for producing MOS transistors. FIGS. 3B to 6B are sectional views along a plane BB orthogonal to the direction of the width, respectively corresponding to FIGS. 3A to 6A. Figure 7C is a sectional view along the plane CC of Figure 7A and Figure 8B is a perspective view in section corresponding to Figure 8A.
    In FIGS. 3A and 3B, a semiconductor-constrained layer 20, for example SiGe, extends over an insulator 22 covering a support 24. The layer 20 was obtained for example from an SOI-type structure by a similar process. to that described in connection with FIG. 2A, that is to say comprising epitaxy of SiGe followed by thermal oxidation. A layer 25 of silicon oxide covers the SiGe layer 20. The stresses 26 in the layer 20 are horizontal and biaxial. These stresses have a component 28 in the direction of the length, and a component 30 in the direction of the width.
    In FIGS. 4A and 4B, a masking layer 32, for example made of silicon nitride, is deposited on the upper surface of the assembly. Apertures 34 are etched in the masking layer and in the silicon oxide layer 25 to the upper surface of the stressed SiGe layer 20. The etched areas form in top view strips 36 parallel to each other in the direction of the width. At this stage, the stresses 26 in the layer 20 are not modified.
    In FIGS. 5A and 5B, a thermal oxidation is carried out in the layer 20 from the openings 34. The portions of the layer 20 located at the bottom of the openings 34 are oxidized over their entire thickness. The oxide formed constitutes parallel insulating bars 38, in contact with the insulating layer 22. The vertical dimension or height of the bars is greater than the total thickness of the strained layer 20 and the silicon oxide layer 25. portion 40 of the layer 20 is thus isolated on two sides between the oxide bars 38.
    It is noted that the oxidation step does not release the stresses 26 in the layer portion 40. The stress component 28 is therefore maintained by the thermal oxide bars 38 over the entire length of the portion 40 without being attenuated. In addition, the increase in volume of the oxidized portions of the layer 20 can even add to the component 28 additional compression. The thermal oxidation of SiGe can be carried out in an oven at a temperature below 1000 ° C. for a duration of between a few minutes, for example 3 minutes, and a few tens of minutes, for example 100 minutes. This oxidation can also be carried out by rapid thermal oxidation ("rapid thermal oxidation") at a temperature of between 950 and 1200 ° C. for a duration of between a few tens of seconds, for example 30 seconds, and a few hundred seconds. seconds, for example 1000 seconds.
    In FIGS. 6A and 6B, the masking layer 32 and the oxide layer 25 have been removed by etching. The height of the bars 38 has been reduced by the etching of the silicon oxide layer, but remains greater than the thickness of the portion of the SiGe layer 20. The stresses 26 are therefore maintained in the portions 40 of the layer 20 by the oxide bars 38 which serve as stops.
    Figures 7A and 7C illustrate the structure at a later stage of manufacture. Figure 7C is a sectional view along the plane CC of Figure 7A and not as previously in the plane BB. In the direction of the length of the device, two trenches 50 have been dug. Thus, all the trenches 50 and thermal silicon oxide regions 38 delimit an active zone of SiGe 52. The trenches 50 can extend into the substrate 24, unlike the apertures 34 which stop at the surface of the stress layer 20 of SiGe. Unlike the openings 34 which preserve the stresses 28 in the layer 20 in the direction of the length of the device, the trenches 50 substantially completely eliminate the stresses 30 in the direction of the gate width, as has been previously described in connection with the Figures 2A to 2D. This elimination of the stresses is all the more important that the active zone 52 is narrow, which is currently the case, the active areas having for example a length of less than 300 nm and a width of less than 200 nm.
    Figure 8A shows a subsequent step of the manufacturing process and Figure 8B is a corresponding sectional view along the plane BB and in perspective. As illustrated in FIG. 8B, the trenches 50 were filled with an insulator 54 and then a grid 60 and epitaxial drain and source thickenings 62 were formed.
    Thus, a transistor occupying the surface of the active zone 52, with stresses released in the direction of the width and with stresses 28 maintained in the direction of the length, is obtained. As stated previously, maintaining the stresses in the length direction and removing them in the width direction results in the formation of a particularly fast transistor.
    Figs. 9A to 12A are top views illustrating successive steps of another exemplary method of making a MOS transistor. Figures 9B to 12B are sectional views along a plane BB orthogonal to the direction of the gate width, respectively corresponding to Figures 9A to 12A.
    In FIGS. 9A and 9B, a masking layer 72, for example made of silicon nitride, is deposited on the upper surface of the upper silicon layer 70 of an SOI structure. The SOI structure comprises, under the upper layer 70, an insulator 22 covering a support 24. Apertures 74 are etched in the masking layer 72 to the upper surface of the layer 70. The openings 74 form a top view of the strips 36 in the direction of the width.
    In FIGS. 10A and 10B, the semiconductor layer 70 is thermally oxidized from the openings 74. The oxidized portions of the layer 70 form insulating bars 76 in contact with the insulating layer 24. As a variant, to produce the insulating bars 76 it is possible to engrave the entire thickness of the layer 70 from the openings 74, then to fill the etched portions and the openings 74 with oxide.
    In FIGS. 11A and 11B, the masking layer 72 is first removed by etching. A layer 78 of SiGe is then epitaxially grown on the upper surface of the unoxidized portions of the semiconductor layer 70. During epitaxy, a mismatch causes compression stresses in the layer 78, as described in connection with the Figure 2A. The resulting layer 78 has stresses 80 in both the width direction and the length direction.
    In FIGS. 12A and 12B, thermal oxidation is carried out. As previously described, the germanium migrates downward to form SiGe stress layer portions 82 disposed between the bars 76. During oxidation, a layer 84 of silicon oxide is formed on the layer 82.
    After removal by etching of the oxide layer 84, an assembly is obtained corresponding to the step illustrated in FIGS. 6A and 6B, in which the portions of the layer under stress between the bars 38 are replaced by the equivalent layer portions 82 Similar to the portions 40 of Figs. 6A and 6B, the layer portions 82 have stresses 88 in the width direction and have stresses 86 in the direction of the grid length between the bars 76 which serve as stops.
    A transistor is then formed after steps equivalent to the steps illustrated in plan view in FIGS. 7A and 8A, the constraints in the direction of the gate width being released by the formation of trenches in a direction orthogonal to that of the strips 36.
    Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although in the process example described above, the isolation trenching step described in connection with FIGS. 7A and 7B takes place after the steps described in connection with FIGS. 3A through 6A of FIG. With the formation of thermal oxide rods, the isolation trenches could be formed and filled before forming the oxide oxide bars.
    Further, although the exemplary methods described above relate to the formation of a P-channel MOS transistor from a compression-stressed SiGe layer, a similar method could be used to form constrained active semiconductor zones. in length without constraint in width, or conversely. In particular, an N-channel MOS transistor could be formed from a stretch-constrained silicon layer.
    权利要求:
    Claims (11)
    [1" id="c-fr-0001]
    A method of making a transistor comprising the steps of: a) forming a semiconductor layer (20) extending over an insulating layer (22); b) thermally oxidizing the semiconductor layer throughout its thickness along two bars (38) extending in the direction of the gate width of the transistor; and c) forming isolation trenches (50) oriented in the direction of the gate length of the transistor, the semiconductor layer being constrained before or after step a).
    [2" id="c-fr-0002]
    A method of making a transistor according to claim 1, comprising the steps of: a) forcing a strained semiconductor layer (20) extending over an insulating layer (22); b ') thermally oxidizing the stress layer throughout its thickness along two bars (38) extending in the direction of the gate width of the transistor; and c ') forming isolation trenches (50) oriented in the direction of the gate length of the transistor.
    [3" id="c-fr-0003]
    3. The method of claim 2, wherein step b ') takes place after step a').
    [4" id="c-fr-0004]
    4. The method of claim 2, wherein step a ') takes place after step b').
    [5" id="c-fr-0005]
    5. Method according to any one of claims 2 to 4, wherein the strained layer is silicon-germanium, the stress being a compressive stress.
    [6" id="c-fr-0006]
    6. The method of claim 5, wherein the stressed layer has a thickness between 5 and 8 nm.
    [7" id="c-fr-0007]
    7. The method of claim 6, wherein step a ') is carried out at a temperature between 850 and 1000 ° C for a period of between 5 and 15 min.
    [8" id="c-fr-0008]
    8. Method according to any one of claims 2 to 4, wherein the strained layer is silicon, the stress being an extension stress.
    [9" id="c-fr-0009]
    A transistor formed in and on an active zone (52) of a semiconductor layer, the active zone being delimited, in the length direction, by thermal oxide bars (38) imposing a stress in the active zone the direction of the gate length of the transistor and, in the direction of the gate width of the transistor, by isolation trenches (50) leaving the active area free of stress in the direction of the width.
    [10" id="c-fr-0010]
    10. Transistor according to claim 9, wherein the strained semiconductor layer is silicon-germanium and is based on an insulating layer of silicon oxide, the oxide bars being made of silicon oxide and germanium, the stress being a stress of compression.
    [11" id="c-fr-0011]
    11. The transistor of claim 10, wherein the strained semiconductor layer is silicon, the oxide bars being silicon oxide, the stress being an extension stress.
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    同族专利:
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    引用文献:
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    法律状态:
    2016-11-21| PLFP| Fee payment|Year of fee payment: 2 |
    2017-07-07| PLSC| Publication of the preliminary search report|Effective date: 20170707 |
    2017-11-21| PLFP| Fee payment|Year of fee payment: 3 |
    2019-11-20| PLFP| Fee payment|Year of fee payment: 5 |
    2020-11-20| PLFP| Fee payment|Year of fee payment: 6 |
    2021-11-18| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1563507A|FR3046492B1|2015-12-31|2015-12-31|METHOD FOR PRODUCING TRANSISTORS MOS CONSTRAINTS|
    FR1563507|2015-12-31|FR1563507A| FR3046492B1|2015-12-31|2015-12-31|METHOD FOR PRODUCING TRANSISTORS MOS CONSTRAINTS|
    US15/387,712| US10263110B2|2015-12-31|2016-12-22|Method of forming strained MOS transistors|
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