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    • 专利摘要:
    A method for producing a semiconductor nanowire transistor (100), comprising the steps of: - producing, on a support (102), a semiconductor nanowire whose portion (123) is covered with a sacrificial gate surrounded, with the nanowire, of a dielectric layer, - withdrawing the sacrificial gate, forming a first space surrounded by first portions of the dielectric layer, - ionically implanting a second portion of the dielectric layer under said first portion, said first portions protecting third parts (136) of the dielectric layer, - etching said second part, forming a second space, - making a grid (140, 142) in the spaces, and a dielectric portion (148) on the grid and said first parts, - implanting ionically fourth portions of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third portions - to engrave the said fourth parts.
    公开号:FR3043837A1
    申请号:FR1561044
    申请日:2015-11-17
    公开日:2017-05-19
    发明作者:Sylvain Barraud；Emmanuel Augendre；Sylvain Maitrejean；Nicolas Posseme
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR PRODUCING A SEMICONDUCTOR NANOFIL TRANSISTOR COMPRISING A SELF-ALIGNED GRID AND SPACERS
    DESCRIPTION
    TECHNICAL FIELD AND PRIOR ART The invention relates to a method for producing a semiconductor nanowire transistor (s) and comprising a gate and self-aligned spacers. The invention applies in particular to the production of multi-gate transistors, or multigrid transistors, for example of GAAFET (Gate-AII-Around Field-Effect Transistor) type. The invention applies in particular to the field of FET devices used for logic applications with high performance and low consumption of microelectronics, as well as to the design and manufacture of FET transistors each comprising several nanowires superimposed on each other. over others, used in the design of integrated circuits with improved electrical performance compared to the current state of the art.
    The document US 2008/0135949 A1 describes a method for producing a FET transistor whose channel is formed of several superimposed nanowires. In this method, a stack of semiconductor layers comprising alternating layers of silicon and SiGe layers is first produced. When silicon is the material intended to form the nanowires, a selective removal of the SiGe with respect to the silicon is then implemented at the channel region of the transistor so as to release the silicon nanowires before depositing the gate of the transistor around these nanowires.
    With such a method, constraining drawing rules must be applied in order to be able to release the silicon nanowires while having a maintenance of the structure. Because of these design rules, the size of the semiconductor blocks forming the source and the drain is large and does not allow to obtain a high density of nanowires. Moreover, a good positioning and a good definition of the grid pattern is difficult to obtain.
    The documents US Pat. No. 8,679,902 B1 and EP 2,654,083 A1 describe other processes for producing transistors whose channels comprise superimposed nanowires and which are provided with a coating grid around the nanowires. In these documents, the grid is formed by a damascene-type process (an approach known under the name of "Gate-Last" or "Replacement Métal Gâte", RMG), in which: a sacrificial gate is first formed in covering a stack of silicon layers and alternate SiGe layers, at the channel region, then - gate spacers and the source and drain regions are made, then - the sacrificial gate is then etched through a layer masking the whole structure, this etching also serving to suppress the SiGe (when the SiGe is used as sacrificial material and the channel is intended to be formed by silicon nanowires) at the channel region of the transistor to form the nanowires, and finally - the final grid is made in the space formed by the etching of the sacrificial gate. The disadvantage of such an approach is that the etching implemented to suppress the SiGe at the channel region does not stop at the level of the opening formed in the masking layer for the removal of the sacrificial gate, this etching propagating towards the source and drain regions. When selectively removing SiGe from silicon, there is no self-alignment of the removed SiGe with the defined location to form the gate. Consequently, the definitive grid deposited after the removal of these sacrificial layers is not self-aligned with the volume formed solely by the withdrawal of the sacrificial gate. This results in an increase in the parasitic capacitances within the transistor because during the filling of the cavity by the gate materials, certain areas of the gate edge cover the source and drain areas.
    STATEMENT OF THE INVENTION
    An object of the present invention is to provide a method for producing a transistor with at least one semiconductor nanowire and a coating grid, or partially encapsulating, self-aligned with internal spacers arranged between the grid and the regions source and drain, allowing the realization of transistors with a high density on the support and does not have the disadvantages of the methods of the prior art described above.
    For this, the present invention proposes a method for producing at least one transistor with at least one semiconductor nanowire, comprising at least the implementation of the following steps: a) production, on a support, of at least one first semiconductor nanowire whose first portion intended to be part of the transistor channel is partially covered with a sacrificial gate, the sacrificial gate and the first nanowire being surrounded by a first dielectric layer, b) removal of the sacrificial gate, forming a first free space around which first portions of the first dielectric layer are disposed, c) first ion implantation of at least a second portion of the first dielectric layer disposed between the first portion of the first nanowire and the support, the first portions of the first dielectric layer protecting third portions of the first dielectric layer with respect to this first ion implantation, d) selectively etching the second portion of the first dielectric layer, forming a second free space, e) producing a gate in the first and second free spaces, and a dielectric portion disposed on the gate and on the first portions of the first dielectric layer, f) second ion implantation of fourth portions of the first dielectric layer surrounding second portions of the first nanowire intended to be part of the source and drain regions of the transistor, the dielectric portion protecting the first and third portions of the first dielectric layer with respect to this second ion implantation, g) selective etching of the fourth portions of the first dielectric layer.
    In this method, the third portions of the first dielectric layer thus form spacers arranged between the first nanowire and the support, and also between the nanowires when the transistor comprises several nanowires, and preventing the deposition of the gate materials in the source regions. and drain of the transistor.
    During the implementation of this method, the nanowire or nanowires are not etched in order to keep only the part or parts of the nanowire or nanowires intended to form the channel of the transistor, thus avoiding a loss of the stress present in the channel. which would be due to the presence of free edges around these parts of the nanowires.
    In this method, the spacers formed by the third portions of the first dielectric layer are defined in a self-aligned manner by virtue of the ion implantation implemented during which the first portions of the first dielectric layer and the dielectric portion mask these third portions of the dielectric layer. the first dielectric layer vis-à-vis these ion implantation which define the portions of the dielectric layer to be removed. Thus, the spacers formed by these third portions of the first dielectric layer are well aligned with the gate spacer formed by the first portions of the first dielectric layer, the gate being also well aligned with the portion of the nanowire forming the channel of the transistor.
    Finally, since portions of the nanowire or nanowires are retained to realize the source and drain regions, the realization of these regions, for example by epitaxy, is not critical because of the exposed semiconductor surface of these parts of the nanowire or nanowires, thus avoiding the formation of defects in the semiconductor of the source and drain regions.
    This method also makes it possible to produce one or more transistors formed of several nanowires, or several sets of superimposed nanowires, placed next to one another with a high density, for example made with a repetition pitch of between approximately 30 nm and 40 nm. .
    This method can be implemented to produce GAAFET type transistors, advantageously having gate lengths of less than about 20 nm. The invention is advantageously applicable to the fabrication of transistors for the production of integrated circuits for high performance and low power microelectronics logic applications: NAND flash memory, molecular memory, charge sensor type applications.
    The method can be applied to any structure requiring a self-alignment of a grid vis-à-vis one or more nanowires suspended over a support.
    The second portion of the first dielectric layer is disposed between the third portions of the first dielectric layer. Step a) can comprise at least the implementation of the following steps: a1) making, on the support, a stack of layers comprising at least a first layer of sacrificial material and at least a second semiconductor layer , the sacrificial material being capable of being selectively etched with respect to the semiconductor of the second layer, a2) etching of the stack of layers, forming at least the first nanowire disposed on a portion of the sacrificial material, a3) making the sacrificial gate on the first portion of the first nanowire and against the lateral flanks of the first portion of the first nanowire and a portion of the portion of sacrificial material, a4) etching the portion of sacrificial material, a5) deposit of the first dielectric layer around the sacrificial gate and the first nanowire.
    In this case, step a3) may comprise at least the implementation of the following steps: a31) depositing a sacrificial gate dielectric layer on the first nanowire and against the lateral flanks of the first nanowire and the portion of the sacrificial material, a32) depositing a layer of sacrificial gate conductive material covering the sacrificial gate dielectric layer, a33) making, on the layer of sacrificial gate conductive material, a mask in a pattern corresponding to that of the sacrificial gate, a34) etching the sacrificial gate dielectric layer and the sacrificial gate conductive material layer according to the pattern of the mask, forming the sacrificial gate, and wherein the first dielectric layer can also cover the mask disposed on the sacrificial grid.
    The method may further comprise, between steps a5) and b), a step of removing a portion of the first dielectric layer disposed on the mask, and a step of removing the mask.
    The first dielectric layer surrounding the sacrificial gate and the first nanowire may comprise at least one dielectric material whose dielectric permittivity is less than or equal to 7. This makes it possible to reduce parasitic capacitances and thus to increase the speed of operation of a circuit CMOS having such transistors. Step c) and / or step f) of the process, corresponding to the ion implantations, can be implemented using a dihydrogen based plasma, or an ion beam based on argon, fluorine or hydrogen.
    In this case, the method may further comprise, when step c) is implemented by ion beam, an annealing step capable of recrystallizing the semiconductor of the first portion of the first nanowire and implemented between steps c) and d).
    The method may further comprise, between steps a) and b), the implementation of the steps of: depositing a second dielectric layer covering the assembly formed of the support, the first nanowire, the sacrificial gate and the the first dielectric layer, - planarization of the second dielectric layer with a stop on the first dielectric layer, and in which portions of the second dielectric layer covering the fourth portions of the first dielectric layer are removed between the step of producing the gate and the second ion implantation step.
    In this case, the dielectric portion may advantageously be made in a third free space formed in the second dielectric layer. The second dielectric layer makes it possible to easily realize the dielectric portion in a localized manner on the gate and on the first portions of the first dielectric layer.
    The method may further comprise, when the gate comprises polysilicon, a siliciding step of an upper portion of the polysilicon of the gate implemented between steps e) and f).
    The implementation of step g) can also etch part of the dielectric portion in which ions have been implanted during the implementation of step f).
    The method may further comprise, after step g), the implementation of an epitaxy of the source and drain regions of the transistor from the second portions of the first nanowire, and then a silicidation of the source regions and drain.
    The method may be such that: step a) furthermore produces at least a second semiconductor nanowire disposed above the first nanowire and a first portion of which is intended to form part of the transistor channel is partly covered by the gate sacrificial, the first dielectric layer also surrounding the second nanowire, - the second portion of the first dielectric layer further comprises a portion of the first dielectric layer disposed between the first and second nanowires, - the fourth portions of the first dielectric layer also surround second portions of the second nanowire intended to be part of the source and drain regions of the transistor.
    The method can be implemented for more than two nanowires superimposed one above the other.
    The sacrificial gate and the gate may each comprise several distinct portions spaced apart from each other.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings, in which: FIGS. 1 to 20 represent the steps of a method of realizing semiconductor nanowire transistors, object of the present invention, according to a particular embodiment.
    Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Reference is first made to FIGS. 1 to 20, which represent the steps of a method of collective realization of two transistors 100 here of GAAFET type, according to a particular embodiment. These steps can however be applied in a similar manner for producing a single transistor 100.
    The transistors 100 are made from a semiconductor substrate that can be bulk or bulk type, for example silicon, or be of semiconductor-on-insulator type (for example SOI or "Silicon-On-Insulator", SiGeOI or "Silicon-Germanium-On-Insulator", etc.). In the particular embodiment described here, the substrate is of the SOI type. In FIG. 1, a buried dielectric layer 102, or BOX ("Burried-Oxide"), of the SOI substrate is shown, this layer 102 being covered with a surface layer 104 here made of silicon. For example, the surface layer 104 has a thickness of about 7 nm, which thickness may be between about 5 nm and 10 nm. For the realization of transistors 100 intended to have a gate length of between about 15 nm and 16 nm, the thickness of the sacrificial layer may be between about 6 nm and 7 nm. The layer 102 has for example a thickness between about 20 nm and 700 nm, and for example equal to about 145 nm.
    The surface layer 104 is then covered with a second layer 106 comprising a material corresponding to the semiconductor intended to form the nanowire or nanowires of the transistor, here SiGe. The material of the surface layer 104 is such that it can be etched selectively with respect to the semiconductor of the second layer 106. The thickness of the second layer 106 is for example equal to approximately 8 nm, and can be between about 2 nm and 50 nm. One or more other stacks of layers similar to the stack formed of the layers 104 and 106 are then made on the second layer 106, according to the number of superimposed nanowires to be made for the transistors 100. In the example of Figure 2 a single additional stack formed of a third layer 108 comprising the same material as that of the surface layer 104, here silicon, and a fourth layer 110 comprising the same material as that of the second layer 106, here of SiGe is made on the second layer 106. The thickness of the third layer 108 is for example similar to that of the surface layer 104, and that of the fourth layer 110 is for example similar to that of the second layer 106. The thicknesses layers 106 and 110 correspond to the thicknesses of the nanowires of the transistors 100 which will be realized thereafter, and the thicknesses of the layers 104 and 108 correspond to the thicknesses of the spaces that separate the superimposed nanowires from each other and the space between the substrate and the first nanowire. In general, the transistors 100 may be made from a number of stackings of layers of between approximately 1 and 20, allowing the production of a number of superimposed semiconductor nanowires between approximately 1 and 20. The layers 106, 108 and 110 are for example produced by epitaxy.
    According to a first variant, the material of the layers 104 and 108 may be silicon and the material of the layers 106, 110 may be Sii-xGex, with X such that 0.05 <X <1. According to a second variant, the material layers 104 and 108 may be Sii-xGex, with X such that 0.05 <X <1, and the material of layers 106, 110 may be silicon to form silicon nanowires.
    The layers 104 to 110 are then etched, for example by lithography and "spacer patterning" type etching, or indirect decomposition printing, in order to form one or more distinct stacks such that one or more superimposed nanowires can be made from each of the stacks arranged next to each other on the layer 102. In the example of Figure 3, three stacks 112a, 112b, 112c are formed, each having a portion of each of the layers 104, 106, 108, 110. Thus, each of the transistors 100, the embodiment of which is described herein, is intended to comprise six semiconductor nanowires arranged forming three groups of nanowires, these groups being arranged next to one another on the dielectric layer 102, and each group of nanowires comprising two nanowires superimposed one above the other. In general, each transistor 100 may comprise between about 1 and 10 superimposed groups of nanowires.
    The width Wnw of each of the stacks 112 (dimension parallel to the Y axis), which also corresponds to the width of the nanowires of the transistors 100 which will be made from these stacks 112, is for example between about 10 nm and 50 nm. and for example equal to about 20 nm. The space Enw between two neighboring stacks 112 (dimension parallel to the Y axis), which also corresponds to the space between two neighboring nanowires or two groups of adjacent nanowires of each transistor 100, is for example between about 20 nm and 40 nm. nm to obtain a high density of nanowires on the layer 102. Alternatively, this Enw space may be greater than about 40 nm, or even greater than about 1 pm. The length Lnw (dimension visible in FIG. 4A and parallel to the X axis) of each of the stacks 112, which also corresponds to the length of the nanowires from which the transistors 100 are made, is for example between approximately 40 nm and 1 pm
    In FIGS. 4A to 20, in order to allow a better reading of the drawings, the remainder of the process for producing the transistors 100 is described by only showing the stack 112a. However, the following steps described and implemented from the stack 112a are also implemented for the stacks 112b and 112c.
    A sacrificial gate 114 is then made for each transistor 100 on a portion of the upper faces of the stacks 112 and on a portion of the lateral flanks of the stacks 112, thus defining the future location of the gates of the transistors 100. In the example of FIGS. 4B, each of the sacrificial grids 114 is for example formed of a portion 116 comprising for example a SiO 2 / polysilicon stack. In Figure 4B, only one of the portions 116 is visible, and only the portion of this portion 116 which covers the stack 112a is shown. However, each of the portions 116 forms a continuous portion covering a portion of each of the stacks 112.
    These portions 116 are for example obtained by first producing a conformal deposition (forming a layer of substantially constant thickness) of SiO 2 whose thickness is for example between about 2 nm and 6 nm, followed by a deposit of polysilicon forming a layer whose thickness is between about 50 nm and 200 nm. A mask 118, for example made of silicon nitride, of thickness for example equal to approximately 40 nm and whose pattern corresponds to that of the portion or portions of the sacrificial gate or grids 114, is then deposited on the polysilicon layer, then the layers of polysilicon and S1O2 are then etched in the pattern defined by the mask 118.
    In each of the stacks 112 previously made, the portions of the layers 104 and 108 are then etched selectively vis-à-vis the portions of the layers 106 and 110 which then form, for each of the stacks 112 previously made, 120 and 122 nanowires of SiGe superimposed one above the other. The first nanowire 120 is suspended above the dielectric layer 102 and the second nanowire 122 is suspended above the first nanowire 120 (Figures 5A and 5B). This etching of the portions of the layers 104 and 108 forms a space 124 around the nanowires 120, 122. The nanowires 120, 122 are held in the suspended state by means of the sacrificial gate 114 which is in contact with them. The portions 116 are located above first portions 123 of the nanowires 120, 122 intended to form part of the channels of the transistors 100.
    A first dielectric layer 126 is then deposited in a conformal manner on the structure previously made (FIG. 6). The material of this layer 126 is notably deposited in the space 124 previously formed by the etching of the portions of the layers 104 and 108, thus completely surrounding the nanowires 120, 122 except at the portions of these nanowires in contact with the sacrificial gate 114. The dielectric material of the layer 126 is here a dielectric whose dielectric permittivity is advantageously less than or equal to about 7.
    As represented in FIG. 7, a second dielectric layer 128, comprising here a semiconductor oxide, covering the whole of the structure previously produced, is then deposited and then planarized by CMP (mechanical-chemical planarization) with stopping on the parts of the layer 126 which covers the mask 118.
    The mask 118 as well as the portions of the layer 126 disposed on and beside the mask 118 are removed by etching, for example by implementing a chemical etching of the H3PO4 type (FIG. 8). This etching forms an access to the portions 116 of the sacrificial grids 114.
    The sacrificial grids 114 are then removed, for example via the implementation of a chemical etching of the TMAH type, thus creating first free spaces 130 around which are arranged first portions 131 of the layer 126 and forming the locations of the final grids transistors 100 (Figure 9).
    As shown in FIG. 10, a first ion implantation is then implemented so that second portions 132 of the layer 126 lying vertically above the first free spaces 130, between and under the nanowires 120, 122, are subjected to this ion implantation and that the nature of the material of these second parts 132 is modified. The dimension "H" represented in FIG. 10 illustrates the depth up to which this implantation is made, and here corresponds to the sum of the thicknesses of the layers 104, 106 and 108. More generally, the ion implantation is implemented as such. that the ion implantation is carried out to this depth H which is equal to the sum of all the layers of the stack used for producing the nanowires, except that of the last layer of the stack (the layer being at top of the stack) used to form the last nanowire, that is to say the nanowire disposed above the other nanowires or nanowires. This first ion implantation allows the second parts 132 of the layer 126 to be etched selectively vis-à-vis the remainder of the layer 126 because the material having undergone this ion implantation grows faster than the non-implanted material.
    Along the side walls of the spaces 130, the first portions 131 are partially subjected to this ion implantation. Since the first portions 131 of the layer 126 covering the side walls of the first free spaces 130 have a height greater than the ion implantation depth H, only a portion of the first portions 131 of the layer 126 undergo this ion implantation. In addition, third portions 136 of the layer 126 located in the space 124, juxtaposed with the second parts 132 and arranged in alignment with the first parts 131 do not undergo this ion implantation thanks to the protection conferred by the first parts 131 of the layer 126 covering the sidewalls of the first free spaces 130, the ions sent vertically above the third parts 136 being implanted in the upper portions of the first parts 131. In addition, the remainder of the layer 126 is protected from this ion implantation thanks to the dielectric layer 128 which covers these other parts of the layer 126. The implantation implemented may correspond to implantation by ion beam or plasma.
    In the case of plasma implantation, the gas used may be composed of light atoms, for example dihydrogen, or H 2, so that the semiconductor of the nanowires 120, 122 is not altered by this ion implantation and retains its crystalline structure. The light atoms may correspond to atoms making it possible to modify the crystalline structure of the dielectric material of the layer 126 without making the semiconductor of the nanowires 120, 122. amorphous. The ion implantation may be carried out in an inductively coupled or capacitive plasma, or by immersion. The change in the chemical nature of the material of the portions of the layer 126 in which ions are implanted occurs in volume, resulting in a greater concentration of implanted species on the surface of these portions. For example, if such plasma implantation is carried out for a depth H equal to about 28 nm, the ion implantation can be carried out in a capacitively coupled reactor (CCP) with the following parameters: gas used : H2, - flow equal to about 50 sccm ("standard cubic centimeter per minute"), - energy of ions equal to about 300 W, - power of the source of emission of ions equal to about 800 W, - pressure equal to about 50 mTorr.
    In the case of ion beam implantation, different types of ions may be used, such as for example argon, fluorine or hydrogen ions. Advantageously, two successive ion beam ion implantations can be implemented in order to properly locate the dose of ions implanted in the desired portions of material. For example, to carry out the ion implantation in the second portions 132 of thickness equal to about 7 nm, the nanowires 120, 122 also having a thickness equal to about 7 nm, a first ion implantation by Ar ion beam of equal power at about 5 keV with a concentration equal to about 1015 cm 3 is implemented, followed by a second Ar ion beam ion implantation of power equal to about 15 keV with a concentration equal to about 1015 cm 3.
    With ion beam ion implantation, it is possible that the semiconductor of the nanowire portions traversed by the ion beam has become at least partially amorphous. In this case, it is possible to implement, after the ion implantation, an annealing to recrystallize the semiconductor of these parts of the nanowires 120, 122, such as a spike-type or peak-type activation annealing, for example at a temperature of about 1050 ° C.
    The portions 132 as well as the upper portions of the first portions 131 of the layer 126 in which ions have been implanted are then removed, for example by using wet etching using a 1% HF solution, thus etching these parts of material. dielectric selectively implanted with respect to the semiconductor of the nanowires 120, 122 and with respect to the dielectric material of the other parts of the layer 126 which have not undergone the ion implantation (FIG. 11). This shrinkage forms second free spaces 138 around the parts of the nanowires 120, 122 which were previously in contact with the second parts 132. In addition, thanks to the protection conferred by the first parts 131 of the layer 126 and the layer 128, these second free spaces 138 are perfectly aligned with the first free spaces 130, which will allow the gates of the transistors 100 to be made without being partially disposed in the source and drain regions of the transistors 100.
    The gates of the transistors 100 are then produced by depositing a layer 140 of high permittivity dielectric (greater than about 3.9, and corresponding, for example, to HfO 2, ZrO 2, TiO 2, ΙΆΙ 2 3, etc.) in the free spaces. 138 and 130, forming the grid dielectrics, then a conductive layer 142 for example metallic or comprising polysilicon filling the remaining space (Figure 12).
    Thus, the portions of the nanowires 120, 122 forming the channels of the transistors 100 are well surrounded by the grids, these grids not extending in the source and drain regions of the transistors thanks to the precise location of the second free spaces 138 delimited by the third portions 136 of the layer 126.
    Upper portions of the layers 140 and 142 previously deposited and which cover in particular the first portions 131 of the layer 126 are then etched until reaching the layer 126 (at the vertices of the first portions 131), thus forming third free spaces 144 located above the gates of the transistors 100 and formed in the layer 128 (Figure 13).
    When the conductive material of the grids (layer 142) is polysilicon, this material is then subjected to silicidation, forming silicided portions 146 which will serve as electrical contacts of the grids (FIG. 14).
    A layer of nitride is then deposited in spaces 144. Part of this layer also covers the upper face of the structure produced, that is to say also covers layer 128. A CMP is then implemented with a stop on the layer 128, thus forming dielectric portions 148 located in the third free spaces 144 and filling these third free spaces 144 (Figure 15).
    The portions of the layer 128 located above the future source and drain regions of the transistors 100 are then removed by stopping etching on the layer 126 (FIG. 16).
    As shown in Fig. 17, all portions of the dielectric layer 126, referred to as fourth portions 149, are not in line with the dielectric portions 148 or not covered by the remaining portions of the layer 128, and then second ion implantation, implemented in a manner analogous to the first ion implantation previously described in connection with Figure 10. Thus, the parts of the layer 126 protected by the dielectric portions 148 and which are not modified by the implementation this second ion implantation correspond to the third parts 136 and the first portions 131 of the layer 126 disposed around the gates of the transistors 100. This second ion implantation is implemented such that the ions are implanted in all parts of the layer 126 located in the future source and drain regions of the transistors 100, up to the portions of the layer 126 being between the layer 102 and the first nanowire 120. Because the dielectric portions 148 serve as a mask for this ion implantation, the upper portions 150 of the portions 148 are also modified by this ion implantation.
    The fourth portions 149 of the dielectric layer 126 modified by this ion implantation are etched selectively with respect to the parts 131, 136 which have not undergone the ion implantation, thus freeing spaces around second portions 151 of the nanowires 120, 122 which will be used to achieve the source and drain regions of the transistors 100 (Figure 18). This etching also removes the upper portions 150 of the dielectric portions 148 and the portions of the layer 140 disposed around these upper portions 150.
    An epitaxy is then implemented from the second portions 151 of the nanowires 120, 122 revealed by the previous etching, corresponding to the source and drain regions 152 of the transistors 100. In the example described here, the source / drain region 152 between the two grids made is common to the two transistors 100. The parts of the nanowires 120,122 which are not subject to this epitaxy correspond to the first portions 123 surrounded by the grids and gate spacers formed by the first parts 131 and the third parts 136 of the layer 126 (Figure 19). This epitaxy increases the semiconductor volume forming the source and drain regions 152, thus reducing the access resistances of the transistors 100.
    Transistors 100 are completed by siliciding the source and drain regions 152, forming silicided zones 154 for electrically contacting these regions 152 (FIG. 20).
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    Method for producing at least one transistor (100) with at least one semiconductor nanowire (120, 122), comprising at least the following steps: a) producing, on a support (102), at least one first semiconductor nanowire (120) having a first portion (123) for forming part of the transistor channel is partially covered by a sacrificial gate (114), the sacrificial gate and the first nanowire being surrounded by a first dielectric layer (126), b) removing the sacrificial gate, forming a first free space (130) around which are arranged first portions (131) of the first dielectric layer, c) first ion implantation of at least a second part (132) of the first dielectric layer disposed between the first portion of the first nanowire and the support, the first portions of the first dielectric layer protecting the third portions (136) of the first dielectric layer with respect to this first ion implantation, d) selectively etching the second portion of the first dielectric layer, forming a second free space (138), e) producing a grid (140, 142) in the first and second free spaces, and a dielectric portion (148) disposed on the grid and on the first portions of the first dielectric layer, f) second ion implantation of fourth portions (149) of the first dielectric layer surrounding second portions ( 151) of the first nanowire intended to form part of the source and drain regions (152) of the transistor, the dielectric portion protecting the first and third portions of the first dielectric layer vis-à-vis the second ion implantation, g) etching selectively the fourth portions of the first dielectric layer.
    [2" id="c-fr-0002]
    2. Method according to claim 1, wherein step a) comprises at least the implementation of the following steps: al) making, on the support (102), a stack of layers (104, 106, 108, 110) comprising at least a first layer of sacrificial material (104) and at least one second semiconductor layer (106), the sacrificial material being capable of being selectively etched with respect to the semiconductor of the second layer (106); ), a2) etching the stack of layers (104, 106, 108, 110), forming at least the first nanowire (120) disposed on a portion of the sacrificial material (104a), a3) producing the sacrificial gate (114) ) on the first portion (123) of the first nanowire (120) and against lateral flanks of the first portion (123) of the first nanowire (120) and a portion of the portion of sacrificial material (104a), a4) etching of the sacrificial material portion (104a), a5) depositing the first dielectric layer (126) a around the sacrificial gate (114) and the first nanowire (120).
    [3" id="c-fr-0003]
    3. Method according to claim 2, wherein step a3) comprises at least the implementation of the following steps: a31) depositing a sacrificial gate dielectric layer on the first nanowire (120) and against the lateral flanks the first nanowire (120) and the portion of the sacrificial material (104a), a32) depositing a layer of sacrificial gate conductive material covering the sacrificial gate dielectric layer, a33) making, on the layer of conductive material of sacrificial gate, a mask (118) in a pattern corresponding to that of the sacrificial gate (114), a34) etching the sacrificial gate dielectric layer and the layer of sacrificial gate conductive material according to the pattern of the mask (118), forming the sacrificial gate (114), and wherein the first dielectric layer (126) also covers the mask (118) disposed on the sacrificial gate (114).
    [4" id="c-fr-0004]
    4. The method of claim 3, further comprising, between steps a5) and b), a step of removing a portion of the first dielectric layer (126) disposed on the mask (118), then a step of withdrawal of the mask (118).
    [5" id="c-fr-0005]
    5. Method according to one of the preceding claims, wherein the first dielectric layer (126) surrounding the sacrificial gate (114) and the first nanowire (120) comprises at least one dielectric material whose dielectric permittivity is less than or equal to 7. .
    [6" id="c-fr-0006]
    6. Method according to one of the preceding claims, wherein step c) and / or step f) are carried out by plasma based on dihydrogen, or ion beam based on argon, fluorine or hydrogen.
    [7" id="c-fr-0007]
    7. The method of claim 6, further comprising, when step c) is implemented by ion beam, an annealing step capable of recrystallizing the semiconductor of the first portion (123) of the first nanowire (120). and implemented between steps c) and d).
    [8" id="c-fr-0008]
    8. Method according to one of the preceding claims, further comprising, between steps a) and b), the implementation of the steps of: - depositing a second dielectric layer (128) covering the formed assembly of the support (102), the first nanowire (120), the sacrificial gate (114) and the first dielectric layer (126), - planarizing the second dielectric layer (128) with a stop on the first dielectric layer (126), and wherein portions of the second dielectric layer (128) covering the fourth portions (149) of the first dielectric layer (126) are removed between the step of forming the gate (140, 142) and the second implantation step ionic.
    [9" id="c-fr-0009]
    The method of claim 8, wherein the dielectric portion (148) is formed in a third clear space (144) formed in the second dielectric layer (128).
    [10" id="c-fr-0010]
    10. Method according to one of the preceding claims, further comprising, when the gate (140, 142) comprises polysilicon, a siliciding step of an upper portion (146) of the polysilicon of the gate implemented between the steps e) and f).
    [11" id="c-fr-0011]
    11. Method according to one of the preceding claims, wherein the implementation of step g) also engraves a portion (150) of the dielectric portion (148) in which ions were implanted during implementation. of step f).
    [12" id="c-fr-0012]
    12. Method according to one of the preceding claims, further comprising, after step g), the implementation of an epitaxy of the source and drain regions (152) of the transistor (100) from the second portions. (151) of the first nanowire (120), followed by siliciding (154) of the source and drain regions (152).
    [13" id="c-fr-0013]
    13. Method according to one of the preceding claims, wherein: - step a) further produces at least a second semiconductor nanowire (122) disposed above the first nanowire (120) and a first portion ( 123) intended to form part of the channel of the transistor (100) is partially covered by the sacrificial gate (114), the first dielectric layer (126) also surrounding the second nanowire (122), - the second portion (132) of the first dielectric layer (126) further comprises a portion of the first dielectric layer (126) disposed between the first and second nanowires (120,122), - the fourth portions (149) of the first dielectric layer (126) also surrounds second portions ( 151) of the second nanowire (122) to be part of the source and drain regions (152) of the transistor (100).
    [14" id="c-fr-0014]
    14. Method according to one of the preceding claims, wherein the sacrificial gate (114) and the gate (140, 142) each comprise a plurality of separate portions spaced apart from each other.
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1561044A|FR3043837B1|2015-11-17|2015-11-17|METHOD FOR PRODUCING A SEMICONDUCTOR NANOFIL TRANSISTOR COMPRISING A SELF-ALIGNED GRID AND SPACERS|FR1561044A| FR3043837B1|2015-11-17|2015-11-17|METHOD FOR PRODUCING A SEMICONDUCTOR NANOFIL TRANSISTOR COMPRISING A SELF-ALIGNED GRID AND SPACERS|
    US15/352,198| US9853124B2|2015-11-17|2016-11-15|Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers|
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