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    • 专利摘要:
    A content addressable memory (CAM) comprising at least one CAM cell (100) comprising: first and second inverters (102, 104) cross-coupled between first and second storage nodes (V1, V2) ; a first transistor (114) coupling the first storage node (V1) to a bit line (BLL), the first transistor (114) being controlled by a first control signal (WL1); a second transistor (116) coupling the second storage node (V2) to the bit line (BLL), the second transistor (116) being controlled by a second control signal (WL2); and a control circuit (118) adapted to perform a CAM read operation by pre-charging the bit line (BLL) to a first voltage level, and then selectively activating the first or second transistor based on a input data bit (DIN).
    公开号:FR3043488A1
    申请号:FR1560605
    申请日:2015-11-05
    公开日:2017-05-12
    发明作者:Navneet Gupta；Adam Makosiej；Costin Anghel；Amara Amara；Olivier Thomas
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    CSM RECONFIGURABLE
    Field
    The present disclosure relates to the field of content addressable memories (CAMs) and a method for performing a CAM read operation.
    Presentation of 11 prior art
    A content addressable memory (CAM) is a device capable of comparing an input data word with data words stored in its memory array, and returning a failure information each time a word in the memory does not match the input data word, and success information each time a word in the memory matches the input data word.
    It is generally desirable for CAM devices to be capable of fast operations, since for each CAM read operation all words in the memory array are generally accessed to generate a success or failure value for each word of the matrix. To enable fast operation, the comparison of the bits of an input word with the bits stored in the CAM is performed in each memory cell of the CAM. This results in the memory cells of a CAM being more complex and larger than those of a conventional SRAM (Random Access Memory) cell.
    In some applications, the CAM function is not always necessary, and there is therefore a need in the art for a CAM that can be fully or partially used as SRAM during periods when the CAM function is not required. In addition, there is a need in the art for a relatively compact CAM cell. summary
    An object of embodiments of the present disclosure is to at least partially solve one or more needs of the prior art.
    In one aspect, there is provided a content addressable memory (CAM) comprising at least one CAM cell comprising: first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bit line, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bit line, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-loading the bit line at a first voltage level, and then selectively activating the first or second transistor based on an input data bit .
    According to one embodiment, the CAM further comprises a detection circuit adapted to detect a success or a failure of CAM as a function of the voltage level on the bit line, or on a first supply voltage rail of the first and second inverter, following the activation of the first or second transistor.
    According to one embodiment, the detection circuit is coupled to the bit line.
    According to one embodiment, the detection circuit is coupled to the first supply voltage rail of the first and second inverters.
    According to one embodiment, the CAM further comprises a plurality of said CAM cells coupled to the bit line, the plurality of CAM cells forming a CAM word, and the input data bits of the plurality of CAM cells form a word , and the detection circuit is adapted to detect a success or a word failure depending on the voltage level on the bit line, or on the first supply voltage rail, following the activation of the first or second transistor.
    According to one embodiment, the detection circuit is adapted to detect a success by detecting a voltage change lower than a first threshold, and to detect a failure by detecting a voltage change greater than the first threshold.
    According to one embodiment, the control circuit is further adapted to perform an SRAM read operation of a data value stored on the first and second storage nodes by pre-loading the bit line at the first voltage level or to another of voltage level, and activating the first transistor.
    According to one embodiment, the control circuit is further adapted to perform a write operation on the first and second storage nodes of the at least one CAM cell by coupling the bit line to the first voltage level or to a second one. another voltage level while selectively activating the first or second transistor based on a data bit to be written in the CAM cell.
    According to one embodiment, the bit line comprises first and second portions, the first transistor being coupled to the first portion and the second transistor being coupled to the second portion, the first and second portions being coupled together by another transistor. , the control circuit being adapted to perform a write operation in said at least one memory cell by deactivating the other transistor and applying independent voltages to the first and second portions.
    According to one embodiment, the first and second inverters of said at least one CAM cell are coupled between a first supply voltage rail at the first voltage level and a second supply voltage rail at a second higher voltage level. at ground and below the first voltage level, and during a write operation in said at least one CAM cell, one of the first and second transistors is activated by a voltage lower than the first power supply voltage.
    According to one embodiment, said at least one CAM cell further comprises: a third transistor coupled between the second storage node and another bit line, the third transistor being controlled by the second control signal; and a fourth transistor coupled between the first storage node and the other bit line, the fourth transistor being controlled by the first control signal, the first, second, third and fourth transistors being TFETs (field effect transistors). tunnel effect).
    According to one embodiment, said at least one CAM cell further comprises a fifth transistor coupled between the other bit line and a read output line, a control node of the fifth transistor being coupled to the second storage node.
    According to one embodiment, the CAM comprises at least one other CAM cell coupled to the bit line by a first transistor controlled by a first control signal and by a second transistor controlled by a second control signal, the control circuit being adapted to mask said at least one other CAM cell during the CAM read operation by deactivating both the first and second transistors of said at least one other CAM cell during the CAM read operation.
    In another aspect, there is provided a method for performing a CAM (Content Addressable Memory) operation in at least one CAM cell, comprising: first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bit line, the first transistor being controlled by a first control signal; and a second transistor coupling the second storage node to the bit line, the second transistor being controlled by a second control signal, the method comprising: preloading, by a control circuit, the bit line at a first voltage level ; and selectively enabling, by the control circuit, either the first or the second transistor based on an input data bit.
    According to one embodiment, the method further comprises: detecting by a detection circuit, success or failure depending on the voltage level on the bit line, or on a supply rail of the first and second inverters, continued at the activation of the first or second transistor.
    In another aspect, there is provided a memory comprising a plurality of memory cells coupled to a bit line, each memory cell comprising: first and second inverters cross-coupled between first and second storage nodes; and a first transistor coupling the first storage node to the bit line, the memory further comprising a detection circuit adapted to read data bits stored by the memory cells, the detection circuit being coupled to a first voltage rail supplying the first and second inverters of each memory cell. For example, the detection circuit is adapted to detect the presence or absence of a voltage rise or a voltage drop on the first supply voltage rail.
    Brief description of the drawings
    The foregoing and other features and advantages will be apparent from the following detailed description of embodiments, given as non-limiting and illustrative, with reference to the accompanying drawings in which: Figure 1 schematically illustrates a cell; CAM according to an exemplary embodiment; Fig. 2A is a timing chart illustrating examples of signals in the CAM cell of Fig. 1 during CAM write operations according to an exemplary embodiment; Fig. 2B is a timing chart illustrating examples of signals in the CAM cell of Fig. 1 during CAM read operations according to an exemplary embodiment; FIG. 3A schematically illustrates a CAM cell according to another exemplary embodiment; FIG. 3B schematically illustrates a CAM cell according to yet another embodiment; Figure 4Ά schematically illustrates a control line driver of a control circuit of Figures 1 to 3A in more detail according to an exemplary embodiment; FIG. 4B schematically illustrates in more detail a bit line driver of the control circuit of FIG. 1 according to an exemplary embodiment; FIG. 5A schematically illustrates a reconfigurable CAM / SRAM matrix comprising CAM cells of FIG. 3A according to an exemplary embodiment; Figure 5B schematically illustrates the reconfigurable CAM / SRAM matrix of Figure 5A in more detail according to an exemplary embodiment; FIG. 6 schematically illustrates a CAM cell according to yet another embodiment; FIG. 7 schematically illustrates a reconfigurable CAM / SRAM matrix comprising CAM cells of FIG. 6 according to an exemplary embodiment; FIG. 8 schematically illustrates a reconfigurable CAM / SRAM matrix comprising CAM cells of FIG. 6 according to another exemplary embodiment; Figure 9A schematically illustrates a column of CAM cells according to an exemplary embodiment; and Fig. 9B is a timing chart illustrating examples of signals in the circuit of Fig. 9A.
    detailed description
    Although in the following description we describe CAM cells and CAM matrices that can be used as standard SRAM devices, it will be clear to those skilled in the art that for some applications these matrices can be configured to operate exclusively as CAMs. .
    The term "connected" is used herein to refer to a direct electrical connection between two components, while the term "coupled" is used to refer to a connection that may be direct or may be via one or more other components such as resistors, capacitors or transistors. The term "around" is used to denote a tolerance of +/- 10% around the value in question.
    Figure 1 schematically illustrates a CAM cell 100 according to an exemplary embodiment. The cell comprises for example a storage portion formed by cross-coupled inverters 102, 104 which form a flip-flop structure. Inverters 102, 104 are cross-coupled between storage nodes VI, V2. For example, the inverter 102 includes transistors 106 and 108 coupled by their main conduction nodes between a supply voltage rail VDD and a supply voltage rail VSS. An intermediate node between the transistors 106, 108 forms the storage node VI, and the control nodes of the transistors 106, 108 are coupled to the storage node V2. The inverter 104 comprises for example transistors 110 and 112 coupled by their main conduction nodes between the supply voltage rails VDD and VSS. An intermediate node between the transistors 110, 112 forms the storage node V2, and the control nodes of the transistors 110, 112 are coupled to the storage node VI.
    The storage node VI is coupled to a bit line BLL via the main conduction nodes of a transistor 114. Similarly, the storage node V2 is coupled to the bit line BLL via the main conduction nodes of a transistor 116. The transistor 114 is controlled at its control node by a control signal WL1, and the transistor 116 is controlled at its control node by a control signal WL2, the control signals WL1, WL2 being for example word line control signals for controlling SRAM words, as will be described in more detail below. Transistors 106 to 116 are, for example, MOS transistors, transistors 114 and 116 being, for example, N-channel MOS transistors (NMOS) having their gates connected to signals WL1 and WL2, respectively. A source / drain node of the transistor 114 is for example connected to the node VI and a source / drain node of the transistor 116 is for example connected to the node V2.
    The control signals WL1 and WL2 are, for example, generated by a control circuit (CTRL) 118, which receives, for example, an input data value and read and write authorization signals RE and WE. The control circuit 118 also applies for example voltages to the bit line BLL, to preload the bit line, and couple the bit line to a supply voltage, as will be described in more detail below.
    The bit line BLL is for example coupled to a detection circuit (SA + MATCH) 120 performing the functions of a detection amplifier and a matching detection circuit. The detection circuit 120 for example generates, on the basis of a voltage level detected on the bit line BLL, an output data signal Dqut during a standard SRAM read operation, or a success / failure signal of CAM, MOUT 'during a read operation in CAM mode.
    For example, the CAM 100 may be reconfigured to function as. a CAM cell, involving read and write operations in CAM mode, to function as an SRAM cell, involving SRAM read and write operations.
    The voltage supply rail VDD of the cell CAM 100 is for example at a voltage of between 0.6 V and 1.4 V, and for example at about 1.2 V. The supply voltage rail VSS is for example at a voltage between -0.6 V and 0.6 V, and for example at about 0.6 V, and the voltage difference between the supply voltage rails VDD and VSS is for example equal to minus 0.6 V, and for example equal to about 0.8 V.
    During a mode of retention of the cell CAM 100, the control signals WL1 and WL2 are for example at the voltage level VSS and the bit line BLL is for example at the level of voltage VSS or VDD or at any level between the two, so that there is a low leakage current from the cell to the bit line.
    During write operations in CAM and SRAM mode described in more detail below, the bit line BLL is for example brought to ground or at a lower voltage, and one of the control signals WL1, WL2 is activated. by a voltage equal for example to a level between the mass and VDD as VSS, which is for example equal to about VDD / 2. The term "activated" in relation to a control signal is used herein to refer to a state of the control signal that turns one or more transistors to which it is coupled. The other control signal is for example deactivated by bringing it to ground.
    During read operations in CAM or SRAM mode, the bit line BLL is for example brought to the voltage level VDD, and one of the control signals WL1, WL2 is activated by bringing it to the voltage level VDD. The other control signal is for example disabled by bringing it to the voltage level VSS.
    The operation of the CAM cell 100 of FIG. 1 will now be described in more detail with reference to FIGS. 2A and 2B.
    Fig. 2A is a timing chart illustrating an example of the input data signal Dj ^, the voltage on the bit line BLL, and control signals WL1 and WL2, during a write operation in CAM mode in the cell CAM 100. It will be assumed in this example that the CAM cell 100 is coupled to a single bit line BLL.
    It will be assumed that during the write operation in CAM mode the write enable signal WE is activated. In a first example, a value "1" is written in the CAM cell, and thus the data signal Dj ^ is high during the write operation.
    During the write operation in CAM mode, the control circuit 118 applies, for example, a voltage V.sub.bl to the bit line BLL, V.sub.bl being, for example, less than VSS and equal to the ground or to a voltage comprised between 0 V and the voltage level VSS. Alternatively, the bit line BLL could be brought to a negative level, for example using a SRAM write assist technique known in the art as negative bit line write assistance ( NBL-WA). In addition, during the write operation, the supply voltage VDD can be reduced, for example by about 0.1 V, corresponding to a power reduction SRAM write assistance technique (Vddud -WA). Although the bit line BLL is at a reduced level, the control circuit 118 activates the control signal WL1 or WL2 on the basis of the data signal to be stored in the cell. The control signal WL1 or WL2 is for example activated by bringing it to the VSS level.
    As shown on the left in FIG. 2A, in the case where the data signal has a value "1", the control signal WL2 is for example activated in order to pull the voltage on the node V2 to a low level, and causing the flip-flop formed by the inverters 102, 104 to switch to a state in which VI is high and V2 is low. For example, to store a write data of "1", a voltage of about 0.6 V is applied to the command line WL2, and a voltage of about 0 V is applied to the command line WL1. In the case where the transistors 114, 116 are NMOS transistors, they are for example activated by high levels on the control signals WL1, WL2. On the other hand, if these transistors were PMOS transistors, they would be activated by a low level of the control signals WL1, WL2.
    FIG. 2A also illustrates on the right an example of writing a value "0" in the CAM cell, which for example involves the activation of the control signal WL1 during the write operation, to draw the voltage on node VI at a low level. For example, to store a write data of "0", a voltage of about 0.6 V is applied to the command line WL1, and a voltage of about 0 V is applied to the command line WL2.
    In alternative embodiments, it would be possible to write in the CAM cell 100 by applying to the bit line BLL a raised voltage higher than VDD, and by activating the control signal WL1 or WL2 to bring the node VI or V2 to a high level. In such a case, the transistors 114 and 116 are for example implemented by PMOS transistors.
    The CAM cell 100 is for example part of a matrix, with a plurality of cells arranged in a column and coupled to a common bit line, and a plurality of columns. For example, each column of cells forms a CAM word. Cells in each row of columns share common control lines WL1 and WL2. During a write operation, a CAM word of memory cells is for example written in one go, and the other columns of CAM cells are for example half selected to avoid writing in them. To half select the CAM cells of a column, the bit line of the column is for example brought to a voltage of about the level of VSS.
    Fig. 2B is a timing diagram illustrating an example of the input data signal Dj ^, the voltage on the bit line BLL, the control signals WL1 and WL2, and the output signal Mqut during a read mode operation. CAM in the cell CAM 100. It is assumed in this example that the CAM cell 100 is coupled to a single bit line BLL.
    In a first example shown on the left in FIG. 2B, the data bit stored in the CAM cell 100 must be compared with a value "1". Thus the input data signal Dj ^ is for example high during the read operation CAM. At the beginning of the read operation CAM, the bit line BLL is for example preloaded at the VDD level, for example at a level of approximately 1.2 V. One of the control signals WL1, WL2 is then activated on the base of the input data bit Dj ^ to compare. For example, the control signal WL1 or WL2 is activated by bringing it from the voltage level VSS to the voltage level VDD. Alternatively, a SRAM read assist technique such as WLud-RA assistance can be used, in which case the activated command line WL1 or WL2 is, for example, a level of about 0.2 V below VDD, for example at a level of about 1 V. The other control signal is for example disabled by bringing it to the voltage level VSS.
    As shown on the left in FIG. 2B, for a read operation in CAM mode on the basis of a value "1" of the input data, the control signal WL1 is for example activated so as to couple the node VI to the BLL bit line. In the example of FIG. 1, the storage node VI is in a high state, and thus the voltage on the bit line BLL remains high, for example. In general, a CAM read operation will involve comparing a plurality of bits on an input data word to a word stored in a corresponding plurality of CAM cells of a column of the CAM array. So in general, if the voltage on the bit line stays high this will indicate a word success.
    As shown on the right in FIG. 2B, for a read operation in CAM mode on the basis of a value "0" of the input data, the control signal WL2 is for example activated in order to couple the node V2 to the BLL bit line. In this case, it is again assumed that the node VI is in a high state, and thus the node V2 is in a low state. Thus, shortly after the control signal WL2 has been activated, the voltage on the bit line BLL begins, for example, to go down, and the voltage drop, which can be a drop of only 100 mV, is for example detected. by a detection amplifier of the detection circuit 120. Thus, the signal Mqut remains low, for example, indicating a failure of CAM.
    An SRAM read operation involves providing the data value stored by the CAM cell 100 to provide an output data value Dqut · This operation is not shown in the figures, and for example involves preloading the bit line BLL to VDD, then activate the control signal WL1 to couple the node VI to the bit line BLL, and detect by the detection circuit 120 if the voltage on the bit line BLL remains at or near the VDD, or if it goes down. A horizontal word of the matrix is for example read in a single operation.
    When the CAM cell 100 is part of a matrix as previously described, the CAM cells of each CAM word will share common control lines WL1, WL2 with the corresponding cells of the other columns, and so a CAM search can be performed in a single operation on the entire matrix.
    In some embodiments, global masking may be performed while performing the CAM read operation. In particular, a CAM search can be carried out on the basis of only certain bits of a word, one or more other bits of the word being set to a "disregard" state while keeping off the two signals WL1 and WL2 associated with these bits. Further, in some embodiments, mask bits for partial comparison may be stored in an SRAM separate from the CAM memory, similar to that disclosed in US Patent No. 6,839,256, of which the content is included here as a reference within the limits permitted by law.
    In some embodiments, each column of the CAM memory can store a plurality of words, and during each CAM search, only one of the words of each column is for example searched at a time, the other words being masked by deactivating the WL1 signals. and corresponding WL2.
    FIG. 3A illustrates a CAM cell 300 according to an alternative embodiment with respect to FIG. 1. Many elements of FIG. 3A are the same as elements of FIG. 1, and these elements bear the same references and will not be described. again in detail.
    In the circuit of FIG. 3A, the bit line BLL is separated into two portions BLL-A and BLL-B. The transistor 114 is coupled between the storage node VI and the bit line portion BLL-A, the transistor 116 is coupled between the storage node V2 and the bit line portion BLL-B. Bit line portions BLL-A and BLL-B are for example coupled together by a transistor 302, which is for example a MOS transistor. Transistor 302 is for example common to an entire column. The transistor 302 is for example controlled at its control node so that it is activated at least during the CAM read operations. In some embodiments, as shown in FIG. 3A, the transistor 302 is controlled by the reverse of the write enable signal WE, so that bit line portions BLL-A and BLL-B are coupled together except during write operations. The detection circuit 120 is for example coupled to only one of the bit line portions BLL-A, BLL-B, and in the example of Figure 3A it is coupled to the bit line portion BLL-A. CAM and SRAM read operations are for example performed in the same manner as previously described in connection with Figure 1, with the transistor 302 activated.
    The write operations in the CAM cell of FIG. 3A are for example performed in a manner similar to a standard SRAM write operation using bit line portions BLL-A and BLL-B. During write operations, the transistor 302 is for example deactivated so that the bit line portions BLL-A and BLL-B can be driven independently. During a write operation, the control circuit 118 is for example adapted to couple one of the bit line portions BLL-A, BLL-B to the supply voltage VDD on the basis of the data to be written in the cell, and coupling the other bit line portion to the ground voltage, while activating the two control signals WL1, WL2. In this way, during the write operations, a row of the matrix can be written in a single operation.
    FIG. 3B illustrates a CAM cell 310 according to an alternative embodiment with respect to FIGS. 1 and 3A. The CAM cell of Figure 3B is very similar to the circuit of Figure 1, and includes transistors 114 and 116, each coupled to the BLL bit line. The embodiment of FIG. 3B also comprises another bit line BLR, and a transistor 312 coupling the storage node V2 to the bit line BLR, and a transistor 314 coupling the storage node VI to the bit line BLR. The transistor 312 is controlled by the control signal WL1, and the transistor 314 is controlled by the control signal WL2. The control circuit 118 in FIG. 3B for example applies voltages to the two bit lines BLL and BLR.
    In the cell CAM 310, all the transistors are TFET devices (tunnel effect field effect transistor). Such devices have the advantage of a very low current leakage. The TFET devices lead in a single direction, indicated in FIG. 3B by an arrow associated with each device. Transistors 114 and 116 are for example arranged to lead from bit line BLL to storage nodes VI and V2 respectively. The transistors 106, 108, 110 and 112 are arranged to lead from the supply voltage rail VDD to the GND ground supply rail. Transistors 312 and 314 are arranged to lead from storage nodes VI and V2 respectively to the bit line BLR.
    The operation of the CAM cell 310 is similar to that of the CAM cell 100 of FIG. 1. However, during a write operation in CAM mode, the bit line BLL is for example brought to the supply voltage level V DD. for example equal to 1 V, and the bit line BLR is brought to ground. The control line WL1 or WL2 is then activated by a voltage of about VDD, based on the data bit to be stored in the CAM cell. The CAM cells of other columns of the matrix are for example half selected by an intermediate level applied to their bit lines BLR, for example 0.6 V. In addition, during a read operation in CAM mode, the line BLR bit is for example at the intermediate level, for example 0.6 V. During an SRAM write, the writing operation is for example carried out in two phases, a phase for writing a value "0" in the CAM cells of a row of the matrix to write, and a phase to write a value "1" in the CAM cells of the row.
    For example, in a first phase, the cells of the row where to write a "1" are selected by coupling their bit line BLL to the voltage VDD, and their bit line BLR to the ground voltage. The other memory cells of the row are for example half selected by coupling their BLR bit lines to an intermediate level, for example equal to about 0.6 V. The signal WL1 is then activated but not the signal WL2, in order to write a value "1" in the selected memory cells.
    In a second phase, the cells of the row to write a "0" are selected by coupling their bit line BLL to the voltage VDD and their bit line BLR to the ground voltage. The other memory cells of the row are for example half selected by coupling their BLR bit lines to an intermediate level, for example equal to about 0.6 V. The signal WL2 is then activated but not the signal WL1, in order to write a value "0" in the selected memory cells.
    During an SRAM read operation, the bit lines BLL are pre-loaded to VDD and the bit lines BLR are brought to an intermediate level, for example to 0.6 V. The signal WL1 is then for example activated for the row. read, and the voltages on the BLL bit lines will indicate the data read.
    FIG. 4A schematically illustrates an exemplary embodiment of a certain portion 400 of the control circuit 118 of FIGS. 1 and 3A for generating the control signals WL1, WL2. The circuit 400 is for example common for all the CAM cells of a row of a matrix, and a similar circuit is for example provided for each other row.
    The line WL1 is for example coupled to the ground (GND) via a transistor 402, and to an intermediate node 404 via a transistor 406. The intermediate node has a voltage Vdlnt, and is coupled to the supply rail VDD via a transistor 408, and to a supply rail VDDH via a transistor 410. The supply rail VDDH is for example at a voltage level lower than VDD and greater than ground, so that 0 <VDDH <VDD. For example, in one embodiment, VDDH is about half of VDD. The transistor 408 is controlled by the write enable signal WE, and the transistor 410 is controlled by the inverse WEb of the write enable signal WE.
    The transistors 402, 406 have their control nodes coupled to a node 412, which in turn is coupled to the VDD supply rail through a transistor 414, at a node 416 via a transistor 418, and to a node 420 via a transistor 422. The transistor 414 is for example controlled by a precharge signal PreChg, the transistor 418 is controlled by the read authorization signal RE, and the Transistor 422 is controlled by the write enable signal WE.
    The line WL2 is for example coupled to the ground rail GND via a transistor 424, and to the voltage Vdlnt on the node 404 via a transistor 426. The transistors 424, 426 have their nodes control coupled to a supply node VDD through transistor 430, at node 416 via transistor 432 and at node 420 through The transistor 430 is controlled by the precharge signal PreChg, the transistor 432 is controlled by the write enable signal WE, and the transistor 434 is controlled by the read authorization signal RE .
    The node 416 is coupled to the ground rail GND via a transistor 436 controlled by the data value Dj ^, and the node 420 is coupled to the ground rail GND via a transistor 438 controlled by the inverse DbjN of the data value Dj ^.
    Transistors 402, 418, 422, 424, 432, 434, 436 and 438 are, for example, NMOS transistors, and transistors 406, 408, 410, 414, 426 and 430 are, for example, PMOS transistors.
    In operation, during a write operation, first the pre-charge signal PreChg is activated at a low level to bring the nodes 412 and 428 to VDD. The signals WE and PreChg are then, for example, brought to the high level, and the signals WEb and RE are, for example, brought to a low level. Thus, if the data value is at a value "1", the line WL2 is coupled to the voltage Vdlnt, which is at VDDH, and the line WL1 is coupled to ground. is a value "0", the line WL1 is coupled to the voltage Vdlnt, which is VDDH, and the line WL2 is coupled to ground.
    When a read operation in CAM mode is to be performed, the PreChg signal is first activated at a low level to bring the nodes 412 and 428 to VDD. Then, the PreChg signal is brought back to the high state, and the RE signal is raised to the high state, while the WE signal is low. Thus, the line WL1 will be coupled to VDD if the input data value Djn is "1", and the ground if the input data value Djn is "0". Conversely, the line WL2 will be coupled to VDD if the input data value Dj ^ is "0", and ground if the input data value Djjj is "1".
    The circuit 400 may for example be adapted to implement a certain portion of the control circuit 118 of the CAM cell 310 of Figure 3B by removing the transistors 408 and 410, and coupling the node 404 directly to VDD.
    FIG. 4B schematically illustrates an exemplary implementation of a certain portion 450 of the control circuit 118 of FIG. 1 for controlling the voltage on the bit lines BLL [0] and BLL [1] of adjacent columns 0 and 1 of the matrix.
    The bit line BLL [0] is for example coupled to the voltage rail V] jbl via a transistor 452 [0] associated with the column 0 and which is controlled by a signal WWO, and the line of BLL bit [1] is coupled to the voltage rail Vjjbl through a transistor 452 fl] associated with the column 1 controlled by a signal WW1. The signals WW0 and WW1 are data signals based on the data to be written in the selected CAM cells of the corresponding columns 0 and 1. The voltage rail V ^ gg is for example at ground, or at a negative voltage level.
    The bit line BLLfO] is also coupled to a node 454 via a transistor 456 [0] associated with the column 0, and the bit line BLLfl] is also coupled to the node 454 via a transistor 456 [1] associated with the column 1. The node 454 has a voltage Vdlnt, which is the same voltage as on the node 404 of FIG. 4A, and is for example generated by the same circuit comprising the transistors 408, 410 , which will not be described again in detail. Transistors 456 [0], 456 [1] are controlled by PrechgBL preload signal ion. Thus, when the bit lines BLLf0, BLLfl] must be preloaded to VDD during a CAM mode or an SRAM read operation, the PrechgBL signal is turned on at a low level to make the transistors 456 [0] and 456 [1] conductors, and the write enable signal WE is low, so that the node 454 is coupled to the supply rail VDD. A pair of transistors 452 [], 456 [] is for example provided for each column p of the matrix.
    As with the circuit 400, the circuit 450 may for example be adapted to implement a certain portion of the control circuit 118 of the CAM cell 310 of FIG. 3B by removing the transistors 408 and 410, and by coupling the node 454 directly. at VDD. A similar circuit may be provided for coupling the BLR bit line to either ground or 0.6V.
    In the case of the CAM cell 300 of FIG. 3A, the circuit 450 comprises, for example, a transistor 452 [] for each of the bit line portions BLL-A, BLL-B of each column p, so that the portions bit line can be controlled independently during a write operation.
    Figure 5A schematically illustrates a CAM array 500 comprising a matrix of CAM cells, which are for example the CAM 300 cells of Figure 3A coupled to the separate bit line portions BLL-A and BLL-B. However, a configuration similar to that of FIG. 5A could be adapted to the memory cell of FIG. 1. The matrix 500 comprises for example a plurality of P + 1 columns, each column storing a CAM word, and each column for example comprising a plurality of N + 1 memory cells forming the word CAM. In addition, each row of P + 1 CAM cells form for example an SRAM word. P and N are both for example equal to 1 or more, and typically there are for example 16, 32 or 64 columns, and 16, 32 or 64 rows. In some embodiments, the number of rows is equal to the number of columns, so that a CAM word is equal in length to an SRAM word. However, in alternative embodiments, there could be a different number of rows compared. to the number of columns.
    The separated bit line portions BLL-A, BLL-B of each column 0 to P are for example coupled together by corresponding transistors 302-0 to 302-P controlled for example by the inverse of the authorization signal d WE write. Indeed, as explained above in connection with FIG. 3A, these transistors are for example deactivated at least during the write operations in the memory cells so that the cells can be written in a standard SRAM manner.
    FIG. 5B schematically illustrates the matrix of FIG. 5A in more detail according to an exemplary embodiment, and illustrates an example of a control circuit for controlling the CAM cells of the matrix.
    A driver circuit WL (WL DRIVERS + WL LOGIC) 504 comprises, for example, control and logic circuits for controlling the word lines WL10, WL20 to WL1N, WL2N of the matrix.
    A bit line control circuit (BL DRIVERS) 506 comprises, for example, control devices for controlling the bit line portions BLL-A, BLL-B of the columns 0 to P of the matrix.
    During SRAM read and write operations to be performed in a row of the array, a row decoder (ROW DECODER (SRAM, READ & WRITE)) 508 for example receives the address ADDR of the operation, and provides a suitable selection of one of the word lines to the driver circuit WL 504. In the case of an SRAM write operation, a bit line selection logic (BL SELECTION LOGIC (SRAM, WRITE)) receives for example also the data DATA to be written, and provides appropriate control signals to the bit line driver circuit 506 to drive the bit lines accordingly and to disable the transistors 302-0 to 302-P.
    During read and write operations CAM to be performed in a column of the matrix, a selection logic WL (WL SELECTION LOGIC (CAM)) 512 for example receives the data DATA to be written or used for the CAM reading, and provides the appropriate signals for driving the word lines WL10, WL20 to WL1N, WL2N based on these data. For example, the selection logic WL 512 is implemented by the circuit of FIG. 4A. During CAM write operations, a column decoder (COLUMN DECODER (CAM, WRITE)) 514 for example receives the address ADDR of the write operation, and supplies the appropriate control signals to the line driver bit 506 to drive the corresponding bit lines accordingly. The column decoder 514 is for example implemented by the circuit of FIG. 4B.
    For example, during a CAM read operation, an output circuit (MQT or DQT) 516 provides the success or failure signal MQT from each column of the array, and during an SRAM read operation, the signal of Dqut data from each column of the matrix.
    In some embodiments, a multiplexer (COLUMN MUX (SRAM, READ)) 518 is provided for SRAM read operations.
    FIG. 6 schematically illustrates a CAM 600 cell according to another exemplary embodiment. The circuit of FIG. 6 is similar to that of the CAM cell 310 of FIG. 3B, and the same elements carry the same references and will not be described again in detail. The CAM cell 600 further comprises a TFET transistor 602, which is for example an NTFET transistor, coupled by its main current nodes between the bit line BLR and a row line RBL. The transistor 602 has for example its control node coupled to the storage node V2 of the cell. Adding transistor 602 makes it possible, for example, to read a column of cells during an SRAM read operation. Thus, CAM words and SRAM words can all be oriented in the same way in the matrix, in the column direction. The circuit includes, for example, another detection circuit (SRAM READ SA) 604 for detecting the voltage on the row line RBL, and providing an output data Dqut on - * - based on the detected voltage level. The detection circuit 120 in FIG. 6 provides, for example, only the concordance signal M ·
    In operation, during an SRAM read operation, the row line RBL is for example preloaded to VDD, and the bit line BLR is for example coupled to ground. The transistor 602 will be turned on or off depending on the voltage on the storage node V2, and when it is conducting it will discharge the voltage on the row line RBL. Thus, a value "1" on the storage node VI can be detected, by the detection circuit 604, by detecting when the voltage state on the row line RBL remains close to VDD, and a value "0" on the storage node VI can be detected by detecting when the voltage state on the row line RBL goes down, for example a value of 100 and 200 mV for a supply of 1 V.
    FIG. 7 schematically illustrates a CAM array 700 comprising the CAM 600 cells of FIG. 6 arranged in N + 1 rows and P + 1 columns. As illustrated, each bit line BLL0 through BLLP is coupled to a corresponding detection circuit 120 providing the match signal Mqut and each row line RBL0 to RBLN is coupled to a corresponding detection circuit 604 to provide the read signal. SRAM Dqut · A control circuit block WL (WL DRIVERS + WL LOGIC) 704 for example controls control lines WL10, WL20 to WL1N, WL2N, and a bit line control circuit block (ROW DECODER + BL DRIVING LOGIC (CAM & SRAM)) 706 driver for example bit lines BLL0, BLR0 to BLLP, BLRP, and row lines RBL0 to RBLN. A column decoder (COLUMN DECODER (SRAM)) 708 is also for example provided for selecting the column to be written or read during an SRAM write or read operation.
    Note that the matrix 700 allows both the CAM words and the SRAM words of the array to be vertically stored in columns, but that it includes a higher number of detection circuits than the array of FIG. 5B.
    FIG. 8 diagrammatically illustrates a matrix 800 comprising the CAM cells 600 of FIG. 6 according to an exemplary variant embodiment in which the number of detection circuits is reduced compared with the matrix 700 of FIG. 7. The matrix 800 is similar to matrix 700, but no longer includes sense circuits 604, and instead includes two-input multiplexers 802-0 through 802-p associated with rows 0 through P, and each having an input coupled to a bit line Corresponding BLL0 to BLLP, and another input coupled to a corresponding row row RBL0 to RBLN. In this example, P and N are equal, although in alternative embodiments any value of P and N would be possible. The outputs of the multiplexers are respectively coupled to the detection circuitry (SA + MATCHO to SA + MATCHP) 120, which provides both the matching output signals MUT and the data output signals DQT · The column decoder 708 of the Figure 7 is for example used only for SRAM access operations, while the decoder 708 of Figure 8 is for example used for SRAM and CAM operations.
    FIG. 9A schematically illustrates a column 900 of memory cells 100 according to another exemplary embodiment. In alternative embodiments, the column 900 could be adapted to include the memory cells 300 of FIG. 3A.
    The column 900 is for example part of a matrix comprising a plurality of such columns. The detection circuit 120 of FIG. 1 coupled to the bit line BLL is replaced in FIG. 9A by a detection circuit (SA + MATCH) 902 coupled to a supply voltage rail 904 of each memory cell of the column. For example, the detection circuit 902 is coupled to the supply voltage rail VSS 904, and the VSS rail 904 is for example coupled, at the foot 906 of the column, to the supply voltage VSS via of a diode-mounted transistor 908, so that the voltage on the rail 904 may be allowed to increase above VSS during a read operation. For example, the transistor 908 is an NMOS transistor having its gate coupled to its drain. The VSS rail 904 is also for example coupled to the supply voltage VSS via a transistor 910, which is for example an NMOS transistor controlled by the inverse of the read authorization signal RE. Thus, the VSS supply rail 904 is coupled to the supply voltage VSS except during read operations.
    The operation of the CAM 900 of FIG. 9A will now be described in more detail with reference to FIG. 9B.
    Fig. 9B is a timing chart illustrating examples of the word line signal WL1 or WL2, the bit line voltage, and the voltage SI on the VSS supply rail 904 during a CAM read operation. The voltage on either one of the line WL1 and the line WL2 is supplied to the supply voltage VDD as a function of the input data during the read operation CAM. For example, the bit line BLL is coupled to a high voltage such as the supply voltage V DD. In the case of a CAM success, the high voltage storage node, which is coupled to the supply voltage VDD, will be coupled to the bit line BLL, and so there will be no change in the voltage state on the VSS supply rail. However, in the case of a failure CAM, the storage node storing a low voltage, which is coupled to the supply voltage rail VSS, will be loaded by the voltage on the bit line BLL. FIG. 9B illustrates the case of a failure CAM, and as illustrated, the rise of the voltage on the storage node will cause the voltage on the supply rail VSS to start to rise, for example about 100 mV or a few hundred mV. This rise in voltage is detected by the detection circuit 902, and the output signal Mqut For example remains low to indicate a failure of CAM.
    Although FIG. 9B illustrates the case of a CAM read operation, the detection circuit 902 can also be used for SRAM read operations. During an SRAM read operation, the bit line BLL is for example coupled to the supply voltage VDD, and only the signal WL1 is for example activated. The data can thus be read using the detection circuit 902, the voltage on the supply rail VSS remaining low if the node VI of the memory cell is at a high voltage, and the voltage on the supply rail VSS amount if the node VI of the memory cell is at a low voltage.
    An advantage of the embodiment of Figure 9Ά is that the CAM and SRAM read operations can be performed at a relatively high speed without stability problems. Indeed, a fast read operation performed via the bit line BLL allowing the bit line BLL to discharge below VDD, using a memory cell of a standard SRAM size and with the signal WL1 or WL2 to VDD and the VSS rail to ground, may lead to stability issues as this may cause a write operation in the cell. By performing the read operation through the VSS supply rail, the transistors of the memory cell can be sized to allow fast operation without causing stability problems in the cell.
    Of course, although in the example of FIG. 9A the detection circuit 902 is coupled to the supply rail VSS, in alternative embodiments, it could be coupled to the supply rail VDD and to the supply voltage VDD, and the bit line could be coupled to the VSS supply voltage during CAM and SRAM read operations. In such a case, the writing in the memory cell is also for example carried out with the bit line BLL at or about the level of the supply voltage VDD.
    An advantage of the embodiments described herein is that a compact CAM cell can be obtained that can operate in both a CAM mode and an SRAM mode. Further, the CAM cell may advantageously be read during a CAM read operation using a single bit line independently coupled to the two storage nodes of the CAM cell, and using a single sense amplifier coupled to the bit.
    With the description thus made of at least one illustrative embodiment, various alterations, modifications, and improvements will be apparent to those skilled in the art.
    For example, it will be clear to those skilled in the art that although circuits have been described in which the transistors are MOS or TFET transistors, other transistor technologies could be used.
    In addition, it will be clear to those skilled in the art that the particular values of the supply voltages mentioned here are merely exemplary, and that other voltage levels could be used, depending for example technology of transistors.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    A content addressable memory (CAM) comprising at least one CAM cell (100, 300, 310, 600) comprising: first and second inverters (102, 104) cross-coupled between first and second storage nodes (VI , V2); a first transistor (114) coupling the first storage node (VI) to a bit line (BLL), the first transistor (114) being controlled by a first control signal (WL1); a second transistor (116) coupling the second storage node (V2) to the bit line (BLL), the second transistor (116) being controlled by a second control signal (WL2); and a control circuit (118) adapted to perform a CAM read operation by pre-charging the bit line (BLL) to a first voltage level, and then selectively activating the first or second transistor based on a bit of input data (Dj ^).
    [2" id="c-fr-0002]
    The CAM of claim 1, further comprising a detection circuit (120, 902) adapted to detect a success or failure of CAM depending on the voltage level on the bit line (BLL), or on a first rail supply voltage (VSS) of the first and second inverters, following activation of the first or second transistor (114, 116).
    [3" id="c-fr-0003]
    The CAM of claim 2, wherein the detection circuit (120, 902) is coupled to the bit line (BLL).
    [4" id="c-fr-0004]
    The CAM of claim 2, wherein the detection circuit (120, 902) is coupled to the first supply voltage rail (VSS) of the first and second inverters.
    [5" id="c-fr-0005]
    The CAM of any one of claims 2 to 4, comprising a plurality of said bit line (BLL) coupled CAM cells, the plurality of CAM word forming CAM cells, and wherein the input data bits of the plurality of CAM cells form a word, and the detection circuit (120) is adapted to detect a success or a word failure depending on the voltage level on the bit line, or on the first voltage rail of power supply (VSS) following activation of the first or second transistor (114, 116).
    [6" id="c-fr-0006]
    The CAM according to any one of claims 1 to 5, wherein the detection circuit (120) is adapted to detect success by detecting a voltage change below a first threshold, and detecting a failure by detecting a change. voltage higher than the first threshold.
    [0007]
    7. The MCAM according to any one of claims 1 to 6, wherein the control circuit (118) is further adapted to perform an SRAM read operation of a data value stored on the first and second nodes of storing (VI, V2) by pre-charging the bit line (BLL) to the first voltage level or another voltage level, and activating the first transistor (114).
    [8" id="c-fr-0008]
    8. CAM according to any one of claims 1 to 7, wherein the control circuit (120) is further adapted to perform a write operation on the first and second storage nodes (VI, V2) of said minus one CAM cell by coupling the bit line (BLL) to the first voltage level or another voltage level while selectively activating the first or second transistor based on a data bit to be written in the CAM cell .
    [9" id="c-fr-0009]
    9. CAM according to any one of claims 1 to 7, wherein the bit line (BLL) comprises first and second portions (BLL-A, BLL-B), the first transistor (114) being coupled to the first portion (BLL-A) and the second transistor (116) being coupled to the second portion (BLL-B), the first and second portions being coupled together by another transistor (302), the control circuit being adapted to perform a write operation in said at least one memory cell by deactivating the other transistor (302) and applying independent voltages to the first and second portions.
    [10" id="c-fr-0010]
    The CAM according to any one of claims 1 to 9, wherein the first and second inverters of said at least one CAM are coupled between a first voltage supply (VDD) rail at the first voltage level and a second voltage supply rail (VSS) at a second voltage level greater than ground and less than the first voltage level, and wherein during a write operation in said at least one CAM cell, one of the first and second transistors is activated by a voltage lower than the first supply voltage (VDD).
    [11" id="c-fr-0011]
    The CAM according to any one of claims 1 to 10, wherein said at least one CAM cell further comprises: a third transistor (312) coupled between the second storage node (V2) and another bit line (BLR) ), the third transistor being controlled by the second control signal (WL2); and a fourth transistor (314) coupled between the first storage node (VI) and the other bit line (BLR), the fourth transistor being controlled by the first control signal (WL1), wherein the first, second, third and fourth transistors (114, 116, 312, 314) are TFETs (tunnel effect field effect transistors).
    [12" id="c-fr-0012]
    The CAM of claim 11, wherein said at least one CAM cell further comprises a fifth transistor (602) coupled between the other bit line (BLR) and a read output line (RBL), a node of controlling the fifth transistor being coupled to the second storage node (V2).
    [13" id="c-fr-0013]
    The CAM according to any one of claims 1 to 12, comprising: at least one other CAM cell (100, 300, 310, 600) coupled to the bit line (BLL) by a first transistor (114) controlled by a first control signal (WL1) and by a second transistor (116) controlled by a second control signal (WL2), the control circuit (118) being adapted to mask said at least one other CAM cell during the read operation CAM by deactivating both the first and second transistors of the at least one other CAM cell during the CAM read operation.
    [14" id="c-fr-0014]
    A method for performing a CAM (Content Addressable Memory) operation in at least one CAM cell comprising: first and second inverters (102, 104) cross-coupled between first and second storage nodes (VI, V2) ; a first transistor (114) coupling the first storage node to a bit line (BLL), the first transistor being controlled by a first control signal (WL1); and a second transistor (116) coupling the second storage node (V2) to the bit line (BLL), the second transistor (116) being controlled by a second control signal (WL2), the method comprising: preloading, by a control circuit (118), the bit line (BLL) at a first voltage level; and selectively activating, by the control circuit (118), either the first or the second transistor (114, 116) based on an input data bit (Dj ^).
    [15" id="c-fr-0015]
    The method of claim 14, further comprising: detecting by a detection circuit (120) a success or failure depending on the bit line voltage level (BLL), or on a power rail ( VSS) of the first and second inverters, following activation of the first or second transistor.
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    同族专利:
    公开号 | 公开日
    EP3166110A1|2017-05-10|
    FR3043488B1|2018-04-27|
    US9679649B2|2017-06-13|
    EP3166110B1|2019-09-18|
    US20170133092A1|2017-05-11|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20030142524A1|2002-01-07|2003-07-31|Uniram Technology, Inc.|Methods for saving power and area for content addressable memory devices|US10839906B2|2018-10-01|2020-11-17|Commissariat A L'energie Atomique Et Aux Energies Alternatives|In memory computingmemory circuit having 6T cells|US6373738B1|2000-11-20|2002-04-16|International Business Machines Corporation|Low power CAM match line circuit|
    US20030090921A1|2001-11-15|2003-05-15|Afghahi Morteza Cyrus|Content addressable memory match line sensing techniques|
    US6839256B1|2002-03-15|2005-01-04|Integrated Device Technology, Inc.|Content addressable memory devices having dedicated mask cell sub-arrays therein and methods of operating same|US10714181B2|2016-11-30|2020-07-14|Taiwan Semiconductor Manufacturing Co., Ltd.|Memory cell|
    FR3067481B1|2017-06-09|2019-07-26|Commissariat A L'energie Atomique Et Aux Energies Alternatives|ASSOCIATIVE MEMORY ARCHITECTURE|
    US10878892B2|2018-04-23|2020-12-29|Arm Limited|Integrated circuit using discharging circuitries for bit lines|
    法律状态:
    2016-11-30| PLFP| Fee payment|Year of fee payment: 2 |
    2017-05-12| PLSC| Search report ready|Effective date: 20170512 |
    2017-11-30| PLFP| Fee payment|Year of fee payment: 3 |
    2019-11-29| PLFP| Fee payment|Year of fee payment: 5 |
    2021-08-06| ST| Notification of lapse|Effective date: 20210705 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1560605|2015-11-05|
    FR1560605A|FR3043488B1|2015-11-05|2015-11-05|RECONFIGURABLE CAM|FR1560605A| FR3043488B1|2015-11-05|2015-11-05|RECONFIGURABLE CAM|
    EP16196060.4A| EP3166110B1|2015-11-05|2016-10-27|Reconfigurable cam|
    US15/342,433| US9679649B2|2015-11-05|2016-11-03|Reconfigurable cam|
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