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    • 专利摘要:
    A diode (102) comprising: - a substrate (104); first and second doped semiconductor portions (120,126) forming a p-n junction, the first portion (126) being disposed between the substrate and the second portion (120); dielectric portions (130) covering lateral flanks of the second portion and of a first portion (124) of the first portion; a first electrode (142) resting on the substrate and disposed against the dielectric portions and lateral flanks (134) of a second portion (132) of the first portion disposed between the first portion of the first portion and the substrate; first electrode being electrically connected to the first portion only by contact with these side flanks; a second electrode (144) electrically connected to the second portion such that the second portion is disposed between the second electrode and the first portion.
    公开号:FR3042913A1
    申请号:FR1560077
    申请日:2015-10-22
    公开日:2017-04-28
    发明作者:Hubert Bono；Jonathan Garcia；Ivan-Christophe Robin
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    MICROELECTRONIC DIODE WITH OPTIMIZED ACTIVE SURFACE
    DESCRIPTION
    TECHNICAL FIELD AND PRIOR ART The invention relates to the field of light-emitting diodes such as light-emitting diodes (called LEDs or LEDs, or even micro-LEDs) as well as that of photoreceptive diodes such as photodiodes. The invention applies in particular to the field of LED lighting devices, light emitting electronic devices comprising LED arrays such as screens, projectors or image walls, as well as in the field of electronic devices or microelectronic photoreceptors having photodiode arrays, such as image sensors.
    The production of diodes, for example when producing a matrix of photodiodes or LEDs forming a matrix of pixels, is generally based on standard microelectronic processes commonly used in so-called planar technology and in which each element of the diodes is realized. by a first deposition step, then a lithography step followed by an etching step. With this type of process, the realization of each pattern of a diode material requires the implementation of at least three distinct steps. In addition, each pattern made must be aligned with those already present. Finally, the definition of each pattern must take into account the performance of the equipment concerned both in terms of achievable dimensions and alignment performance compared to the previous pattern.
    In addition, to obtain sufficient performance with the standard technologies of microelectronics, it is necessary to carry out a planarization of the elements made to control the lithography steps implemented on these elements because the resolution achievable with such a step of lithography is directly related to the topography on which the lithography is implemented, the very large aperture optical lenses used in lithographic insolation devices having depths of field that decrease with increasing resolution.
    In a matrix of standard diodes, deposition, lithography and etching steps are successively implemented to make the electrical contacts (anodes and cathodes) of the diodes and the layers of electrical insulation between these electrical contacts. However, it is essential to control the electrical insulation between the cathode and the anode of each of the diodes. The realization of the electrical insulation between the electrodes of the diodes via the production of insulating layers deposited in accordance with the patterns of the structure generates a significant loss of active surface available (corresponding to the area occupied by the diode elements performing the photoelectric conversion or light emission, i.e. the pn junction of the diode) relative to the total available area on which the diode array is made, given the area occupied by these electrical insulation layers.
    In the document FR 2 992 465 A, an LED device is produced from a stack of pre-structured semiconductor layers in the form of independent islands, each island serving to produce an LED of the device. The area occupied by each of the LEDs is therefore predefined and the deposition, lithography and etching steps used do not make it possible to minimize the loss of active surface area generated by the use of islands whose dimensions, in the plane of the substrate, do not correspond to those pn junctions to achieve. The embodiment of the anode of each LED comprises the etching of an opening of a dielectric layer previously deposited on the p-type semiconductor. To ensure a good geometric definition of this electrode, it is necessary to achieve this opening by a plasma assisted dry etching. However, the InGaN used for the realization of this device is a large-gap semiconductor which is impaired by this type of etching, which leads to a bad electrical interface and therefore to an irreversible degradation of the electrical properties of the LEDs. Furthermore, in this type of LED, the electrical contact between the cathode and the n-type semiconductor is obtained mainly by the horizontal contact surface obtained by etching the semiconductor island, which represents an additional loss of active surface. In addition, many lithography steps must be implemented to complete the device. Finally, the n-type semiconductor portions forming the horizontal electrical contact surfaces on which the cathodes are arranged generate light losses on the sides of the LEDs because part of the light is guided horizontally by these semiconductor portions and gets lost in the environment around the LED. The LEDs of this device are poorly optically isolated from each other, which affects the resolution of the image obtained with this device.
    STATEMENT OF THE INVENTION
    An object of the present invention is to propose a diode whose structure makes it possible to minimize the active surface losses as well as the lateral optical losses, while reducing the number of steps to be implemented for its realization in order to reduce its cost of production.
    For this, the invention proposes a diode comprising at least: a substrate; first and second doped semiconductor portions forming a p-n junction, the first semiconductor portion being disposed between the substrate and the second semiconductor portion; dielectric portions covering lateral flanks of the second semiconductor portion and a first portion of the first semiconductor portion; a first electrode resting on the substrate and disposed against the dielectric portions and lateral flanks of a second portion of the first semiconductor portion which is disposed between the first portion of the first semiconductor portion and the substrate, the first electrode being electrically connected to the first semiconductor portion only by contact with the side flanks of the second portion of the first semiconductor portion; a second electrode electrically connected to the second semiconductor portion such that the second semiconductor portion is disposed between the second electrode and the first semiconductor portion.
    In this diode, the first electrode is electrically connected to the first semiconductor portion only at the lateral flanks of the second portion of this portion. Thus, unlike diodes of the prior art in which a horizontal contact surface, that is to say a contact surface substantially parallel to the main plane of the substrate, is achieved by etching the semiconductor, the fact of using the side flanks to achieve this electrical contact optimizes the area occupied by the diode and maximize its active surface. In addition, this absence of a horizontal contact surface with the first semiconductor portion makes it possible to avoid the optical losses generated by a structure comprising such contact surfaces (because the differences in dimensions, in the plane parallel to the substrate , between the different parts of the first semiconductor portion are minimal), which improves the optical isolation of the diode as well as its efficiency of emission or conversion of light.
    This diode uses dielectric portions, or portions of electrical insulation, covering the lateral flanks of a portion of the elements forming the pn junction of the diode and for electrically isolating and passivating these lateral flanks, in particular vis-à-vis the first electrode, and also electrically isolating the doped semiconductor portions of the pn junction vis-à-vis the other when they are not in direct contact against each other; the other (especially when one or more emissive layers are present between the first and second semiconductor portions, or an intrinsic semiconductor portion is disposed between them). These dielectric portions also make it possible to ensure electrical insulation between the first and the second electrodes while occupying a minimum of space in the diode. This localization of the dielectric portions on the lateral flanks of the pn junction of the diode as well as the realization of the electrical contact between the first semiconductor portion and the first electrode only by the lateral flanks of a portion of the first sem fraction. -conductor makes it possible to improve the ratio between the active surface of the diode (surface occupied by the pn junction) occupied on the substrate and the total surface of the substrate on which the diode is made, and therefore to increase the integration of the diode on the substrate given the small size of the dielectric portions and the first electrode which each have a vertical structure (parallel to the lateral flanks of the pn junction of the diode which are covered by these dielectric portions and by the first electrode). This strong integration allows for example the realization of electronic display device whose pixels have a lateral dimension of the order of 7 pm and are spaced apart by a distance of about 3 pm.
    In addition, this strong integration of the dielectric portions also has the advantage of minimizing the current densities obtained in the electrodes of the diode, and therefore of reducing Joule heating generated in the diode via an overall decrease in the thermal resistance of the diode. .
    The structure of this diode reduces its manufacturing cost as well as its energy consumption. In the field of lighting, such a diode can improve the electrical injection within it and thus increase its energy efficiency. In the field of imaging devices, such a diode makes it possible to produce high resolution devices by reducing the size of the pixels, which becomes limited only by the formatting means used.
    The p-n junction formed by the first and second semiconductor portions and the dielectric portions covering the lateral flanks of the second semiconductor portion and the first portion of the first semiconductor portion may form a mesa structure. The expression "mesa structure" designates the fact that the diode is made in the form of a stack of the first and second doped semiconductor portions, a junction zone being present between these two semiconductor portions. doped, and that this stack is here engraved on all its height in the form of an island called mesa. In addition, this island comprises, at the side flanks of the second portion of the first doped semiconductor portion, an electrical contact area of the first doped semiconductor portion to which the first electrode is connected.
    In addition, because the electrical contact between the first electrode and the first semiconductor portion is formed on the lateral flanks of the second portion of the first semiconductor portion, the contact resistance, which is inversely proportional to the the contact surface is totally independent of the width of the spaces separating the diodes and in which the first electrodes are arranged.
    The first semiconductor portion may be n-doped and the second semiconductor portion may be p-doped, the first electrode may form a cathode of the diode and the second electrode may form an anode of the diode.
    The diode may further include a dielectric mask such that a first portion of the second electrode is disposed between the dielectric mask and the second semiconductor portion, wherein at least a second portion of the second electrode may be disposed in least one opening through the dielectric mask, and that the dielectric portions can cover side flanks of the dielectric mask.
    In this case, upper faces of the dielectric mask, dielectric portions, and first and second electrodes may together form a substantially planar continuous surface of the diode. This substantially planar continuous surface makes it easy to hybridize, for example without using inserts such as connection microbeads, the diode to another element such as a substrate making it possible to produce different connection configurations of the diode and which may comprise also a planar face at which there are materials similar to those of the diode, for example by direct bonding metal against metal (for the electrodes) and dielectric against dielectric (for the dielectric portions and the dielectric mask). This substantially planar continuous surface is also well suited for producing an interconnection structure directly on the electrodes, thereby avoiding a number of difficulties related to the residual topology of the diode structures of the prior art.
    The upper faces of the dielectric mask, first and second electrodes and dielectric portions form a substantially flat continuous surface, that is to say are arranged substantially in the same plane. The term "substantially planar" is used here to designate the fact that the surface formed by the upper faces of the dielectric mask, electrodes and dielectric portions may have variations in height, or thickness, between about 0 and 150 nm. These slight variations in height or thickness may be due to the implementation of a chemical mechanical planarization (CMP) implemented in the presence of the materials of the electrodes, the dielectric mask and the dielectric portions, the etching rates of these different materials being different from each other. These slight variations in height or thickness, between the upper faces of the dielectric portions, of the dielectric mask and those of the electrodes, may have the advantage of guaranteeing excellent insulation between the diode electrodes and / or with respect to adjacent diode electrodes when depressions are formed at the upper faces of the electrodes.
    External lateral flanks of the dielectric portions may be aligned with the lateral flanks of the second portion of the first semiconductor portion. This configuration facilitates the realization of the first electrode and further optimizes the bulk of the structure formed by the semiconductor portions and the dielectric portions.
    The first semiconductor portion may comprise a stack of at least two doped semiconductors in different conductivity levels. For example, when the first semiconductor portion is n-doped, it may comprise a stack of a first n + doped semiconductor disposed on the substrate and a second doped semiconductor disposed on the first semiconductor. driver. The thickness of the first semiconductor portion is advantageously between about 2 μm and 4 μm. Such a thickness can be obtained because the first semiconductor portion is disposed directly on the substrate, without the presence of a dielectric layer between the first semiconductor portion and the substrate. This thickness makes it possible to have a very good electrical contact between the first semiconductor portion and the first electrode only by the lateral flanks of the first semiconductor portion, without having to make a horizontal contact surface (parallel to the plane principal of the substrate) to form the electrical connection between the first electrode and the first semiconductor portion. Such a thickness of the first semiconductor portion also allows the implementation of a laser lift-off of the substrate, although no dielectric layer is interposed between the substrate and the first portion of the substrate. semiconductor, such a withdrawal can be implemented after hybridization of the diode electrodes on an interconnection substrate.
    The diode can be a photodiode or an LED.
    In this case, the photodiode may comprise at least one intrinsic semiconductor portion disposed between the first and second semiconductor portions and such that side flanks of the intrinsic semiconductor portion are covered by the dielectric portions, or the LED may comprise at least one emissive active zone to at least one quantum well disposed between the first and second semiconductor portions and such that lateral flanks of the emissive active zone are covered by the dielectric portions. The invention also relates to an electronic device comprising a plurality of diodes as described above, in which each of the first electrodes is further electrically connected to the first semiconductor portion of at least one neighboring diode solely by contact with the sidewalls. lateral portions of the second portion of the first semiconductor portion of said at least one neighboring diode. The integration of the diodes is thus maximized within the electronic device because the first electrodes can fill gaps between two neighboring diodes.
    The first electrodes of the diodes of the device can form a cathode common to these diodes.
    The diodes may be part of a matrix of diodes of similar structures forming a matrix of pixels of the electronic device. The invention also relates to a method for producing a diode, comprising at least the steps of: - producing, on a substrate, a stack of layers comprising at least first and second semiconductor layers doped according to types of opposite conductivity, such that the first semiconductor layer is disposed between the second semiconductor layer and the substrate, and comprising at least one electrically conductive layer disposed on the second semiconductor layer; first etching of the stack of layers through the electrically conductive layer, the second semiconductor layer and a portion of the thickness of the first semiconductor layer, forming a first portion of the second electrode, a second semiconductor portion and a first portion of a first semiconductor portion; - Making dielectric portions covering lateral flanks of the first portion of the second electrode, the second semiconductor portion and the first portion of the first semiconductor portion; second etching of the stack of layers through a remaining thickness of the first semiconductor layer until reaching the substrate, forming a second portion of the first semiconductor portion disposed between the first portion of the first portion; semiconductor and the substrate, the first and second semiconductor portions forming a pn junction; - Realizing a first electrode resting on the substrate and disposed against the dielectric portions and lateral flanks of the second portion of the first semiconductor portion, the first electrode being electrically connected to the first semiconductor portion only by contact with the lateral flanks of the second portion of the first semiconductor portion, and forming a second portion of the second electrode on the first portion of the second electrode.
    The dielectric portions being deposited on the lateral flanks of the etched structure in the stack of layers, these dielectric portions can be made by a self-aligned method for isolating the electrodes of the diode without using a mask specially adapted to the realization of these dielectric portions, for example via a conformal deposition of the material of the dielectric portions and etching of the portions of this material which do not cover the lateral flanks of the structures.
    The first etch of the stack of layers can be implemented through a dielectric mask disposed on the stack of layers, and the dielectric portions can cover side flanks of the dielectric mask.
    The second etching of the stack can be performed such that external lateral flanks of the dielectric portions are aligned with the lateral flanks of the second portion of the first semiconductor portion.
    The production of the first electrode and the second part of the second electrode may comprise the implementation of the following steps: - making an opening through the dielectric mask and opening on the first part of the second electrode; depositing at least one electrically conductive material in the opening and in a space formed through the stack of layers by the implementation of the first and second etchings; - Planarization of the electrically conductive material with stop on the dielectric mask.
    In this case, the realization of the electrodes corresponds to the implementation of a "damascene" type process in which one or more electrically conductive materials are formed by at least one full-plate deposit, that is to say a deposit of electrically conductive material on the entire structure made, the electrodes being obtained thereafter via a planarization of this electrically conductive material. The realization of the first electrode therefore does not require a specific alignment step or special masking. The location of the first electrode may correspond to a space formed between the dielectric portions covering the lateral flanks of two neighboring diodes. The invention also relates to a method for producing an electronic device, comprising the implementation of a method as described above, in which the steps implemented form several diodes such that each of the first electrodes is connected. electrically to the first semiconductor portion of at least one adjacent diode solely by contact with the side flanks of the second portion of the first semiconductor portion of said at least one neighboring diode.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings, in which: FIGS. 1A to 1H show the steps of a method of realizing an electronic device, object of the present invention, comprising a plurality of diodes, also objects of the present invention, according to a particular embodiment.
    Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    FIGS. 1A to 1H show the steps of a method of producing an electronic device 100 according to a particular embodiment. In the particular embodiment described here, the device 100 comprises a plurality of diodes 102 corresponding to light-emitting diodes and forming a matrix of diodes serving as a matrix of pixels of the device 100. As a variant, the diodes 102 may be produced next to the others without forming a matrix of diodes, without regular spacings between them.
    As shown in FIG. 1A, the device 100 comprises a substrate 104 comprising, for example, sapphire, silicon, a semiconductor similar to that used to form the active portion of the diodes 102, or any other material enabling the substrate 104 to form a growth substrate allowing the deposition of the semiconductor stack to form the active part of the diodes 102. The substrate 104 serves as a support for the deposition or the growth of layers intended for the production of the diodes 102 of the device 100.
    A first semiconductor layer 106 doped according to a first type of conductivity, for example n-type, is deposited on the substrate 104. In the particular embodiment described here, this layer 106 corresponds to a stack of several layers of semi-conductor. -conductor separate, for example a n + doped semiconductor layer 108 with a concentration of donors for example between about 5.1017 and 5.1020 donors / cm3 on which is disposed another layer 110 of n-doped semiconductor with a concentration of donors for example between about 1017 and 5.1019 donors / cm3. For example, the layer 108 may be a GaN layer and the layer 110 may be an InGaN layer. The thickness of the layer 108 is for example greater than about 100 nm, for example equal to about 3 μm, and that of the layer 110 is for example between about 5 nm and 500 nm. The total thickness of the first layer 106, that is to say the sum of the thicknesses of the layers 108 and 110, is for example between about 20 nm and 10 μιτι, and preferably between about 2 μιτι and 4 μη . The layer 108 here forms a buffer layer disposed between the layer 110 and the substrate 104 and used in particular to filter the growth defects so that these defects do not find the layer 110 used to form the p-n junctions of the diodes 102.
    As a variant, the layers 108 and 110 may be doped with the same level of n-type doping (in contrast to the case described above where the layer 108 is n + doped and the layer 110 is n-doped). According to another variant, the layer 106 may correspond to a single layer of n-doped semiconductor, and with a concentration of donors for example of between 1017 and 5.1020 donors / cm3, for example comprising GaN and whose thickness is for example between about 20 nm and 10 μιτι, and advantageously between about 2 μιτι and 4 μιτι.
    A stack 112 comprising one or more emitting layers, for example five, intended to each form in the diodes 102 a quantum well, for example based on InGaN, and each disposed between two barrier layers, for example based on GaN, is disposed on the first layer 106 (on the layer 110 in Figure IA). The stack 112 is formed of layers comprising intrinsic semiconductor materials, that is to say unintentionally doped (concentration residual donors nnid for example equal to about 1017 donors / cm'3, or between about 1015 and 1018 donors / cm3). The thickness of the or each of the emissive layers is for example equal to approximately 3 nm and more generally between approximately 0.5 nm and 10 nm, and the thickness of each of the barrier layers is for example between approximately 1 nm. and 25 nm. The layers of the stack 112 are intended to form the active emitting layers of the diodes 102.
    A second semiconductor layer 114 doped according to a second type of conductivity, opposite to that of the doping of the first layer 106 and therefore here p-type, with a concentration of acceptors for example between about 1017 and 5.1019 acceptors / cm3 is placed on the stack 112. The layers 106 and 114 (and more particularly the layers 110 and 114 in the example described here) are intended to form the pn junctions of the diodes 102. The semiconductor of the layer 114 is for example GaN and its thickness is for example between about 20 nm and 10 μιτι.
    In an alternative embodiment, an electron-blocking layer (not visible in FIGS. 1A to 1H) may be disposed between the second layer 114 and the stack of layers 112, this electron-blocking layer being for example AIGaN with 12% aluminum and p-doped with a concentration of acceptors, for example equal to approximately 1 × 10 17 acceptors / cm 3.
    Materials other than those mentioned above may be used to make the diodes 102.
    An electrically conductive layer 115 intended to form a portion of the electrode which will be in contact with the semiconductor of the layer 114, is disposed on the layer 114. The electrically conductive material used is for example optically reflective, and corresponds, for example to aluminum.
    A layer 116 for forming a dielectric hard mask is formed on the layer 115. The material of this layer 116 is, for example, SiO 2.
    As shown in FIG. 1B, patterns are formed by etching in the layer 116, forming the dielectric mask 118. The openings formed in the dielectric mask 118 correspond to the patterns to be etched in the layers on which the dielectric mask 118 is disposed in order to defining the mesa structures of the diodes 102. An etching of the electrically conductive layer 115 is carried out according to the pattern of the dielectric mask 118, retaining remaining portions 119 of the layer 115 intended to form portions of the anodes of the diodes 102. An etching of the layer 114 is then implemented according to the patterns defined by the dielectric mask 118, producing second doped semiconductor portions 120 intended to be part of the pn junctions of the diodes 102. The layers 114, 115 and 116 are, for example engraved by the implementation of a reactive ion etching by a plasma torch system, or ICP-RIE for "Inductively Coupled Plasma - Reactive Ion Etching ".
    As shown in FIG. 1C, the etching is then extended in the stack 112 and a first portion of the first layer 106 (or a first one of the stack of layers forming the first layer 106) still according to the patterns defined by the mask dielectric 118. This etching is stopped at a depth level located in the first layer 106 such that a second portion of the first layer 106 is kept at the bottom of each of the etched areas of the stack. In the example described here, the etching is stopped at a level in the layer 110 such that the layer 108 and part of the thickness of the layer 110 are not etched. The thickness, referenced "b" in FIG. 1C, of the layer 110 which is etched, that is to say the thickness of the first part of the first layer 106, is for example between about 100 nm and 5 pm.
    As a variant, this etching can be stopped at the upper face of the layer 108 such that this layer 108 is not etched but the entire thickness of the layer 110 is etched. According to another variant, this etching can be stopped at a level in the layer 108 such that only a portion of the thickness of the layer 108 is not etched.
    The choice of the depth of etching performed, and therefore the thickness of each of the first and second parts of the first layer 106, depends in particular on the initial thickness of the first layer 106 (and therefore the initial thicknesses of the layers 108 and 110 in the embodiment described here) and this so that the remaining thickness of the first layer 106, that is to say the thickness of the second portion of the first layer 106 is sufficient to achieve a good electrical contact between this second portion of the first layer 106 and the cathodes of the diodes 102 as described below.
    The remaining portions of the stack 112 form active areas 122 of the diodes 102 and the remaining portions of the first portion of the first layer 106 form first portions 124 of first doped semiconductor portions 126 for forming, with the second portions 120, the pn junctions of the diodes 102 (in Figure IC, the first portions 124 are symbolically delimited from the remainder of the first layer 106 by dashed lines).
    The etchings made in the layers 106 (108 + 110), 112, 114 and 115 correspond to the locations of the cathodes of the diodes 102 of the device 100. This etching of these layers forms, between the mesa structures of the diodes 102, spaces 128 which will be used by the following the realization of the cathodes of the diodes 102. In the particular embodiment described here, the cathodes of the diodes 102 will form a cathode common to several diodes 102, or all the diodes 102, of the device 100.
    A dimension, referenced "a" in FIG. 1C, spaces 128 corresponding to the distance between two mesa structures of adjacent diodes 102 is for example greater than or equal to approximately 50 nm, the minimum distance between two neighboring diodes 102 being defined by the minimal resolution of the lithography used. This dimension "a" corresponds to the sum of the width of a portion of electrically conductive material to be made between the two mesa structures of the diodes 102 to form a cathode common to these diodes 102 and thicknesses of two vertical dielectric portions which will be also arranged between the two mesa structures diodes 102. Thus, the dimension "a" is a function of the width of the cathode made between the diodes 102 which is chosen in particular according to the acceptable losses related to the supply of electric current in the areas furthest away from peripheral contact points. The etching used is a dry etching, for example via an IC2-based plasma or an RIE etching, for example ICP-RIE.
    The dimensions of the ribs of one of the mesa structures can be between about 500 nm and 1 mm, or between 500 nm and several millimeters, depending on the intended applications. For applications using high power diodes (eg LED bulbs to form car headlights), the dimensions of the diodes 102 will be larger than for applications using diodes 102 of lower power.
    A dielectric layer, corresponding for example to a SiN / SiO 2 bilayer, and forming a passivation layer, is then deposited with a conformal thickness, for example between about 5 nm and 1 μm and advantageously equal to about 200 nm, on the mask dielectric 118 and along the walls of the spaces 128, thus covering the side walls of the dielectric mask 118, the second semiconductor portions 120, the active areas 122 and the first portions 124 of the first semiconductor portions 126. The layer dielectric is also deposited on the non-etched portions of the first layer 106 forming the bottom walls of the spaces 128. This dielectric layer is for example formed by a PECVD type deposit (plasma-assisted chemical vapor deposition) or ALD (deposit atomic layer) depending on the nature of the deposited material (s).
    Anisotropic etching, for example a dry etching such as an RIE etching, is then implemented such that the portions of the dielectric layer in the spaces 128 and not covering the side walls of the mesa structures of the diodes 102 are removed. , thus revealing the portions of the first layer 106 at the bottom of the spaces 128. The portions of this dielectric layer covering the upper faces of the dielectric mask 118 are also removed. Thus, only portions 130 of the dielectric layer covering the side walls of the dielectric mask 118, second semiconductor portions 120, active areas 122 and first portions 124 of the first semiconductor portions 126 are stored in the gaps. 128.
    As shown in FIG. 1D, a second etching of the layer 106 is then carried out until the bottom walls of the spaces 128 are formed by the substrate 104, i.e., all the way through. the thickness of the second portion of the first layer 106, thereby forming second portions 132 of the first semiconductor portions 126 which comprise the remaining portions of the second portion of the first layer 106. This etching makes it possible to reveal lateral flanks 134 of these second portions 134 of the first portions 126 which will form electrical contact zones for the cathodes of the diodes 102.
    The portions of the dielectric mask 118, the semiconductor portions 120 and 126, the active areas 122 and the dielectric portions 130 form mesa structures, that is, island-shaped stacks, arranged on the substrate. 104. Each mesa structure of each diode 102 has a section, in a plane parallel to the face of the substrate 104 on which these structures reside, for example in the form of a disk. Each of the mesa structures can thus form an island of cylindrical shape. Mesa structures of different shape are possible, for example in the form of pavement.
    Apertures 136 are then made through the dielectric mask 118, forming locations for making second portions of the diode anodes 102 (Fig. 1E). These openings 136 pass through the entire thickness of the dielectric mask 118 so that the bottom walls of the openings 136 are formed by the portions 119. This etching is for example of the ICP-RIE type.
    A first electrically conductive material 138 is then deposited in the spaces 128, between the mesa structures of the diodes 102, as well as on the upper faces of the dielectric mask 118 and in the openings 136 (FIG. 1F). This first electrically conductive material 138 is deposited in a conformal manner, that is to say by forming a layer of substantially constant thickness on the dielectric mask 118 and along the walls of the spaces 128 and the openings 136. In the example embodiment described here, the first electrically conductive material 138 is formed by the deposition of a first titanium layer of thickness for example between about 5 nm and 300 nm, followed by a deposit of a second layer of aluminum thickness for example between about 50 nm and 1 pm.
    The first electrically conductive material 138 is in electrical contact with the lateral flanks 134 of the second portions 134 of the first portions 126, and with the portions 119 at the bottom walls of the openings 136. These electrical contacts are intended to form the electrical connections between the pn junctions and the anodes and cathodes of the diodes 102.
    As shown in FIG. 1G, a second electrically conductive material 140 is deposited by filling the remaining volume of spaces 128 and openings 136. In FIG. 1G, the thickness of this second electrically conductive material 140 is such that it also covers the portions of the first electrically conductive material 138 disposed on the dielectric mask 118. The second electrically conductive material 140 is for example copper which may be formed by the implementation of an electrochemical deposition (ECD or "Electro-Chemical Deposition") full plate, that is to say on the entire structure previously performed.
    Finally, the diodes 102 of the device 100 are completed by implementing a chemical mechanical planarization (CMP) in order to eliminate the portions of the first and second electrically conductive materials 138 and 140 that protrude from spaces 128 and openings 134 and which are arranged on the dielectric mask 118. This planarization electrically isolates the portions of conductive material disposed in the spaces 128 vis-à-vis those arranged in the openings 136 (Figure 1H). The portions of the electrically conductive materials 138 and 140 disposed in the gaps 128 form cathodes 142 extending over the entire height of the mesa structures of the diodes 102 and are electrically connected to the first semiconductor portions 126 only at the side flanks 134. The portions of the electrically conductive materials 138 and 140 disposed in the openings 136 form second portions of the anodes 144 electrically connected to the portions 119 corresponding to the first portions of the anodes 144, the anodes 144 being connected to the second semi-conductor portions 120 at the upper faces of these portions 120. An upper face 146 of the device 100 made which is substantially planar, formed by the upper faces of the cathodes 142, anodes 142, dielectric portions 130 and the dielectric mask 118 is obtained.
    Thanks to the vertical dielectric portions 130, the cathodes 142 are electrically well insulated from the second semiconductor portions 120, anodes 144 and active zones 122. The thickness of the dielectric portions 130, which corresponds to the thickness of the dielectric layer the embodiment of the portions 130, can be chosen such that an acceptable leakage current is tolerated on each of the diodes 102, for example less than about 1% of the nominal current flowing through the diode 102, when they are subject to a difference of potential (applied between the cathode and the anode) for example of the order of 4 volts. The minimum thickness of the dielectric portions 130 is for example between about 3 nm and 5 nm, or between 3 nm and 4 nm, depending on the material or materials used to make the dielectric portions 130.
    In order to ensure electrical isolation between the cathodes 142 and the anodes 144 of the diodes 102, and to avoid the presence of parts of the electrically conductive materials 138 and 140 electrically connecting one or more of the cathodes 142 with one or more of the anodes 144, the step planarization is advantageously carried out until an over-etching of the portions of the electrically conductive materials 138 and 140 arranged in the spaces 128 and in the openings 136 with respect to the dielectric materials of the portions 130 and the mask 118, forming in the cathodes 142 and the anodes 144 of the hollows at the upper faces of these electrodes. These recesses may have a depth, relative to the plane of the upper face 146, of between about 5 nm and 150 nm. This over-etching can be obtained by adjusting the etching anisotropy and by the etching selectivity that exists between the dielectric materials of the portions 130 and the mask 118 and the electrically conductive materials 138 and 140. The CMP implemented a different abrasion rate depending on the materials, and in the method described here, the abrasion of the electrically conductive materials 138 and 140 is faster than that of the dielectric materials of the portions 130 and the mask 118. This translates, at the level of of the upper face 146 of the device 100, by a withdrawal of the materials 138 and 140 with respect to the dielectric portions 130 and the dielectric mask 118. Thus, the electrodes of the diodes 102 remain perfectly isolated from each other thanks to an intrinsic property of the planarization implemented. Such over-etching can also be implemented by a RIE etching process.
    In the particular embodiment described above, the first semiconductor portions 126 are n-type and the second semiconductor portions 120 are p-type. In a variant, the first semiconductor portions 126 may be of the p type and the second semiconductor portions 120 may be of the n type, with in this case the portions of electrically conductive material disposed in the spaces 128 forming the anodes of the electrodes. diodes 102 and the portions of electrically conductive material disposed in the openings 136 forming, with the portions 119, the cathodes of the diodes 102.
    The substantially planar surface obtained at the upper face 146 of the device 100 makes it easy to hybridize the matrix of diodes 102 made to any type of element such as an electronic circuit, and makes it possible, in particular, to perform such hybridization by direct bonding. ("Direct bonding", also called molecular bonding) of the diode array 102 to the electronic circuit without using inserts, such as microbeads, between the diode array 102 and the electronic circuit. The direct metal-metal and dielectric-dielectric type of collages made in this case have the advantage of being sealed. The fact that depressions are present at the upper faces of the cathodes 142 and anodes 144 does not pose a problem for the implementation of such a direct bonding because during this direct bonding, the materials of these portions expand and it is therefore possible to obtain a very good contact between these electrodes and conductive elements of the electronic circuit. Details of implementation of such a direct bonding are for example described in the document "Mechanisms of copper direct bonding observed by in situ and quantitative transmission electron microscopy" by M. Martinez et al., Thin Solid Films 530 (2013 ) 96-99.
    In the particular embodiment described here, the device 100 comprises a matrix of diodes 102 which are light-emitting diodes, the microelectronic device being able to be part of an LED display device (screens, projector, wall of images, etc. .). This matrix of diodes 102 comprises the cathodes 142 which form a common cathode to all the diodes 102, and each diode 102 comprises an anode 144 making it possible to individually address each of the diodes 102.
    In a variant, the microelectronic device 100 may comprise a matrix of diodes 102 which are photo-receptor diodes, or photodiodes. In this case, the stack of layers 112 disposed between the semiconductor layers 106 and 114 respectively doped n and p may correspond to one or more intrinsic semiconductor layers. In addition, in this variant, the anodes 144 and the cathodes 142 of the diodes 102 are not used to supply current to the diodes 102 but serve to recover the currents photo-generated by the diodes 102.
    According to another variant, that the diodes 102 correspond to light-emitting diodes or to photodiodes, the mesa structures of the diodes 102 may not comprise layers between the doped semiconductor portions 120 and 126 (corresponding to the emissive active zones or to the intrinsic semiconductor portions), and the doped semiconductors p and n are then arranged directly against each other.
    Alternatively, the device 100 may comprise, on the upper face 134, a connection structure forming the electrical connections of the diodes 102 and having first electrically conductive elements electrically connected to the cathodes 142 of the diodes 102 and the second electrically conductive elements electrically connected to the anodes 144 of the diodes 102. These electrically conductive elements of such a connection structure are electrically isolated from each other by dielectric elements whose dimensions, in the plane of the face 134, are at least equal to those of the dielectric portions 130 and the hard mask 118 so that the electrically conductive elements do not form short circuits between the electrodes of the diodes 102.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    A diode (102) comprising at least: - a substrate (104); a first and second doped semiconductor portions (120, 126) forming a pn junction, the first semiconductor portion (126) being disposed between the substrate (104) and the second semiconductor portion (120); ); dielectric portions (130) covering lateral flanks of the second semiconductor portion (120) and a first portion (124) of the first semiconductor portion (126); a first electrode (142) resting on the substrate (104) and disposed against the dielectric portions (130) and side flanks (134) of a second portion (132) of the first semiconductor portion (126) which is disposed between the first portion (124) of the first semiconductor portion (126) and the substrate (104), the first electrode (142) being electrically connected to the first semiconductor portion (126) only by a contacting the lateral flanks (134) of the second portion (132) of the first semiconductor portion (126); a second electrode (144) electrically connected to the second semiconductor portion (120) such that the second semiconductor portion (120) is disposed between the second electrode (144) and the first semiconductor portion ( 126).
    [2" id="c-fr-0002]
    The diode (102) of claim 1, further comprising a dielectric mask (118) such that a first portion (119) of the second electrode (144) is disposed between the dielectric mask (118) and the second portion of semiconductor (120), at least a second portion of the second electrode (144) is disposed in at least one aperture (136) passing through the dielectric mask (118), and that the dielectric portions (130) overlap flanks side of the dielectric mask (118).
    [3" id="c-fr-0003]
    The diode (102) according to claim 2, wherein upper faces of the dielectric mask (118), dielectric portions (130), and first and second electrodes (142, 144) together form a substantially planar continuous surface of the diode. (102).
    [4" id="c-fr-0004]
    4. Diode (102) according to one of the preceding claims, wherein outer side flanks of the dielectric portions (130) are aligned with the side flanks (134) of the second portion (132) of the first semiconductor portion. (126).
    [5" id="c-fr-0005]
    5. Diode (102) according to one of the preceding claims, wherein the first semiconductor portion (126) comprises a stack of at least two semiconductors (108, 110) doped at different conductivity levels.
    [6" id="c-fr-0006]
    6. Diode (102) according to one of the preceding claims, wherein the thickness of the first semiconductor portion (126) is between about 2 pm and 4 pm.
    [7" id="c-fr-0007]
    7. Diode (102) according to one of the preceding claims, wherein the diode (102) is a photodiode or an LED.
    [8" id="c-fr-0008]
    8. Diode (102) according to claim 7, wherein the photodiode comprises at least one intrinsic semiconductor portion disposed between the first and second semiconductor portions (120, 126) and such that side flanks of the semi-conductor portion. -conductor are covered by the dielectric portions (130), or wherein the LED has at least one emissive active area (122) at least one quantum well disposed between the first and second semiconductor portions (120,126) and such side flanks of the emissive active zone (122) are covered by the dielectric portions (130).
    [9" id="c-fr-0009]
    9. An electronic device (100) comprising a plurality of diodes (102) according to one of the preceding claims, wherein each of the first electrodes (142) is further electrically connected to the first semiconductor portion (126) of at least a diode (102) adjacent only by contact with the side flanks (134) of the second portion (132) of the first semiconductor portion (126) of said at least one neighboring diode (102).
    [10" id="c-fr-0010]
    The electronic device (100) of claim 9, wherein the diodes (102) are part of a matrix of diodes (102) of similar structures forming a pixel array of the electronic device (100).
    [11" id="c-fr-0011]
    11. A method for producing a diode (102), comprising at least the steps of: - producing, on a substrate (104), a stack of layers comprising at least first and second semiconductor layers (106, 114 ) doped according to opposite conductivity types, such that the first semiconductor layer (106) is disposed between the second semiconductor layer (114) and the substrate (104), and comprising at least one electrically conductive layer ( 115) disposed on the second semiconductor layer (114); first etching of the stack of layers through the electrically conductive layer (115), the second semiconductor layer (114) and a portion of the thickness of the first semiconductor layer (106), forming a first part (119) a second electrode (144) of the diode (102), a second semiconductor portion (120), and a first portion (124) of a first semiconductor portion (126); - Making dielectric portions (130) covering lateral flanks of the first portion (119) of the second electrode (144), the second semiconductor portion (120) and the first portion (124) of the first portion semiconductor (126); second etching of the stack of layers through a remaining thickness of the first semiconductor layer (106) to reach the substrate (104), forming a second portion (132) of the first semiconductor portion (126) disposed between the first portion (124) of the first semiconductor portion (126) and the substrate (104), the first and second semiconductor portions (120, 126) forming a pn junction; - Realizing a first electrode (142) resting on the substrate (104) and disposed against the dielectric portions (130) and side flanks (134) of the second portion (132) of the first semiconductor portion (126). ), the first electrode (142) being electrically connected to the first semiconductor portion (126) only by contact with the side flanks (134) of the second portion (132) of the first semiconductor portion (126). ), and making a second portion of the second electrode (144) on the first portion (119) of the second electrode (144).
    [12" id="c-fr-0012]
    The method of claim 11, wherein the first etching of the layer stack is implemented through a dielectric mask (118) disposed on the layer stack, and wherein the dielectric portions (130) overlap with lateral flanks of the dielectric mask (118).
    [13" id="c-fr-0013]
    The method of claim 12, wherein the second etching of the stack is performed such that outer side flanks of the dielectric portions (130) are aligned with the side flanks (134) of the second portion (132) of the first portion. semiconductor portion (126).
    [14" id="c-fr-0014]
    14. Method according to one of claims 12 or 13, wherein the embodiment of the first electrode (142) and the second portion of the second electrode (144) comprises the implementation of the following steps: - realization of a opening (136) through the dielectric mask (118) and opening on the first portion (119) of the second electrode (144); depositing at least one electrically conductive material (138, 140) in the opening (136) and in a space (128) formed through the stack of layers by the implementation of the first and second etchings; - Planarization of the electrically conductive material (138, 140) with stop on the dielectric mask (118).
    [15" id="c-fr-0015]
    15. A method of producing an electronic device (100), comprising the implementation of a method according to one of claims 11 to 14, wherein the steps implemented form several diodes (102) such that each of the first electrodes (142) is electrically connected to the first semiconductor portion (126) of at least one adjacent diode (102) only by contact with the lateral flanks (134) of the second portion (132) of the first semiconductor portion (126) of said at least one neighboring diode (102).
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    法律状态:
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    2017-04-28| PLSC| Publication of the preliminary search report|Effective date: 20170428 |
    2017-10-31| PLFP| Fee payment|Year of fee payment: 3 |
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    2021-10-29| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1560077A|FR3042913B1|2015-10-22|2015-10-22|MICROELECTRONIC DIODE WITH OPTIMIZED ACTIVE SURFACE|
    FR1560077|2015-10-22|FR1560077A| FR3042913B1|2015-10-22|2015-10-22|MICROELECTRONIC DIODE WITH OPTIMIZED ACTIVE SURFACE|
    EP16785124.5A| EP3365924B1|2015-10-22|2016-10-20|Microelectronic diode with optimised active surface|
    US15/769,962| US11075192B2|2015-10-22|2016-10-20|Microelectronic diode with optimised active surface|
    CN201680061766.8A| CN108140701B|2015-10-22|2016-10-20|Microelectronic diode with optimized active surface|
    PCT/EP2016/075199| WO2017068029A1|2015-10-22|2016-10-20|Microelectronic diode with optimised active surface|
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