• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The method of smoothing the consumed current (Ivdd) is based on a sequence of current recopies (4, 5, 7) and on a current source (61) delivering a reference current (Iset) so that the current consumed (Ivcc) seen from the power supply depends only on the reference current (Iset).
    公开号:FR3042066A1
    申请号:FR1559354
    申请日:2015-10-01
    公开日:2017-04-07
    发明作者:Nicolas Demange；Jimmy Fort；Thierry Soude
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    Method of smoothing a current consumed by an integrated circuit and corresponding device
    Embodiments and embodiments of the invention relate to integrated circuits, more particularly integrated circuits that include secure modules, and in particular the protection of these modules against external attacks of the SPA type ("Simple Power Analysis"). .
    An integrated circuit comprising a module may be the target of attacks aimed at the recovery of secure information, and in particular attacks by consumption analysis or SPA.
    In operation, an integrated circuit consumes more or less depending on the operations it performs. The SPA attack involves the analysis of these consumption variations in order to deduce in particular indications on the operations carried out and / or on their occurrences.
    In secure applications, it is therefore recommended to smooth as much as possible the consumption seen from the power supply so that a potential attacker can hardly determine the activity of the various components of the circuit by SPA attacks.
    There are means of protection against attacks SPA, including for example shunt regulators ("shunt regulator" according to the English name), but these means are not particularly suitable for smoothing the current consumed by several modules.
    According to one embodiment, it is proposed a different and simple way to smooth the current seen from the power supply of an integrated circuit, and which is also compatible with an integrated circuit possibly including several secure modules.
    According to one aspect, there is provided a method of smoothing the current consumed by a supply of an electronic circuit, said electronic circuit comprising at least one module, for example a microprocessor, a memory, etc., powered directly or indirectly, for example via a voltage regulator, by said power supply and consuming a module current.
    In the method according to this aspect, a module auxiliary current is produced within the circuit, for each module, equal to a first fraction of the corresponding module current, and the circuit of a first stage, powered by the power supply, comprising at least one main current source providing a main current greater than the sum of the maximum values of each module auxiliary current, said first stage delivering a stage current at least equal to said main current, - an intermediate current is produced equal to the difference between the stage current and a secondary current equal to the sum of each module auxiliary current, and multiplying in a terminal stage supplied by said power supply, the intermediate current by a multiplication factor equal to inverse of said first fraction increased by one.
    Thus, in the method according to this aspect, a plurality of currents consumed by the power supply, the sum of which does not depend on the current consumed by each module but only in theory of the current supplied by the current source stage, is easily developed. .
    The consumption of the integrated circuit is smoothed, and this overall consumption smoothed from the outside is greater than the sum of the maximum consumption of each module.
    The main current delivered by the main current source may be a second fraction of a reference current. This second fraction may be equal to the first fraction, and of course in this case the reference current is greater than the sum of the maximum values of each module auxiliary current.
    The first stage may furthermore comprise at least one additional activatable current source supplying an additional current and the stage current is equal to the sum of the main current and each additional current delivered by each additional activated current source.
    Thus, by successively and / or simultaneously activating the different current sources, the current consumed by the power supply varies, which makes it even more difficult to detect variations in the module current. In this respect, it is also possible to add capacitive noise within the device, for example at the output of the first stage.
    In another aspect, there is provided an electronic device comprising - a power supply terminal, - at least one module connected to the power supply terminal and configured to consume a module current, - first generating means connected to the supply terminal and configured to develop for each module a module auxiliary current equal to a first fraction of the corresponding module current, - a first stage, connected to the power supply terminal, comprising at least one main current source configured to supplying a main current greater than the sum of the maximum values of each module auxiliary current, the first stage being configured to deliver a stage current at least equal to said main current, - second generation means configured to develop an intermediate current equal to the difference between the floor current and a secondary current equal to the sum of module auxiliary current, - a terminal stage connected to the power supply terminal and configured to multiply the intermediate current by a multiplication factor equal to the inverse of said first fraction increased by one.
    The main current may be equal to a second fraction of a reference current and the main current source may include a control input for receiving a control signal for selecting the value of the second fraction from a set of values. The first fraction may be equal to the second fraction, and in this case the reference current is greater than the sum of the module auxiliary currents.
    The device advantageously comprises a succession of current copying means.
    Thus, the first generating means may comprise for each module a first copy factor current mirror equal to said first fraction, having a first output delivering the corresponding module current and a second output delivering the corresponding module auxiliary current.
    The second generation means may comprise a second copy factor current mirror equal to one, and the second output of the first current mirror is connected to the input of the second current mirror and the output of the second current mirror is connected to the output of the first stage of current source (s). The terminal stage may comprise a current copying means having a copy factor equal to said multiplication factor and whose input is connected to the output of the second processing means and the output of which is connected to the power supply terminal. .
    According to one embodiment, the terminal stage comprises a first MOS transistor connected to the output of the second current mirror, and at least one second MOS transistor connected between the supply terminal and ground, the gates of the MOS transistors being mutually connected.
    And, in order to ensure better current copying by the second elaboration means, in particular when the module auxiliary current or the sum of the module auxiliary currents is close to said stage current, it is also possible to add an intermediate operational amplifier. whose non-inverting input is connected to the output of the second current mirror, whose inverting input is connected to the input of the second current mirror, and whose output is connected to the gates of the MOS transistors of the stage terminal.
    Also in order to improve the current copying, the first production means can comprise for each module a cascode first stage connected between the second output of the corresponding first current mirror and the input of the second current mirror, the first cascode stage. comprising a first PMOS transistor and a first operational amplifier whose non-inverting input is connected between the power supply terminal and the corresponding module, whose inverting input is connected to the source of the first PMOS transistor and whose output is connected at the gate of the first PMOS transistor,
    A second cascode stage may also be connected between the output of the terminal stage and the power supply terminal, the cascode stage comprising a second PMOS transistor and a second operational amplifier whose non-inverting input is connected between the output of the the terminal stage and the second PMOS transistor, the inverting input is connected to the input of the terminal stage, and whose output is connected to the gate of the second PMOS transistor.
    The first stage may comprise at least one additional current source that can be activated independently of the main current source, the outputs of all the current sources being connected to the output of the first stage.
    The electronic device may further comprise a capacitive noise generator, for example connected to the output of the first stage.
    A controller configured to provide a regulated voltage to said at least one module may be connected between the power supply terminal and the at least one module. This regulator can include the first means of elaboration.
    According to one embodiment, the device may comprise several modules, and the first processing means comprise a plurality of first outputs respectively connected to said modules so as to deliver the respective module currents and several second outputs connected together to the input of the first means. of elaboration so as to deliver the secondary current. Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and embodiment of the invention, in no way limiting, and the accompanying drawings in which - Figures 1 to 6 show schematically modes of implementation of the invention.
    In the remainder of the description, the terms "coupled" and "connected" denote an electrical connection which is either direct or indirect via other devices or connection means.
    In FIG. 1, the reference DIS designates an electronic device according to one embodiment of the invention.
    The device DIS comprises a module 1, for example a microprocessor of a smart card. The device can be located within the integrated circuit of the smart card.
    The device DIS further comprises a power supply terminal 2 intended to receive a supply voltage Vcc, for example a voltage of 5 volts.
    The device also comprises first generation means 4, comprising a first input E31 and a second input E32 connected to the power supply terminal 2 and a first output S31, and a second output S32.
    The device also comprises second generation means 5 comprising an input E5 and an output S5, a terminal stage 7 comprising an input E7 and an output S7, and a first stage 6 of source (s) of current (s) comprising a E6 input and S6 output. Their respective connections and characteristics will be described in more detail below.
    A regulator 3 is connected between the power supply terminal 2 and the microprocessor 1, so as to deliver a regulated voltage Vdd to the microprocessor, for example here a voltage of 2.5 volts.
    The microprocessor 1 consumes a current Ivdd, whose value depends on the operations it performs.
    In this example, the regulator 3 comprises the first generating means 4, here a first current mirror which supplies at the input E5 of the second generating means 5, an auxiliary current equal to a first fraction of the current consumed Ivdd In this example, the current mirror has a copy factor equal to 1/100, that is to say it delivers an auxiliary current of module equal to one hundredth of the current consumed Ivdd (the first fraction is equal to at 1/100).
    The first current mirror conventionally comprises two transistors 41 and 42 mutually coupled by their gates.
    The first transistor 41, for example a PMOS transistor, is diode-mounted. Its source S41 which forms the first input E31 of the first elaboration means is connected to the first power supply terminal, and its drain D41, which forms the first output S31 of the first elaboration means, is connected to the module 1.
    The second transistor 42, for example a second PMOS transistor, has its source S42, which forms the second input E32 of the first generating means 4, connected to the supply terminal 2, and its drain D42, which forms the second output S32 of the first elaboration means, is connected to the input E5 of the second elaboration means 5.
    In order to obtain the first fraction of the consumed current IVdd, it is possible to choose the second PMOS transistor having a ratio W42 / L42 between the width W42 and the length L42 of its channel, which is 100 times lower than the ratio W41 / L41 between the width W41 and the length L41 of the channel of the first transistor 41.
    An alternative solution would be to have a plurality of first transistors 41 connected in parallel and one or more second transistors 42 identical to the first transistors 41 and connected in parallel, so that the number of first transistors is 100 times greater than the number of second transistors.
    The second generation means 5 comprise in this example a second current mirror, with a copy factor equal to one, which conventionally comprises two identical transistors 51 and 52, for example NMOS transistors, mutually coupled by their gates G51 and G52.
    The first NMOS transistor 51 is diode-mounted. Its drain D51, which forms the input E5 of the second elaboration means 5, is connected to the drain D42 of the second PMOS transistor 42 of the first current mirror, and its source S51 is connected to the ground GND.
    The second NMOS transistor 52 has its source S52 connected to ground, and its drain D52, which forms the output S5 of the second generating means 5, is connected to the input E7 of the terminal stage 7 and to the output S6 first floor 6.
    Thus, the second elaboration means receive at the input E5 the auxiliary current of the Iaux module and recopying at the output S5 this same auxiliary current of the module Iaux.
    The first stage 6 here comprises a main current source 61 connected between the supply terminal 2 and the input E7 of the terminal stage.
    This main current source 61 is configured to deliver to the input E7 of the terminal stage 5, a main current Ip here equal to a second fraction of a reference current Iset.
    The first fraction is chosen here equal to the second fraction. So, in this example where the auxiliary current of module Iaux is equal to
    and the main current Ip is equal to
    The reference current Iset is chosen to be greater than the maximum value of the module current Ivdd.
    This maximum value is for example determined by simulation during the design of the integrated circuit taking into account the foreseeable activity of the module 1.
    Since the reference current Iset is greater than the maximum value of the maximum module current, the main current Ip is greater than the maximum value of the auxiliary current of the module I.sub.aux.
    The main current source 61 may further include a control input 62 for receiving a control signal SC for selecting the second fraction from a predefined set of values.
    For example, the set of values can be, and the main current Ip delivered can therefore be equal to
    Since the first stage 6 delivers a main current Ip equal to the terminal stage 7 thus receives at its input E7 a positive intermediate current Lnt equal to
    In this example, the terminal stage 7 comprises a third copy factor current mirror equal to the inverse of the first fraction increased by 1. In this example, the third current mirror therefore has a copy factor equal to 101.
    This third current mirror conventionally comprises third and fourth transistors 71 and 72, for example here NMOS transistors, mutually coupled by their gates G71 and G72.
    The third NMOS transistor 71 is diode-mounted. Its source S71 is connected to ground, and its drain D71, which forms the input E7 of the terminal stage, is connected to the output S5 of the second elaboration means and to the output S6 of the first stage.
    The fourth NMOS transistor 72 has its source S72 connected to the ground GND and its drain D72 connected to the supply terminal 2.
    In order to obtain a multiplication factor equal to 101, it is possible to choose a fourth NMOS transistor 72 whose ratio W72 / L72 between the width W72 and the length L72 of its channel is 101 times greater than the ratio W71 / L71 between the width W71. and the length L71 of the channel of the third transistor 71.
    An alternative solution would be to have one or more third transistors 71 connected in parallel and a plurality of fourth transistors 72 identical to the third transistors 71 and
    mounted in parallel, so that the number of fourth transistors is 101 times greater than the number of third transistors.
    Thus, the terminal stage generates a current Iterm equal to 101 times the intermediate current Iint, here a current
    In operation, the DIS device thus configured consumes - the first current Ivdd, - the module auxiliary current - the main current
    , and - the terminal current I term - 101 * (Ip-Iaux) ·
    The current IVCc consumed by the power supply is therefore equal to the sum of these currents, ie 1.02 Iset, and therefore does not depend on the current of module Ivdd but only on the reference current Iset, which is constant and here greater than the maximum value of the module current Ivdd · Figure 2 illustrates a second embodiment of the invention. In this embodiment, the DIS device as described above has been modified so that the third NMOS transistor 71 of the terminal stage is no longer mounted as a diode.
    An operational amplifier 8 has been added between the second generation means 5 and the terminal stage 7.
    Its non-inverting input is connected to the input E7 of the terminal stage, and its inverting input is connected to the mutually coupled gates G51 and G52 of the first and second NMOS transistors 51 and 52, ie to the first one. input E5 of the second processing means 5 since the first NMOS transistor 51 is diode-mounted.
    The output of the amplifier 8 is connected to the mutually coupled gates G71 and G72 of the third NMOS transistor 71 and the fourth NMOS transistor 72.
    Thus, by driving the gate G71 of the third NMOS transistor 71 so as to equalize the potentials of the drains D51 and D52 of the first and second NMOS transistors 51 and 52, the operational amplifier makes it possible to obtain an intermediate current Iint at the input E7 of the terminal stage which is precisely equal to the difference between the current
    main Ip and auxiliary current of module IaUx, even if the auxiliary current of module Iaux has a value close to the main Ip current.
    According to another embodiment illustrated in FIG. 3, the device DIS can also comprise a first cascode stage 9 coupled to the second output S32 of the first production means 4, and a second cascode stage 10 coupled to the output S7 of the terminal floor.
    The cascode first stage 9 comprises a third PMOS transistor 91 whose source S91 is connected to the second output S32 of the first elaboration means, and whose drain D91 is coupled to the input E5 of the second elaboration means 5. cascode stage 9 furthermore comprises a second operational amplifier 92, whose non-inverting input is coupled to the first output S31 of the first generation means 4 and whose non-inverting input is coupled to the second output S32 of the first output means 4. The output of the second operational amplifier 92 is coupled to the gate G91 of the third PMOS transistor 91.
    Thus, the first cascode stage 9 makes it possible to equalize the voltages at the first and second outputs S31 and S32 of the first elaboration means, which contributes to obtaining the desired ratio 1/100 between the current Ivdd and the auxiliary current.
    The second cascode stage 10 comprises a fourth PMOS transistor 101, whose source S101 is connected to the first power supply terminal 2, and whose drain D101 is connected to the output S7 of the terminal stage.
    The second cascode stage 10 further comprises a third operational amplifier 102, the non-inverting input of which is connected to the output S7 of the terminal stage, whose inverting input is connected to the input E7 of the terminal stage. . The output of the amplifier is connected to the gate G101 of the fourth PMOS transistor 101.
    Thus, the second cascode stage 10 makes it possible to equalize the voltages at the input E7 and at the output S7 of the terminal stage, which contributes to obtaining the desired ratio 101 between the intermediate current Iint and the terminal current Iterm.
    The two cascode stages 9 and 10 thus make it possible to improve the accuracy of the current copies respectively made by the first drawing means 4 and the terminal stage 7.
    FIG. 4 illustrates one embodiment of the invention, in which the first stage 6 has been modified with respect to the device DIS described previously and illustrated in FIG. 1.
    In this embodiment, the first stage comprises, in addition to the main current source 61 delivering the second fraction of the Iset reference current, a first additional current source 63 delivering a first additional current Ii and a second additional current source. 64 delivering a second additional current h.
    The three current sources, 61, 63, and 64 are connected in parallel between the power supply terminal 2 and the output S6 of the first stage 6, and the first and second additional sources 63 and 64 are also activatable independently of the main current source 61.
    The stage stage current delivered by the first stage 6 is therefore a current equal to the sum of the main current Ip, the first additional current Ii and the second additional current h when the two additional current sources 63 and 64 are activated.
    The total current IVcc consumed by the feed is then Ivcc = 1.02 * Iset + 102 * / x + 102 * / 2.
    The first and second additional current sources 63 and 64 being independently activatable, the current IVCc consumed by the power supply can take successively different values from the following set of values: - Ivcc = 1.02 * Iset + 102 * / x + 102 * / 2) - Ivcc = 1,02 * Iset + 102 * / x, - Ivcc = 1,02 * Iset + 102 * Z2, - Ivcc = 1,02 * Iset.
    Thus, the detection of variations of the Ivdd module current is even more difficult to detect by consumption analysis attacks (PPS).
    It should be noted that this modification of the first stage is compatible with the embodiments illustrated in FIGS. 2 and 3. It is presented here from the embodiment illustrated in FIG. 1 only for purposes of simplification.
    According to a variant illustrated in FIG. 5, it is also possible to add a capacitive noise generator at the output S6 of the first stage.
    For example, here the capacitive noise generator 11 comprises a capacitor 110, an inverter 111 and control means 112.
    The first capacitor is connected by a first terminal to the output S6 of the first stage and by a second terminal to the inverter 111. The inverter 111 is supplied between the supply terminal 2 and the ground GND. The control means 112 are connected to the inverter 111 in a manner depending on the output of the inverter, to charge or discharge the capacitor 110.
    This embodiment is also compatible with the embodiments of FIGS. 1, 2, 3, and 4.
    According to a variant of the invention, the device may comprise several modules.
    For example, in the embodiment illustrated in FIG. 6, the device DIS comprises a second module 12, for example a second microprocessor, which consumes a second module current Ivdd2, and a second regulator 13 coupled between the supply terminal 2 and the second module, also comprising first processing means 14.
    The first generating means 14 thus deliver a second auxiliary current of module Iaux2 equal to the first fraction of the second module current Ivdd2, at the input E5 of the second elaboration means 5. In this example,
    Thus, the second elaboration means 5 receive on their input E5 a secondary current Isec equal to the sum of the auxiliary currents of module Iraux and Iaux2.
    In this example, the main current Ip is slightly greater than the maximum value of the secondary current Isec.
    This embodiment is compatible with all the embodiments described above and illustrated by FIGS. 1 to 5.
    It should be noted that although embodiments have been described in which the current regulators 3 and 13 comprise the first generating means 4 and 14, an embodiment in which the regulators 3 and 13 are separate from the first means of elaboration 4 and 14 is entirely conceivable.
    In addition, regulators are not essential. Indeed, each module could be powered by the supply voltage Vcc through a current mirror.
    In addition, although an efficient injection of capacitive noise at the output S6 of the first stage 6 has been described, it would also be possible to inject capacitive noise onto other nodes, for example at the input E5 of the second elaboration means 5. or at the output of the operational amplifier 8.
    权利要求:
    Claims (18)
    [1" id="c-fr-0001]
    1. A method of smoothing the current (Ivcc) consumed by a supply of an electronic circuit, said electronic circuit comprising at least one module (1) supplied directly or indirectly by said power supply and consuming a module current (Ivdd), a method of which - a module auxiliary current equal to a first fraction of the current (Ivdd, Ivdd2) of corresponding module is produced within the circuit, for each module (1, 12), - the circuit is equipped with a first stage (6), powered by the power supply, having at least one main current source (61) providing a main current (Ip) greater than the sum of the maximum values of each auxiliary circuit current (Iaux), said first stage (6) ) delivering a stage current at least equal to said main current (Ip), an intermediate current equal to the difference between the stage current and a secondary current (Isec) equal to the sum of each auxiliary current (Iaux) module, and - one multiplies in a terminal stage (7) fed by said supply, the intermediate current by a multiplication factor equal to the inverse of said first fraction increased by one.
    [2" id="c-fr-0002]
    2. Method according to claim 1, wherein the main current is equal to a second fraction of a reference current and said first fraction is equal to said second fraction.
    [3" id="c-fr-0003]
    The method of claim 2, wherein the value of said second fraction is selected from a set of values.
    [4" id="c-fr-0004]
    4. Method according to one of the preceding claims wherein said first stage (6) further comprises at least one additional activatable current source (63, 64) delivering an additional current (11, 12) and the stage current ( Istage) is equal to the sum of the main current (Ip) and each additional current (Ii, I2) delivered by each additional current source (63, 64) activated.
    [5" id="c-fr-0005]
    5. Method according to any one of claims 1 to 4, wherein capacitive noise is added within the electronic circuit.
    [6" id="c-fr-0006]
    An electronic device comprising - a power supply terminal (2), - at least one module (1,12) connected to the power supply terminal (2) and configured to consume a module current (Ivdd), - first generating means (4) connected to the power supply terminal (2) and configured to develop for each module (1, 12) a module auxiliary current (Iaux) equal to a corresponding first fraction of the corresponding module current (Ivdd) a first stage (6), connected to the power supply terminal (2), comprising at least one main current source (61) configured to supply a main current (Ip) greater than the sum of the maximum values of each current auxiliary module (Ivdd, Ivdd2), the first stage (6) being configured to deliver a stage current (stage) at least equal to said main current (Ip), - second forming means (5) configured to develop an intermediate current equal to the difference between the stage current and a secondary current (ISec) equal to the sum of each module auxiliary current (Iaux, Iaux2), - a terminal stage (7) connected to the power supply terminal (2) and configured to multiply the current intermediate by a multiplication factor equal to the inverse of said first fraction increased by one.
    [7" id="c-fr-0007]
    7. Device according to claim 6, wherein the main current is equal to a second fraction of a reference current (Iset) the first fraction is equal to the second fraction.
    [8" id="c-fr-0008]
    The apparatus of claim 7, wherein the main current source (61) includes a control input (62) for receiving a control signal for selecting the value of the second fraction from a set of values.
    [9" id="c-fr-0009]
    9. Device according to one of claims 6 to 8, wherein - the first generating means (4) comprise for each module, a first copy factor current mirror equal to said first fraction having a first output (S31 ) delivering the corresponding module current (Ivdd) and a second output (S32) delivering the corresponding module auxiliary current (Iaux, Iaux2), - the second generation means (5) comprise a second copy factor current mirror; equal to one, and - the second output (S32) of the first current mirror is connected to the input (E5) of the second current mirror and the output (S5) of the second current mirror is connected to the output (S6) first floor
    [10" id="c-fr-0010]
    10. Device according to one of claims 6 to 9, wherein the terminal stage (7) comprises a current copying means having a copy factor equal to the multiplication factor, whose input (E7) is connected to the output (S5) of the second processing means (5) and whose output (S7) is connected to the supply terminal (2).
    [11" id="c-fr-0011]
    11. Device according to claim 10, wherein the terminal stage (7) comprises a first MOS transistor (71) connected to the output (S5) of the second current mirror, and at least one second MOS transistor (72) connected between the supply terminal (2) and the ground (GND), the grids (G71, G72) of the MOS transistors (71, 72) being mutually connected, and the device (DIS) further comprises an operational amplifier (8) intermediate whose non-inverting input is connected to the output (S5) of the second current mirror, whose inverter input is connected to the input (E5) of the second current mirror, and whose output is connected to the gates ( G71, G72) of the MOS transistors.
    [12" id="c-fr-0012]
    12. Device according to one of claims 9 to 11, wherein - the first generating means (3) comprise for each module (1, 12) a cascode first stage (9) connected between the second output (S32) of the first corresponding current mirror and the input (E5) of the second current mirror, the first cascode stage (9) comprising a first PMOS transistor (91) and a first operational amplifier (92) whose non-inverting input is connected between the supply terminal (2) and the corresponding module (1, 12), whose inverting input is connected to the source (S91) of the first PMOS transistor (91) and whose output is connected to the gate (G91 ) of the first PMOS transistor (91), and - the device (DIS) further comprises a second cascode stage (10) connected between the output (S7) of the terminal stage (7) and the supply terminal (2) , comprising a second PMOS transistor (101) and a second operational amplifier (102) whose non-inverting input is connected between the output (S7) of the terminal stage and the second PMOS transistor (101), the inverting input is connected to the input (E7) of the terminal stage (7) , and whose output is connected to the gate (G101) of the second PMOS transistor (101).
    [13" id="c-fr-0013]
    Apparatus according to any of claims 6 to 12, wherein the first stage (6) comprises at least one additional current source (63,64) activatable independently of the main current source (61), the outputs of all current sources (61, 63, 64) being connected to the output (S6) of the first stage (6).
    [14" id="c-fr-0014]
    14. Device according to one of claims 6 to 13, further comprising a capacitive noise generator (11).
    [15" id="c-fr-0015]
    15. Device according to any one of claims 6 to 14, comprising at least one regulator (3, 13) connected between the supply terminal (2) and said at least one module (1, 12), configured to deliver a regulated voltage (Vdd, Vdd2) to said at least one module (1, 12).
    [16" id="c-fr-0016]
    16. Device according to claim 15, wherein said at least one regulator comprises the first elaboration means.
    [17" id="c-fr-0017]
    17. Device according to any one of claims 6 to 16, comprising a plurality of modules (1, 12) and wherein the first generating means comprise a plurality of first outputs (S31) respectively connected to said modules (1, 12) so as to supplying the respective module currents (Ivdd, Ivdd2) and several second outputs (S32) connected together to the input (E5) of the second generating means (5) so as to deliver the secondary current ISec-
    [18" id="c-fr-0018]
    18. Device according to one of claims 6 to 17, implemented in an integrated manner
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    FR2975511A1|2012-11-23|DEVICE FOR GENERATING A REFERENCE CURRENT PROPORTIONAL TO ABSOLUTE TEMPERATURE, WITH LOW POWER SUPPLY VOLTAGE AND HIGH FEED REJECTION RATE
    EP3961344A1|2022-03-02|Power supply for electronic circuit
    EP3961345A1|2022-03-02|Power supply for electronic circuit
    FR3047815B1|2018-03-09|DEVICE FOR CONTROLLING A CURRENT IN AN UNKNOWN CURRENT-VOLTAGE CHARACTERISTIC CHARGE
    同族专利:
    公开号 | 公开日
    FR3042066B1|2017-10-27|
    CN205788193U|2016-12-07|
    DE102016106800A1|2017-04-06|
    US10054973B2|2018-08-21|
    US20170192448A1|2017-07-06|
    CN109656305A|2019-04-19|
    US20170097653A1|2017-04-06|
    US9678525B2|2017-06-13|
    CN106560757A|2017-04-12|
    CN106560757B|2019-01-11|
    CN109656305B|2020-11-24|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    EP0368727A1|1988-11-10|1990-05-16|Sgs Thomson Microelectronics Sa|Security device against the unauthorised detection of protected data|
    FR2793904A1|1999-05-21|2000-11-24|St Microelectronics Sa|Control of the current taken by an electronic circuit used in reading the security code from a device such as a bankers card of portable telephone to mask the period during which the code is read, but to reduce the masking period|
    WO2004027688A2|2002-09-19|2004-04-01|Stmicroelectronics Sa|Power supply for an asynchronous data treatment circuit|
    FR2857804A1|2003-07-17|2005-01-21|Atmel Corp|System for smoothing the current consumption in a digital logical module, e.g. a chip card, comprises a smoothing circuit that outputs a signal when a processing circuit is inactive|
    FR3007857A1|2013-06-26|2015-01-02|St Microelectronics Rousset|REGULATOR FOR INTEGRATED CIRCUIT|
    FR2776410B1|1998-03-20|2002-11-15|Gemplus Card Int|DEVICES FOR MASKING THE OPERATIONS CARRIED OUT IN A MICROPROCESSOR CARD|
    WO1999066452A1|1998-06-12|1999-12-23|Kreft Hans Diedrich|Chip card with an electronic security circuit|
    US6107868A|1998-08-11|2000-08-22|Analog Devices, Inc.|Temperature, supply and process-insensitive CMOS reference structures|
    JP2002149251A|2000-11-07|2002-05-24|Seiko Epson Corp|Semiconductor integrated circuit|
    GB0221240D0|2002-09-13|2002-10-23|Koninkl Philips Electronics Nv|Current source for cryptographic processor|
    US6963188B2|2004-04-06|2005-11-08|Atmel Corporation|On-chip power supply interface with load-independent current demand|
    KR100596978B1|2004-11-15|2006-07-05|삼성전자주식회사|Circuit for providing positive temperature coefficient current, circuit for providing negative temperature coefficient current and current reference circuit using the same|
    US8482266B2|2011-01-25|2013-07-09|Freescale Semiconductor, Inc.|Voltage regulation circuitry and related operating methods|
    US8334705B1|2011-10-27|2012-12-18|Certicom Corp.|Analog circuitry to conceal activity of logic circuitry|
    US8536934B1|2012-02-23|2013-09-17|Texas Instruments Incorporated|Linear voltage regulator generating sub-reference output voltages|
    US9081404B2|2012-04-13|2015-07-14|Infineon Technologies Austria Ag|Voltage regulator having input stage and current mirror|
    CN102664520A|2012-05-10|2012-09-12|东南大学|Phase-locked loop charge pump circuit with low current mismatch|
    US9104222B2|2012-08-24|2015-08-11|Freescale Semiconductor, Inc.|Low dropout voltage regulator with a floating voltage reference|
    CN104765397B|2014-01-02|2017-11-24|意法半导体研发有限公司|The ldo regulator with improved load transient performance for internal electric source|
    FR3042066B1|2015-10-01|2017-10-27|Stmicroelectronics Sas|METHOD FOR SMOOTHING A CURRENT CONSUMED BY AN INTEGRATED CIRCUIT AND CORRESPONDING DEVICE|FR3042066B1|2015-10-01|2017-10-27|StmicroelectronicsSas|METHOD FOR SMOOTHING A CURRENT CONSUMED BY AN INTEGRATED CIRCUIT AND CORRESPONDING DEVICE|
    FR3104751B1|2019-12-12|2021-11-26|St Microelectronics Rousset|Method of smoothing a current consumed by an integrated circuit and corresponding device|
    FR3113777A1|2020-08-25|2022-03-04|StmicroelectronicsSas|Electronic circuit power supply|
    FR3113776A1|2020-08-25|2022-03-04|StmicroelectronicsSas|Electronic circuit power supply|
    法律状态:
    2016-09-21| PLFP| Fee payment|Year of fee payment: 2 |
    2017-04-07| PLSC| Search report ready|Effective date: 20170407 |
    2017-09-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-09-19| PLFP| Fee payment|Year of fee payment: 4 |
    2019-09-19| PLFP| Fee payment|Year of fee payment: 5 |
    2021-07-09| ST| Notification of lapse|Effective date: 20210605 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1559354A|FR3042066B1|2015-10-01|2015-10-01|METHOD FOR SMOOTHING A CURRENT CONSUMED BY AN INTEGRATED CIRCUIT AND CORRESPONDING DEVICE|FR1559354A| FR3042066B1|2015-10-01|2015-10-01|METHOD FOR SMOOTHING A CURRENT CONSUMED BY AN INTEGRATED CIRCUIT AND CORRESPONDING DEVICE|
    DE102016106800.4A| DE102016106800A1|2015-10-01|2016-04-13|A method of smoothing a current consumed by an integrated circuit and corresponding device|
    CN201811553901.8A| CN109656305B|2015-10-01|2016-04-26|Method for smoothing the current consumed by an integrated circuit and corresponding device|
    CN201620363279.4U| CN205788193U|2015-10-01|2016-04-26|Electronic equipment|
    CN201610267137.2A| CN106560757B|2015-10-01|2016-04-26|Method for the electric current smoothly consumed by integrated circuit and corresponding equipment|
    US15/150,713| US9678525B2|2015-10-01|2016-05-10|Method for smoothing a current consumed by an integrated circuit and corresponding device|
    US15/467,927| US10054973B2|2015-10-01|2017-03-23|Method for smoothing a current consumed by an integrated circuit and corresponding device|
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