• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    Realization of a device for connecting a nano-object to an external electrical system (SEE) comprising: - a first chip having conductive areas (8a, 8b) and a first nano-object (50) connected to the conductive areas, the first chip being assembled on a support (70) so that the first nano-object is disposed facing an upper face of the support, the device being further provided with first connection elements (80a, 80b) adapted to be connected to the external electrical system and arranged on and in contact with the first conductive regions (8a, 8b), the first connection elements being formed on the side of the upper face of the support (70) and being accessible on the side of the upper face of the support .
    公开号:FR3042064A1
    申请号:FR1559467
    申请日:2015-10-05
    公开日:2017-04-07
    发明作者:Aurelie Thuaire；Patrick Reynaud；Patrick Leduc；Emmanuel Rolland
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    DEVICE FOR CONNECTING AT LEAST ONE NANO-OBJECT ASSOCIATED WITH A CHIP ALLOWING CONNECTION TO AT LEAST ONE EXTERNAL ELECTRICAL SYSTEM AND
    ITS PRODUCTION METHOD
    DESCRIPTION
    TECHNICAL FIELD AND PRIOR ART
    The present invention relates to a device for connecting nanoobjects to at least one external electrical system and a method of manufacturing such a device.
    "Nano-objects" means objects in which at least one of the dimensions is in the range from 0.1 nm to 1000 nm and more particularly from 1 nm to 100 nm, and in this category nano -objects, include nanoparticles (organic or inorganic), nano-son, molecules or associations of molecules, including biological molecules such as viruses and bacteria.
    We are now trying to characterize nano-objects that are smaller and smaller, or to make nanoscale structures. It is therefore necessary to manufacture a device for electrically measuring these nano-objects and to be able to connect them to an external electrical system configured to perform an electrical test of the nano-objects.
    The document US 2012/0161333 A1 provides an electrical connection of a nano-object through the rear face of a substrate, with the aid of a connection element passing through the substrate.
    To make such a device and to be able to connect the nano-object, it is generally necessary to traverse the entire thickness of the substrate. However, such a substrate may have a thickness of the order of several hundred microns.
    The document WO 2009/022982 A1 for its part provides an electrical connection of a nano-object through the rear face of a substrate, passing through a cavity formed in a portion of the thickness of the substrate, the nano-object being formed on a remaining portion of the substrate.
    This remaining portion may be fragile.
    There is the problem of making a new device for connecting a nano-object and a new method of producing such a device.
    STATEMENT OF THE INVENTION
    An embodiment of the present invention provides a device for connecting at least one nano-object to an external electrical system, the device comprising: at least one first chip having one or more first conductive regions and at least one first nano-object connected to said one or more first conductive areas, the first chip being assembled on a support so that the first nano-object is disposed facing an upper face of the support, the device being further provided with one or a plurality of first connection elements adapted to be connected to the external electrical system and disposed on and in contact with the first conductive areas, the first connection elements being formed on the side of the upper face of the support and being accessible on the side of the upper face of the support .
    A face called "first face" of the first chip on which the nano-object is located is arranged opposite the upper face of the support. The first connection elements are located on a second face of the first chip, that is to say the face of the first chip opposite to the first face.
    A lower face of the support opposite to said upper face forms a rear face of the device. The first connection elements are in turn accessible from the side of the front face of the device, that is to say a face of the device opposite to the rear face of the device, in other words to the underside of the support.
    With such an arrangement of the first connection elements, the formation of connections passing through the support is not essential to allow the nano-object to be connected to an external electrical system.
    Such an arrangement also makes it possible to implement short-length connection elements, which notably makes it possible to carry out electrical measurements of improved sensitivity on the nano-object.
    According to one possible implementation of the device, at least one second chip may be disposed on the support, the second chip also having one or more second conductive zones and a second nano-object connected to said second conductive zones.
    Advantageously, the support comprises at least one cavity at its upper face, the first nano-object not being in contact with said support.
    It is thus possible to realize a device whose space requirement is less while preserving this nano-object and providing protection thereof.
    According to one embodiment, another electrical connection element connected to the first nano-object passes through the support, this other connection element opening on a lower face of the support opposite to the upper face.
    The device may comprise at least one electronic circuit provided with one or more components, the circuit being assembled on the upper face of the support.
    The device may also comprise an electronic circuit integrated in the support.
    The device may also include an electronic circuit integrated with the support assembled on the first chip and connected to the first nano-object.
    The electronic circuit may be provided with amplification and / or filtering means for filtering and / or amplifying electrical test signals of the nano-object.
    According to another aspect, an embodiment of the present invention provides a method of producing a device for connecting at least one nano-object to an external electrical system, the method comprising the steps of: - assembling on a support a first chip having one or more first conductive regions and a first nano-object connected to said one or more first conductive regions, the assembly of the first chip on the support being constructed so that the first nano-object is disposed facing an upper face of the support, - make on the side of the upper face of the support one or more first connection elements disposed on and in contact with the first conductive areas.
    Advantageously, the nano-object is located on a first face of the first chip, opposite to a second face, the method further comprising between the assembly and the production of the first connection elements: a step of removing a thickness of the first chip on the side of his second face.
    Thus, this removal is carried out once the assembly has been made, which makes it possible to achieve access to the conductive zones of the chip without damaging it, the support providing mechanical rigidity during removal.
    The first chip may be formed from a substrate on which said first conductive areas are made.
    The method may further comprise a step of cutting the substrate into several chips. This allows a collective implementation of chips before assembly with the support.
    According to a possibility of implementing the method in which the nanoobject is formed on a first face of the first chip after the step of cutting the substrate, and in which, prior to cutting, a protective cover is formed on the first face , the removal of this protective cover prior to the formation of the first nano-object on the first face of the first chip.
    The nano-object may be formed on a first face of the first chip before the step of cutting the substrate, the cutting of the substrate then being performed after forming a protective cover on the first face.
    According to a possibility of implementing the method, the first nano-object can be positioned on an area of interest of the first chip by using patterns or marks delimiting this area of interest. The patterns may be for example in the form of holes or trenches.
    After assembly of the first chip on the support, it is possible to form a wall that is advantageously insulating around the first chip. This insulating wall can serve both for protection and electrical insulation of the first chip.
    A possibility of implementing the method provides a step of assembling a dummy block on the upper face of the support.
    Such a dummy block when attached to the first chip can improve the cohesion of the assembly between the first chip and the support.
    Such a dummy block may also make it possible to limit the relief of the assembly between the support and the first chip.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIG. 1 serves to illustrate a device according to an embodiment of the present invention for connecting at least one nano-object formed on a chip carried on a substrate; FIGS. 2A-2L illustrate, by way of cross-sectional views, an exemplary method of producing such a device; FIG. 3 illustrates an alternative embodiment in which the substrate is provided with at least one receiving cavity of the nano-object; FIG. 4 illustrates a particular exemplary embodiment in which at least one additional connection element passes through the thickness of the substrate to allow contact to be made on its lower face; FIG. 5 illustrates an exemplary embodiment in which an electronic circuit provided with a filtering and / or amplification block is placed on the same substrate as the one on which the chip equipped with the nano-object is postponed; FIG. 6 illustrates an exemplary embodiment in which the substrate on which the chip is carried is provided with at least one integrated circuit with one or more active components; FIG. 7 illustrates an exemplary embodiment in which an integrated circuit is reported on the chip which is assembled to the substrate and is provided with a nano-object; FIG. 8 illustrates an example of arrangement of connection pads connected to a nano-object disposed on a chip itself assembled to a substrate;
    Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    In addition, in the following description, terms that depend on the orientation, such as "before", "backward", "upper", "lower", etc. of a structure apply considering that the structure is oriented in the manner illustrated in the figures.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Referring now to Figure 1 giving a schematic sectional view of a particular embodiment of a device for connecting one or more nano-object (s) to an external electrical system.
    In the example of FIG. 1, the device is intended to connect a first nano-object 50, for example a molecule, to an external electrical system SEE.
    The electrical system may include an integrated circuit with a characterization device or a control device or a reading device. This system makes it possible, for example, to determine the electrical properties of the nano-object 50.
    The nano-object 50 is integrated on an element, such as a chip 30i, provided with conductive zones 8a, 8b to which the first nano-object 50 is connected. The chip 30i rests and is assembled on an upper face Fl of a support 70. The chip 30i can be turned over on the support 70 so that a face called "first face" on which the nano-object 50 is placed is located facing the upper face of the support 70.
    The external electrical system SEE is connected to the nano-object 50 by means of connection elements 80a, 80b arranged on and in contact with the conductive zones 8a, 8b of the first chip 30i in order to be able to circulate a current through the nanoobject. 50. The connection elements 80a, 80b are placed on the side of the upper face Fi of the support 70 and one face of the first chip 30i called "second face", the second face being opposite to said first face. These connection elements 80a, 80b may be formed of at least one stud 81 and / or at least one conductive line 82 and / or at least one conductive via 83 passing through a layer or stack of insulating layers 85 covering the first chip 30i.
    With such an arrangement, the connection elements 80a, 80b are advantageously accessible on the front face A of the device, on the side of the support-chip assembly where the nano-object 50 is located. The rear face B of the device opposite said face before A corresponds to the lower face F2 of the support, in other words to the face of the support which is opposed to its upper face F1. The arrangement of the elements 80a, 80b makes it possible to make a short-distance connection between the nano-object 50 to characterize and external electrical system, which improves the measurement sensitivity. In particular, a shorter connection, for example of length of the order of 400 nm, is produced with a connection element passing through the support 70, which can have a thickness, for example of the order of several hundred micrometers, and typically of the order of 725 pm.
    The support 70 is for example in the form of a semiconductor substrate and is able to accommodate, as in the particular exemplary embodiment of FIG. 1, at least one other chip 302. This other chip 302 may also be equipped with another nanoobject 60, for example from another molecule. Thus, one can co-integrate on the same support 70 several chips 30i, 302 with different nano-objects. A particular embodiment of the device provides for integrating both organic and inorganic nano-objects. The chips 30i, 302 may come from different laboratories or manufacturing sites.
    With such a device, it is also possible to carry out an individual addressing and an electrical measurement on each of the chips taken individually or alternatively to implement a collective electrical characterization of several chips 30i, 302, and possibly to interconnect several chips in series using a resumption of collective contact.
    An example of an electrical test consists in applying a voltage between the elements 80a, 80b respectively connected to the conductive zones 8a, 8b of the first chip 30i and measuring a current flowing through the nano-object, for example in the form of a molecule.
    In the particular embodiment of FIG. 1, the support 70 on which the chips 30i, 302 lie is covered with a layer 71 based on dielectric material, for example SiO 2, which can serve both as an interface bonding and electrical insulation.
    An encapsulation layer 52 covering and protecting the nano-object 50 may also be provided. This encapsulation layer 52 may for example be a layer of semiconductor material or advantageously an insulating layer.
    To improve the electrical insulation and the protection of the first chip 30i, it may also be surrounded by insulating walls 91, for example based on polymeric material or SiO 2, configured to form an insulating enclosure for protection around the puce 30i.
    An example of a method of manufacturing a device of the type previously described will now be given in conjunction with FIGS. 2A-2L.
    The starting material of this process may be a substrate 1 of the semiconductor-on-insulator type (FIG. 2A), in particular of the SOI (for "Silicion On Insulator") or GeOI or SiGeOI type, comprising a layer 2 of coated semiconductive support. an insulating layer 3 called BOX (for "Burrried Oxide"), itself coated with a superficial semiconductor layer 4, for example based on Si, Ge or SiGe. The surface layer 4 may have a thickness of, for example, between 10 nm and 1 μm, whereas the layer S102 may be between 10 nm and several μm. The layer 2 of semiconductive support can, for its part, have a thickness of between 625 nm nm and 1.5 mm.
    Patterns are then produced in the surface layer 4, in particular in the form of trenches 5 in order to delimit one or more areas of interest 4a of the surface layer 4, each area of interest being able to accommodate at least one nano-object (Figure 2B). The trenches 5 thus form location marks located around the zones of interest 4a and making it possible to locate these zones 4a. The zone or areas of interest 4a may have a surface area of, for example, between 10 nm 2 and 1 mm 2, in particular between 0.01 μm x 0.01 μm and 10 μm x 10 μm. To produce the trenches 5, for example, a photolithography technique is used in which a resin mask is formed, then the semiconductor layer 4 is etched through this mask and the resin mask is finally removed.
    Subsequently, conductive zones are formed in the surface layer 4. In this example, these conductive zones are doped zones 8a, 8b made in the zone (s) of interest 4a, in particular by implantation through masking ( not shown).
    The doped zones 8a, 8b produced inside a perimeter delimited by the trenches 5 or locating marks are able to be placed in electrical contact with at least one nano-object. Typically, two P or N-doped zones may be produced per area of interest 4a. The distance Δ between the two doped zones 8a, 8b can be for example between several nanometers and several hundred microns. This distance Δ depends on the size of the nano-object that will be brought into contact with these zones 8a, 8b. By way of example, a distance Δ of 0.1 μm may be provided when the nano-object has a length of the order of 150 nm.
    It is then possible to carry out a surface preparation step of the surface layer 4 in order, in particular, to functionalize it and possibly be able to subsequently carry out on this surface a grafting of molecule (s) or the manufacture of a nano-object.
    This functionalization can be carried out by heat treatment and / or chemical treatment. It is preferably preceded by a surface cleaning to remove any contaminants. A type of cleaning commonly known as "RCA" or "piranha" can be performed. Then, a cleaning is carried out in a solution of hydrofluoric acid (HF) for obtaining a hydrophobic surface, composed in particular of Si-H bonds. A heat treatment is then performed to order the atoms on the surface.
    Typically, an annealing between 850 ° C. and 1200 ° C. for several minutes, for example of the order of 7 min, under an atmosphere containing hydrogen, makes it possible to obtain a functionalized surface saturated with Si-H, where it will be possible to set molecules.
    Advantageously, the heat treatment implemented during the preparation of the surface of the surface layer 4 also makes it possible to activate the P or N dopants implanted previously in order to produce the conductive zones 8a, 8b. When such a treatment is performed on an Si (100) silicon plate, a reconstructed Si (001) - (2xl) surface is obtained.
    Then, a temporary protective cover 20 can be assembled on a first face of the substrate 1, that is to say on which the surface layer 4 is located (FIG. 2D).
    A hermetic protection of the first face of the substrate 1 is thus ensured. The assembly of the cover 20 on the substrate 1 can be achieved by a molecular bonding bonding, in particular of hydrophobic type, in which the hydrophobized surface of the surface layer 4 and for example saturated by Si-H bonds can be bonded. to another surface with Si-H bonds. Molecular adhesion bonding can be carried out at room temperature, typically of the order of 20 ° C.
    Then, a cutting of the substrate 1 assembled to the temporary cover 20 is performed in several elements 30i, 30k also called chips (Figure 2E).
    The chips 30i, 30k may have a size for example between several mm and several tens of centimeters, typically of the order of 1 cm 2. The cutting may possibly be performed so as to produce elements or chips of different sizes with respect to each other. This cutting is for example carried out using equipment with a thin blade for example of the order of 100 pm thick.
    In Fig. 2F, a subsequent step of removing the temporary cover on a first die 30i from the plurality of die chips is illustrated. The removal of the temporary cover 20 can be carried out, for example, using a blade which is inserted at the level of the bonding interface between the cover 20 and the first chip 30i and which is then used like a lever.
    A nano-object 50 is then formed on the upper face of the first chip 30i, that is to say on which the conductive zones 8a, 8b have been made (FIG. 2G). The nano-object 50 is arranged to be in contact with a portion of the implanted areas. The nano-object 50 may be, for example, in the form of organic or inorganic nano-particles, of molecule (s), in particular of biological molecule (s), such as a protein, DNA or a virus. , or an anti-body. In another example, the nanoobject 50 may be a nanowire
    By "formation" of the nano-object ", a surface modification (functionalization) and / or a grafting, or a bonding, or a deposit optionally followed by a structuring is included.
    The precise placement of the nano-object 50 over the area of interest 4a and the conductive areas 8a, 8b of this area 4a can be performed automatically by equipment configured to detect the location marks.
    An encapsulation layer 52 may then be formed to protect the nano-object 50 (Fig. 2H).
    For a nano-object 50 of organic nature, the encapsulation layer 52 may for example be based on resin. The encapsulation layer 52 is preferably formed at a low temperature. For an inorganic nano-object 50, it is possible, for example, to provide an encapsulation layer 52 made of silicon or silicon oxide. A particular embodiment provides for forming a semiconductor encapsulation layer 52 by epitaxial growth on the surface layer 4 of the substrate or an insulating layer made for example by a deposit. For a nano-object 50 of several nanometers in height, there is provided for example an encapsulation layer 52 of the order of 20 nm thick.
    Then, the first chip 30isassembled on a support 70, for example a semiconductor substrate based on silicon, or germanium, or SiGe, or glass or mica. The support 70 may be in particular a wafer (silicon wafer) with a diameter of the order of 100 mm, or 150 mm, or 200 mm, or 300 mm, or more. The support 70 for receiving the first chip 30i may have a large thickness, for example of the order of 725 pm.
    In the particular example of FIG. 21, the support 70 is coated on its surface with a passivation layer 71, for example based on SiCh or S13N4, for example. At this stage of the process, the support 70 on which the chip 30i is assembled may be provided with an integrated electronic circuit having in particular one or more active components forming filtering and / or amplification means. The assembly of the chip 30i and the support 70 is made for example by gluing or molecular adhesion. For this purpose, a surface cleaning sequence may be carried out in order to eliminate any contaminants and make the surface of the first chip 30i and the support 70 hydrophilic. A hydrophilic bonding of the first chip 30i on the support 70 makes it possible to obtain good adhesion. This molecular adhesion can be improved by carrying out thermal annealing, for example at a temperature of the order of 200 ° C. under a nitrogen or argon atmosphere. A good quality bonding is obtained when the support 70 is coated with a layer 71 of silicon oxide. Such a layer is typically made by thermal oxidation of a silicon substrate. The thermal oxide layer obtained has, for example, a thickness of between 50 nm and 1 μm.
    The support 70 may be provided to accommodate multiple elements or chips. In the assembly example illustrated in FIG. 21, an assembly is also made between a second chip 302 and the support 70. This second chip 302 is provided with a nano-object 60, which may be different from that arranged on the first chip 30i. The second chip 302 may be derived from the cut described above in connection with FIG. 2E or may have been manufactured totally independently of the first chip 30i.
    In order to be able to locate the location provided for the chips 30i, 302on can make alignment marks on the upper face of the support 70.
    The chips 30i, 302 may also be provided with specific alignment marks on the upper face so as to be able to place them accurately on the support 70. The marks and alignment marks may be, for example, in the form of trenches. The alignment marks provided on a chip 30i may have been made at the same time as the location marks 5, the embodiment of which has been described previously with reference to FIG. 2B.
    Alignment or superimposition of the marks and alignment marks of the chips 30i, 302 and the support 70 can therefore be carried out in order to make it possible to check the correct positioning of these two parts of the device with respect to the other.
    One or more additional elements can also be assembled on the upper face of the support 70. In the embodiment illustrated in FIG. 21, an additional element is also assembled in the form of a dummy block 80 Anglo-Saxon terminology) which has neither component nor connection element but can be provided to make it possible to standardize the stresses on the support 70 and / or to limit the relief. Such a dummy block contributes to the integral holding of the elements of the assembly and to avoid detachment of the chips 30i, 302 of the support 70. In this case, the block 80 may have a height substantially equal to that of the chips 30i, 302assembled on the support 70. In an advantageous embodiment this dummy block can have substantially the same dimensions as the chip to which it is juxtaposed
    Then, once this assembly is completed, an insulating layer 91 can be formed around chips 30i, 302 and block 80 (FIG. 2J). This insulating layer 91 may be arranged so as to fill gaps or spaces between the chips 30i, 302 and the block 80 and form a side wall or an enclosure making it possible to promote the integral retention of the assembly formed between the chips 30i, 302 , and the support 70. Such an insulating layer 91 can thus be provided to prevent the separation of the chips 30i, 302. The insulating layer 91 may for example be based on silicon oxide or polymer. The insulating layer 91 may also make it possible to perform an electrical chip chip isolation, to form a barrier for protecting the lateral flanks of the chips 30ι, 302.
    Such a step is particularly suitable when making a chip assembly of very small size, in particular of less than 1 mm 2 surface because the smaller the surface in contact with the substrate 2 and the greater the risk of separation between the chip and the chip. support is usually more important.
    In the case where it is necessary to remove a portion of the insulating layer 91 covering the chips 30i, 302, one can then planarization by CMP (for Chemical Mechanical Polishing).
    Then, the assembly is thinned, in particular on the side where the chips 30i, 302 are arranged.
    Thus, a portion of the second face of the first chip 30i, the second chip 302 and the block 80 (Figure 2K) are removed.
    This step can be carried out until reaching the insulating layer 3 of the starting substrate 1 from which the first chip 30i has been made. When the starting substrate 1 is, for example, a plate having a diameter of 200 mm, it is possible to remove a thickness, for example of the order of 725 μιτι of silicon, in order to achieve such thinning and to arrive at the insulating layer 3 of BOX. This removal can be done by engraving. The support 70 makes it possible to ensure rigid retention of the chips 30i, 302 during thinning.
    The removal of the support layer 2 can be carried out in two phases.
    According to a first phase, for example, at least 70% to 95% of the thickness of the support layer 2 of the substrate 1 is first removed by a material removal process according to a grinding technique ( "Grinding" according to the English terminology).
    Then, according to a second phase, the 20% to 5% is removed by stopping etching on the insulating layer 3 of the substrate. This etching can be carried out dry using a RIE type technique (for "Reactive Ion Etching") or a wet etching in a chemical solution for example based on TMAH. With a TMAH solution with a concentration of 20 to 50% by weight with a temperature of 50 to 90 °, an etching rate of the order of 0.2 to 1 μm can be obtained. Such a solution makes it possible to perform a selective etching with respect to an insulating layer 2 of the oxide support.
    This insulating layer 2 is then preserved.
    Connector elements 80a, 80b can then be made respectively on the doped zones 8a, 8b (FIG. 2L). These connection elements 80a, 80b are advantageously short and in particular have a length less than 1 μm in length. In the case where the insulating layer 3 has been preserved, these connection elements 80a, 80b are produced through the insulating layer 3 and possibly through one or more additional insulating layers 85 formed on the second face of the first chip 30i. The connection elements 80a, 80b are in contact with the doped zones 8a, 8b.
    The formation of the connection elements 80a, 80b may comprise, for example, a deposition by electrolysis or by PVD ("Physical Vapor Deposition") technique of conductive material such as, for example, AISi, W, Pt, Au , of ΙΆΙ, NiSi.
    The elements 80a, 80b of connection may have a diameter or a width typically of for example between 100 nm and several tens of microns typically of the order of 3 pm.
    The connection elements 80a, 80b may also have a height of, for example, between 10 nm and several μm, for example of the order of 400 nm.
    The connection elements 80a, 80b may each be formed of a conductive via 82 and / or a conductive line 83 ending for example by a conductive pad 81 on the surface of the assembly.
    A conductive pad 81 for example having a width greater than 70 μm and a length greater than 70 μm is for example designed to accommodate microtips of an external electrical system adapted to perform electrical measurements of the nano-object 50 An example of arrangement of conductive pads 81 on the surface of the support-chip assembly is given in FIG.
    A possibility of implementing the device provides the formation of connection elements for interconnecting different chips 30i, 302, between them and / or different nano-objects between them.
    We can ensure a collective contact recovery between all chips glued to perform a collective electrical measurement or on some chips. Such a resumption of collective contact makes it possible to measure several nano-objects in series and thus to increase the electric signal injected into a nano-object.
    An alternative embodiment of the previously described method example comprises, after the step of forming the nano-object 50 described in connection with FIG. 2G, to bring back a temporary protective cover on the first face of the substrate 1, so as to protect the nano-object 50. Bonding the same temporary cover 20, or a new temporary cover provides a hermetic protection of the nano-object 50 as the assembly with the support 70 is not realized.
    Another variant provides for using a temporary encapsulation layer of the nano-object, which is removed before making the assembly between the chip 30i and the support 70
    According to another variant illustrated in FIG. 3 of one or the other of the examples described above, the support 70 on which the chips 30i, 302 are assembled is provided on its upper face with cavities 75, 76 in which the nanoparticles objects 50, 60 of the chips 30i, 302 are housed.
    Such recesses 75, 76 make it possible to assemble the chips 30i, 302 on the support 70 without the nano-objects 50, 60 on which these chips 30i, 302 are arranged being crushed.
    In addition to providing protection for the nano-objects 50, 60, such recesses 75, 76 also make the device more compact. The cavities 75, 76 have larger expected dimensions than the nano-objects 50. For example cavities 75, 76 having an area of between 300 nm 2 and several hundred pm 2 and a depth between 500 nm 2 to several hundred pm2 can be provided. The cavities 75, 76 are made for example by photolithography and etching steps.
    In Figure 4, an alternative embodiment of the device provides an additional connecting element 90 through the thickness of the support 70 and opening on the bottom face F2 of the support 70 to allow to establish an electrical connection between a nano-object 50 disposed on the side of the upper face Fi of the support and an external electrical system (not shown). This additional connecting element 90 may be formed for example of a via 91 extending between the lower face F2 and the upper face Fi of the support 70, and at least one conductive line 92 and / or a conductive pad 93 arranged against the lower face F2 of the support 70. The additional connecting element 91 can be connected to an additional conductive zone 8c made on the first face of the chip 30i and in contact with the nano-object 50.
    In another exemplary embodiment illustrated in FIG. 5, provision is made to integrate an electronic circuit 100 disposed on the upper face F1 of the support 70. This electronic circuit 100, for example made in CMOS technology, is provided with one or more active components. The electronic circuit 100 may be provided with one or more amplification and / or signal filtering stages coming from one or the other of the chips 30i, 302. The electronic circuit 100 may also comprise an addressing device chips 30ι, 3Ο2.
    In the exemplary embodiment illustrated in FIG. 6, it is the support 70 itself which comprises at least one active electronic circuit, and in particular a first active circuit 101 on which the first chip 30i is located and connected as well as a second active circuit 102 on which the second chip 302 is arranged and connected. The support 70 may also comprise a block 103 provided with passive components between the first active circuit 101 and the second active circuit 102.
    In the exemplary embodiment illustrated in FIG. 7, after assembling the support 70 and the chips 30i, 302, circuits are reported on these chips 30i, 302, and in particular a first active circuit 201 that the it is arranged on the first chip 30i and a second active circuit 202 that is available on the second chip 302. As in the examples given above, the active circuits 201, 202 formed on the first chip 30i and on the second chip 302 may be equipped with amplification and / or filtering means.
    A device as previously described formed of an assembly between at least one chip and a support can itself be transferred to another support, possibly larger, or be transferred to assembly of the same type to produce a device multi-stage chips and nano-objects.
    A device finds applications in particular in electronics, optics, chemistry and biology.
    In particular, it can make it possible to produce, on the one hand, a molecular characterization device and, on the other hand, hybrid chips, for example hybrid MOS / molecule circuits. The invention makes it possible, among other things, to integrate molecular electronics with microelectronics, in particular with CMOS technology. The invention proposes, among other things, a device making it possible to characterize and exploit the electrical, optical, chemical, or even biological properties of molecules that have been synthesized by design. This device is obtained using tools, processes and infrastructures that have been developed in microelectronics for the manufacture of advanced MOS transistors (transistors with a small gate width). The invention also proposes a new architecture that makes it possible to integrate both molecular components and microelectronic components on the same substrate.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    A device for connecting at least one nano-object to an external electrical system (SEE), the device comprising: - at least one first chip (30i) having one or more first conductive regions (8a, 8b) and at least one first nano-object (50) connected to said one or more first conductive regions, the first chip being assembled on a support (70) so that the first nano-object is arranged opposite an upper face (F1) of the support, a lower face (F2) of the support forming a rear face (B) of the device, said lower face being opposite to said upper face of the support, the device further comprising a front face (A), opposite to said rear face , the front face being provided with one or more first connection elements (80a, 80b) able to be connected to the external electrical system and arranged on and in contact with the first conductive areas (8a, 8b) of the first chip, the first element s connection (80a, 80b) being accessible on the side of the front face of the device.
    [2" id="c-fr-0002]
    2. Device according to claim 1, wherein at least one second chip (3Ο2) is disposed on the support (70), the second chip also being provided with one or more second conductive zones (8a, 8b) and with at least one second nano-object (60) connected to said second conductive regions.
    [3" id="c-fr-0003]
    3. Device according to one of claims 1 or 2, wherein the carrier (70) comprises at least one cavity (75) at its upper face (Fl), the first nano-object (50) being housed in the cavity.
    [4" id="c-fr-0004]
    4. Device according to one of claims 1 to 3, further comprising at least one other electrical connection element (90) connected to the first nano-object and passing through the support (70), the other connecting element opening on the lower face (F2) of the device opposite to the upper face (A).
    [5" id="c-fr-0005]
    5. Device according to one of claims 1 to 4, further comprising at least one circuit (100) provided with one or more component (s) active (s) and / or passive (s), the circuit being arranged on the upper face (Fl) of the support (70).
    [6" id="c-fr-0006]
    6. Device according to one of claims 1 to 5, further comprising at least one dummy block (80) assembled on the upper face of the support (70).
    [7" id="c-fr-0007]
    7. Device according to one of claims 1 to 6, further comprising a circuit (101) integrated with the support (70) and provided with at least one active and / or passive component.
    [8" id="c-fr-0008]
    8. Device according to one of claims 1 to 7, further comprising a circuit (201) disposed on the first chip (30i), the circuit being provided with at least one active and / or passive component.
    [9" id="c-fr-0009]
    9. Device according to one of claims 5, 7 or 8, wherein the circuit is provided with amplification means and / or filtering.
    [10" id="c-fr-0010]
    10. A method of producing a device for connecting at least one nano-object to an external electrical system, the method comprising the steps of: - assembling on a support a first chip (30i) having one or more first zones conductors (8a, 8b) and at least one first nano-object (50) connected to said one or more first conductive regions, the assembly of the first chip on the support (70) being realized so that the first nano object is disposed facing an upper face (Fi) of the support, a lower face (F2) of the support forming a rear face of the device, the latter further comprising a front face (A) opposite to said rear face, - on the side of the front face (A) of the device one or more first connection elements disposed on and in contact with the first conductive zones (8a, 8b).
    [11" id="c-fr-0011]
    11. The method of claim 10, wherein the nano-object (50) is located on a first face of the first chip (30i), opposite a second face, the method further comprising between the assembly and the realization of first connection elements (80a, 80b), a step of removing a thickness of the first chip (30i) on the side of its second face.
    [12" id="c-fr-0012]
    The method according to one of claims 10 or 11, wherein the first chip (30i) is formed from a substrate on which said first conductive regions are formed, the method further comprising a step of cutting the substrate for delimit said first chip.
    [13" id="c-fr-0013]
    13. The method of claim 12, wherein the nano-object is formed on a first face of the first chip (30i) after the step of cutting the substrate, and wherein, prior to cutting forms a protective cover on the first face of the first chip, the protective cap being removed prior to the formation of the first nano-object (50) on the first face of the first chip.
    [14" id="c-fr-0014]
    The method according to one of claims 10 to 13, wherein the first chip (30i) is formed from a substrate, the method further comprising forming the first nano-object on the first chip, the first nano object being positioned on an area of interest of the first chip in which the first conductive areas are located using patterns (5) serving as markers delimiting the zone of interest.
    [15" id="c-fr-0015]
    15. Method according to one of claims 10 to 14, wherein after assembly of the first chip (30i) on the support, forms a wall advantageously insulating (91) on all or part of the periphery of the first chip.
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    同族专利:
    公开号 | 公开日
    EP3153462A1|2017-04-12|
    US20170098638A1|2017-04-06|
    FR3042064B1|2019-06-14|
    US10858244B2|2020-12-08|
    EP3153462B1|2019-04-17|
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    法律状态:
    2016-10-28| PLFP| Fee payment|Year of fee payment: 2 |
    2017-04-07| PLSC| Search report ready|Effective date: 20170407 |
    2017-10-31| PLFP| Fee payment|Year of fee payment: 3 |
    2018-10-30| PLFP| Fee payment|Year of fee payment: 4 |
    2019-10-31| PLFP| Fee payment|Year of fee payment: 5 |
    2021-07-09| ST| Notification of lapse|Effective date: 20210605 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1559467A|FR3042064B1|2015-10-05|2015-10-05|DEVICE FOR CONNECTING AT LEAST ONE NANO-OBJECT ASSOCIATED WITH A CHIP ENABLING A CONNECTION TO AT LEAST ONE EXTERNAL ELECTRICAL SYSTEM AND ITS IMPLEMENTATION METHOD|
    FR1559467|2015-10-05|FR1559467A| FR3042064B1|2015-10-05|2015-10-05|DEVICE FOR CONNECTING AT LEAST ONE NANO-OBJECT ASSOCIATED WITH A CHIP ENABLING A CONNECTION TO AT LEAST ONE EXTERNAL ELECTRICAL SYSTEM AND ITS IMPLEMENTATION METHOD|
    EP16191926.1A| EP3153462B1|2015-10-05|2016-09-30|Device for connecting at least one nano-object associated with a chip allowing a connection to at least one external electrical system and method for manufacturing same|
    US15/283,683| US10858244B2|2015-10-05|2016-10-03|Device for connecting at least one nano-object associated with a chip enabling a connection to at least one external electrical system and method of fabrication thereof|
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