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    • 专利摘要:
    The invention relates to a method for producing a memory cell comprising a step of forming a stack of layers comprising a first electrode (100) and a dielectric layer (300), characterized in that it comprises a training step a second electrode (200) comprising: - a step of depositing the second electrode (200) on the dielectric layer (300), - a step of defining the contour of said second electrode (200), so that the second electrode (200) forms a protruding element (250) above the dielectric layer (300) having inclined flanks (255), the angle α between the flanks (255) of the second electrode (200) forming an acute angle α with the plane in which the dielectric layer (300) extends mainly.
    公开号:FR3041808A1
    申请号:FR1559316
    申请日:2015-09-30
    公开日:2017-03-31
    发明作者:Sophie Bernasconi；Christelle Charpin-Nicolle；Luca Anthony De
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    FIELD OF THE INVENTION
    The present invention relates, in general, to a resistive memory cell, and more particularly to a non-volatile resistive memory cell and to its method of production.
    BACKGROUND
    OxRRAM resistive memories (acronym for "Oxide-Based Resistive Random Access Memories") typically comprising a metal oxide layer, are preferably chosen for non-volatile applications, in order to replace Flash type memories. . They have the particular advantage of being compatible with the end-of-line method (acronym BEOL in English for "Back-End Of Line") of the CMOS technology (acronym for "Complementary Metal-Oxide-Semiconductor").
    OxRRAM resistive memories are devices comprising in particular a metal oxide layer disposed between two electrodes. The electrical resistance of such devices can be modified by write and erase operations. These write and erase operations make it possible to pass the resistive memory device OxRAM from a low resistance state LRS (acronym for "Low Resistive State") to a high resistance state HRS (acronym for "High Resistive State"). Resistive State "), and vice versa.
    During programming steps, that is to say when a sufficient voltage and current are applied to the device, with a current limitation crossing the device, lower, for example, to a few milliamperes (mA), filaments Conductors can selectively be created (LRS status) and broken (HRS status) between the electrodes through the oxide layer.
    From cycle to cycle, the resistances of the low resistance states LRS and high resistance HRS tend to evolve. A variability of these resistances LRS and HRS is thus observed during the life of these memory cells.
    This variability is also observed from cell to cell.
    This variability is particularly important for the state of high resistance HRS, inducing a decrease in the programming window, or even a total loss of the programming window. This problem of variability is today a real obstacle to industrialization.
    This concern remains despite many efforts made in the field of resistive memory production methods and programming methods.
    In addition, numerous studies have been carried out in order to reduce the variability of electrical performance by reducing the contact area between one of the electrodes and the oxide layer.
    In particular, it has been shown in the publication: "Conductive Filament Control in Highly Scalable Unipolar Resistive Switching Devices for Low-Power and High-density Next Generation Memory", Kyung-Chang Ryoo et al., IEDM2013, that a solution for reducing the dimensions of the device is to reduce the contact area between one of the electrodes and the oxide layer. This solution involves complex and expensive implementation methods.
    Document US8470681 proposes to add a disturbance element in the oxide layer and on the lower electrode, so as to promote the formation of a conductive filament at the zone where said perturbation element is located. Adding this element generates a larger constraint field in the device. In this same document, another embodiment consists in producing a cone or pyramid shape in the lower electrode before proceeding with the deposition of the oxide layer.
    These solutions have the disadvantage of adding many steps of realization of the device. Moreover, these steps are complex and it is not easy to achieve good reproducibility.
    Moreover, the reduction of the surface of the upper electrode makes complex contact recovery at this electrode.
    Document FR2998708 proposes to minimize the dimensions of the memory point formed by the material within which the conductive filament is created between the two electrodes of the CBRAM memory cell. The invention essentially relates to ion-conduction memories (CBRAM or Conductive Bridging RAM memories), but can be extended to other types of memories and requires several levels of lithography.One of the technological sequences proposed is as follows: of a metallic line, production of an inert lower electrode, for example, by a damascene method, production of a confinement electrode comprising a soluble material, deposition of a dielectric, production of an additional via lithography, realization of spacers (deposition, etching), filling with a material, chemical-mechanical polishing, then new deposition of a dielectric layer, production of a via lithography, realization of spacers and filling with a material. to create a peak effect on the upper electrode, but to keep a sufficient volume of electrolyte (applicatio US 8,377,789 aims to achieve the same objective by seeking a peak effect on the transition metal oxide.
    Disadvantages appear in this type of device. First of all, problems can occur during via fills, especially in view of minimizing dimensions. Furthermore, the method of making such devices is difficult to implement in terms of technological achievement and reproducibility.
    Thus, in all the known solutions, in order to form a reduced contact surface between at least one of the electrodes and the oxide layer, it is necessary to resort to multiple and therefore expensive steps. In particular, the steps of lithography, deposition, planarization, necessary to obtain nanoscale dimensions at the contact between the electrodes and the dielectric material of the oxide layer are complex and require heavy development steps and not always perfectly reproducible. In addition, a contact recovery performed on a small area inevitably leads to additional constraints in terms of industrialization.
    The present invention aims to solve all or at least some of the disadvantages of current techniques. In particular, it would be advantageous to propose a solution for reducing or even eliminating the variability of the H RS and / or LRS resistances observed cycle after cycle for resistive memory devices, while limiting or avoiding the disadvantages of the known production methods of the invention. prior art mentioned above.
    SUMMARY OF THE INVENTION
    The present invention relates to a method for producing a resistive memory cell from a stack of layers comprising at least a first electrode and a dielectric layer surmounting the first electrode.
    The method comprises a step of forming a second electrode comprising at least one step of depositing the second electrode on the dielectric layer, a step of defining the contour of said second electrode, so that the second electrode forms an element. protruding above the dielectric layer having curved or inclined flanks with respect to the perpendicular to a plane in which the dielectric layer extends predominantly.
    The method of the present invention enables a memory cell to be made using simple lithography and etching steps of the second electrode. Instead of minimizing as much as possible the dimensions of the dielectric layer within which the conductive filament is formed or alternately to pass alternately from the LRS and HRS states, the invention provides for conventional lithography steps (advantageously a lithography in deep ultraviolet), less expensive to reduce the dimensions of one of the two electrodes. The constraints on the dimensions are thus relaxed. The etching step advantageously makes it possible to minimize the size of the "active" zone of a resistive memory of the Ox-RAM type. Moreover, the surface S2 does not need to be very small, which favors the resumption of contact at the level of the second electrode.
    The present invention thus proposes a simple, reliable and reproducible method, making it possible to release the stresses at the level of the contact recovery at the top of the memory point (no expensive lithography step), while minimizing the effective zone of filament formation. driver.
    The present invention also relates to a memory cell or memory device comprising a stack of layers comprising a first electrode, a second electrode and a dielectric layer positioned between the first electrode. The second electrode forms a protruding element above the dielectric layer. This protruding element has flanks inclined with respect to the perpendicular to a plane in which the dielectric layer extends or curves so that the projecting element defines a first surface S1 facing the dielectric layer and a second surface S2, opposite to the first, the first surface S1 being smaller than the second surface S2.
    The present invention also relates to a memory cell comprising a stack of layers comprising a first electrode and a dielectric layer. A second electrode, positioned on the dielectric layer, is configured to form a protruding element above the dielectric layer having inclined flanks, the angle a between the flanks of the second electrode forming an acute angle with the plane in which the dielectric layer extends mainly.
    Particularly advantageously, the flanks of the projecting element forming the second electrode are curved or inclined. To do this, a standard etching is carried out comprising an over-etching of the second electrode so as to form a protruding element whose profile is substantially concave or trapezoidal recess. This approach forming inclined flanks is not standard. Indeed, in microelectronic devices, it is generally sought to obtain profiles as straight as possible or with a slope "out" (so that the deposits made thereafter are consistent).
    Advantageously, in order to reduce the instability observed cycle after cycle in the memory cell, the present invention makes it possible to reduce the contact area between the at least one of the first and second electrodes and the dielectric layer. The more the contact surface between one of the electrodes and the dielectric layer is reduced, the more the conductive filament will be guided in its growth, and the more the electrical characteristics will be reproducible.
    When the contact area between the at least one electrode of the first electrode and the second electrode and the dielectric layer is large, the number of conductive filament interfering paths that can be created during programming steps is high. can generate significant variability in cycle-to-cycle and / or cell-to-cell performance.
    The present invention does not require adjustment of the thickness of the dielectric layer. Advantageously, the dielectric layer will be "intact" and not modified by the etching chemistry used in subsequent steps of the process. Thus, the present invention presents an alternative solution that does not require a modification of the fabrication of the memory cell following an adjustment of the dielectric layer.
    The method according to the present invention makes it possible to reduce the "active" area of the memory point, advantageously by a factor of 1000 (for example, from 100 nanometers to 10 nanometers in lateral dimensions), while enabling the memory point to be made using releasing lithography techniques (for example a deep UV deep lithography), and not posing any specific problem during the resumption of contact on the upper via. In the same way, standard optical lithography techniques can be used, with alignments (in English "overlay"), on the memory point, not critical. The method is, moreover, easy to implement, not requiring expensive and difficult lithography levels.
    Another object of the present invention relates to a microelectronic device comprising a plurality of memory cells according to the invention. By microelectronic device is meant any type of device made with microelectronics means. These devices include, in addition, devices for purely electronic purposes, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.).
    BRIEF INTRODUCTION OF THE FIGURES Other characteristics, objects and advantages of the present invention will appear on reading the detailed description which follows, with reference to the appended drawings, given by way of nonlimiting examples, and in which FIGS. 5 each illustrate a step of an exemplary embodiment of the present invention: FIG. 1 illustrates a sectional view of a deposition step of a stack of layers forming a memory cell, comprising a dielectric layer arranged between two electrodes. FIGURE 2 illustrates a sectional view of a lithography step for forming a projecting element. FIG. 3 illustrates a sectional view of the projecting element forming one of the electrodes. - FIGURE 4 illustrates a sectional view of a step of depositing a dielectric layer covering the protruding element. FIGURE 5 illustrates a sectional view of a step of forming a contact recovery on the electrode formed by the protruding element.
    The drawings are given by way of examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications. In particular, the relative thicknesses of the different layers and substrates may not be representative of reality.
    DETAILED DESCRIPTION
    Before beginning a detailed review of embodiments of the invention, are set forth below optional features that may optionally be used in any combination or alternatively: the step of defining the contour of the second electrode is carried out of so that the projecting element defines a first surface S1 facing the dielectric layer and a second surface S2, opposite to the first, the first surface S1 being smaller than the second surface S2; said surfaces S1, S2 extending substantially parallel to the plane in which the dielectric layer extends substantially. Thus, S1, S2 extend perpendicular to the thickness of the dielectric layer. This step comprises at least one engraving. - The definition step comprises an etching performed to define the inclined sides and the surfaces S1 and S2. The definition step comprises etching in a thickness dimension of the second electrode. In other words, the definition step comprises an anisotropic etching. - The engraving is at least partly isotropic. The etching comprises a chemical phase, preferably chosen from dry etching. - At least the etching time is modified to adjust the inclination of the flanks of the second electrode, formed by the etching of said second electrode. Preferably, the inclined flanks of the second electrode form an acute angle α with the plane in which the dielectric layer extends mainly. - The definition step comprises an etching performed to define the flanks of the second electrode forming the angle with the plane in which mainly extends the dielectric layer. - The angle a is between 10 ° and 80 °. The angle α is constant or not on the height of the flanks. - The ratio between the first surface S1 and the second surface S2 of the second electrode is less than 0.8. It is preferably between 0.01 and 0.25 (0.01 corresponding to 11 = 0.1 * 12, ie a reduction of 90% of 12 and 0.25 corresponding to 12 = 0.5 * 11, ie a reduction of I2 50%). - The projecting element has a width 11 at its face in contact with the dielectric layer and has a width I2 at its opposite side to that in contact with the dielectric layer, and wherein the 11 is less than I2 . In other words, the projecting element comprises a first dimension of width 11 of the first surface S1 less than a second dimension of width I2 of the second surface S2. Advantageously, the ratio 11/12 between the first dimension of width 11 and the second dimension of width I 2 is less than 0.9 and is preferably between 0.1 and 0.5. - The projecting element has a length L1 at its face in contact with the dielectric layer and has a width L2 at its face opposite to that in contact with the dielectric layer, and wherein the L1 is less than L2 . Advantageously, the ratios mentioned above concerning 11 and I2 are equal to the ratios concerning L1 and L2. The step of defining the contour of said second electrode comprises an at least partial etching in the thickness of the dielectric layer. This etching step can help to minimize a little more 11; thus, on an HfO 2 / Second electrode (Ti 10 nm + TiN 50 nm) stack, the etch chemistries used to etch the HfO 2 layer are nonselective with respect to Ti and TiN. By etching the Hf02 layer partially or not, the second electrode will continue to be etched. - The deposition of the second electrode is performed in full plate. The step of defining the contour of the second electrode comprises a lithography to define the pattern of the second electrode, preferably a deep ultraviolet lithography. After the step of forming the second electrode, a dielectric layer is deposited at least on the sidewalls and the second surface of the protruding element forming the second electrode and on the dielectric layer, the deposition of the dielectric layer being preferably a compliant deposit. - Preferably, the dielectric layer is an oxide layer. Alternatively it can be formed by another layer. - After the formation of the dielectric layer, a planarization step of said dielectric layer performed by a chemical mechanical polishing. The planarization is carried out by mechanical-chemical polishing, the etching makes it possible to lower the height of the layer 500. Preferably, the planarization step is followed by an etching step to "lower" the level of the oxide. However, it is also possible to use only a chemical mechanical polishing step (having in this case the primary purpose of planarizing the surface but also to lower the dielectric height). Preferably, in said dielectric layer, a passage is formed for accessing the second electrode (via). - At least in part, the passage is filled with a conductive material so as to form a contact recovery for the second electrode. Alternatively, it is also possible to lower the level of the dielectric to the memory point, then to deposit a conductive material, and to burn it to delimit the contact recovery area. - A dielectric layer is positioned at least on the sidewalls and the second surface of the protruding element forming the second electrode and the dielectric layer. - Preferably, in said dielectric layer is formed a passage to access the second electrode. - The passage is at least partly filled with a conductive material so as to form a contact recovery for the second electrode. - The contour of the protruding element forming the second electrode is trapezoid whose side facing the dielectric layer is smaller than the opposite side to the dielectric layer. This contour forms a reentrant trapezoid. the contour of the protruding element forming the second electrode forms a concave profile. the contour of the protruding element forming the second electrode has: two faces substantially parallel to each other and parallel to the dielectric layer; flanks, preferably two pairs of flanks, joining said two substantially parallel faces, the flanks being curved; , preferably towards the inside of the projection. Thus flanks are not necessarily straight, they can be curved. Preferably the values of the angles a and β mentioned above are found for the two pairs of flanks.
    It is specified that in the context of the present invention, the term "on" does not necessarily mean "in contact with". Thus, for example, the deposition of a layer on another layer does not necessarily mean that the two layers are directly in contact with each other but that means that one of the layers at least partially covers the other being either directly in contact with it, or being separated from it by a film, another layer or another element. The expression the zone of the element A is located "at right" or "at the gaze" of the element B signifies that the zone of the element A and the element B are superimposed, in direct contact or not, following a direction perpendicular to the main plane in which the dielectric layer extends.
    The memory cell according to the present invention comprises elements of micron and / or nanometric dimensions. The following description has the preferred purpose of presenting a memory cell and its method of production with reference to FIGS. 1 to 5.
    Figure 1 illustrates a memory cell comprising a dielectric layer 300 disposed between a first electrode 100 and a second electrode 200. Preferably, the dielectric layer is an oxide layer. Alternatively it can be formed by another layer. Preferably, the first electrode 100 is first formed, then the dielectric layer 300 is deposited on the first electrode 100, and finally the second electrode 200 is formed on the dielectric layer 300. According to a particularly advantageous embodiment, at least one layer but preferably all the layers forming the first electrode 100, the second electrode 200 and the dielectric layer 300 are deposited in full plate, ie over the entire surface. Preferably, the deposits are compliant.
    Preferably, the first electrode 100 may be formed of a material, for example, selected from platinum (Pt), titanium nitride (TiN), or tantalum nitride (TaN). According to a nonlimiting exemplary embodiment of the invention, the first electrode 100 may be formed of a stack of layers comprising, for example, successively, a titanium (Ti) layer with a thickness of 10 nanometers (nm) ), a copper-aluminum alloy (AlCu) layer with a thickness of about 440 nm, a titanium (Ti) layer with a thickness of 10 nm and a layer of titanium nitride (TiN) with a thickness of 40 nm.
    Preferably, the second electrode 200 may be formed of a material based on titanium (Ti), tantalum (Ta), hafnium (Hf), zirconium (Zr), for example. According to an exemplary embodiment, the second electrode 200 is formed of a stack of layers comprising, for example, a titanium layer 201 and a titanium nitride layer 202.
    The dielectric layer 300 is, for its part, preferably chosen from a metal oxide, for example based on hafnium oxide (HfO 2), titanium oxide (TiO 2), tantalum oxide (Ta 2 O 5), nickel oxide (NiO), zinc oxide (ZnO) or bilayer (for example of Al2O3 / HfO2 type).
    Fig. 2 illustrates a lithography step such that the second electrode 200 forms a projecting element 250 above the dielectric layer 300. The lithography step is for defining patterns in the second electrode 200.
    According to a preferred but non-limiting embodiment of the invention, the pattern will be formed by an ultra-violet (UV) optical or extreme photolithography technique or by nano-printing or by electron beam ("ebeam"). .
    According to a preferred embodiment, a deep ultraviolet type lithography (English "deep UV", acronym DUV) is used. This method has the advantage of being less expensive, more industrializable, more commonly used, and also faster.
    The lithography comprises for example three main stages: spreading (or coating) of a resin layer 400 on the second electrode 200, exposure of the resin film 400 and development. Resin 400 may be positive or negative tone.
    According to another embodiment, a lithography is carried out, for example, by electron beam or electronic lithography, intended to define patterns in the second electrode 200; said patterns may have a surface of about one square micrometer, and preferably of the order of one hundred square nanometers. For dimensions greater than 100 nm, it is not at all interesting to use electron beam lithography (too long, too expensive, etc.), electron beam lithography is used to push the limits of the Optical lithography and draw patterns with a resolution up to dimensions of the order of deca-nanometers. In order to make the patterns of small surface dimension, a resin layer 400, preferably "negative", is used during the electronic lithography.
    FIG. 3 illustrates the step of defining the contour of the second electrode 200 so as to form a projecting element 250.
    After the lithography step, an etching step of the second electrode 200 is carried out in its thickness, the aim being to reveal a projecting element 250 forming the second electrode 200, by transfer of the previously formed pattern into the resin layer 400 .
    The previously formed resin layer 400 will make it possible to protect the zone of the second electrode 200 which will not have to be engraved or which will have to be etched to a lesser extent (that is to say the top of the pattern).
    The etching of the second electrode 200 is at least partially isotropic. The etching is, for example, performed by plasma etching. It is broken down into several stages: in a first step, the etching is "standard": it preferably comprises a "breakthrough" step in English, intended to etch the surface oxide layer formed on the surface of the material 200, then it is mainly anisotropic (in order to be able to efficiently transfer the resin pattern into the layer to be etched 200), and lastly finally more "chemical" to be able to ensure good etch selectivity with respect to a barrier layer (here the dielectric layer 300 ). This last step is classically called "overgrading" or "over-etch" in English. Usually, it is used to remove the residue of material after etching, but it is minimized so as not to obtain "reentrant" profiles. In this case, the "over-etch" step is deliberately prolonged to laterally attack the layer defining the second electrode 200. The second electrode 200, for example made of TiN / Ti, can be etched with an IC 2 / Ar chemistry. or in CI2 / 02. The "over-etch" time chosen is between 10% and 90% of the time required for the anisotropic etching (usually called "hand-etch" in English).
    The remaining resin layer 400 is then removed. The projecting element 250 obtained by etching the layer 200 preferably has a recessed trapezoidal shape or a concave profile. The projecting element comprises a first surface S1 251 opposite or in contact with the dielectric layer 300 and a second surface S2 252, opposite to the first S1 251. Advantageously, the first surface S1 251 is smaller than the second surface S2 252 The surfaces S1, S2 251, 252 extend perpendicular to the thickness of the dielectric layer 300.
    Preferably, the ratio S1 / S2 between the first surface S1 251 and the second surface S1 252 of the projecting element 250 of the second electrode 200 is less than 0.8 and is between 0.01 and 0.25. The projecting element 250 comprises a first dimension of width 11 of the first surface S1 251 smaller than a second dimension of width I2 of the second surface S2 252. The ratio between the first dimension of width 11 and the second dimension of width I2 is between 0.1 and 0.9, and preferably between 0.1 and 0.5.
    Particularly advantageously, the flanks 255 of the projecting element 250 of the second electrode 200 are curved or inclined. The angle α between the flanks 255 of the second electrode 200 forms an acute angle with the plane in which the dielectric layer 300 extends. The flank 255 has an outward facing surface of the projecting element 250 and an inner face, the latter defining the space occupied by the projecting element 250.
    Due to the inclination of the sidewall 255, the outer face of the sidewall 255 is turned facing the upper face of the dielectric layer 300. The angle a is formed between the outer face of the sidewall and the upper face of the dielectric layer 300. An angle β is formed between the inner face of the sidewall and the upper face of the dielectric layer 300. The angles a and β advantageously form additional angles (the sum of their measurement being 180 degrees). The angle a is preferably between 10 ° and 80 °. The angle a is constant or may instead vary on the height of the sidewall.
    To create a concave profile of the projecting element 250 and in particular to promote the formation of inclined sidewalls 255, a standard engraving with a specific overetching is preferably required. To do this, a standard etching is carried out comprising a supergrafting of the second electrode so as to form a projecting element whose profile is substantially concave or trapezoidal recess. This approach forming inclined flanks is not standard.
    Indeed, in the known methods for producing microelectronic devices, it is generally sought to obtain profiles as straight as possible or with an "outgoing" slope (so that the deposits made thereafter are consistent). To obtain a vertical profile, over-etching is usually minimized and only serves to remove the residue of material after etching. Over-etching is essentially chemical and gives strongly isotropic profiles in case of strongly prolonged etching time.
    In the context of the present invention, advantageously modifies at least the over-etching time to adjust the inclination of the sidewalls 255 (ie the angle α) of the projecting element 250, formed by the etching of the second electrode 200. More exactly, the ratio between the etching time of the over-etch and the time of the anisotropic etching (also called "etch etching" in English) is varied. This amounts to playing on the ratio between the ion bombardment and the dissociation of the ions in the plasma, or on the ratio: power of the coils / power of the electrodes.
    The over-etch time chosen is between 10% and 90% of the time required for the anisotropic etching (usually called "hand-etch"). According to one embodiment, the step of defining the contour of said second electrode 200 comprises an at least partial etching in the thickness of the dielectric layer 300. This etching step can contribute to minimizing a little more 11; thus, on an Hf02 / Second Electrode (Ti 10 nm + TiN 50 nm) stack, the etch chemistries used to etch the HfO 2 layer are non-selective with respect to Ti and TiN. By etching the Hf02 layer partially or not, the second electrode 200 will continue to be etched.
    Advantageously, the projecting element 250 has, in addition to the pair of sides 255, another pair of flanks 253 extending from the faces of the projecting element 250 which are parallel to the layer 300. Advantageously these flanks 253 have the same inclination or curvature as the flanks 255. The inclination or curvature of the flanks 253 is formed during the same steps as the inclination or the curvature of the flanks 255.
    As illustrated in FIG. 3B, the length L1 of the first surface S1 251 of the projecting element 250 is smaller than the length L2 of the second surface S2 252. The ratios relating to the lengths L1 and L2 are preferably equal to the ratios mentioned in FIG. the present description concerning widths 11 and 12.
    FIG. 4 illustrates a step of forming a dielectric layer 500, after the step of forming the projecting element 250 forming the second electrode 200. The dielectric layer 500 is made so as to cover, preferably, the entire memory cell and at least the projecting element 250 and the dielectric layer 300.
    Preferably, the dielectric layer 500 comprises an insulating material, for example selected from silicon oxide (SiO 2), silicon nitride (SiN), silicon carbide (SiC). According to one embodiment, the dielectric layer 500 comprises a single layer, for example based on silicon oxide. According to another embodiment illustrated in FIG. 4, but not limiting of the invention, the dielectric layer 500 is formed of a bilayer of which a first layer 501, for example silicon nitride with a thickness of 30 nanometers and a second layer 502, for example, silicon oxide with a thickness of 300 nanometers. The deposition of SiN is done for example using a plasma enhanced chemical vapor deposition technique (PECVD acronym for "Plasma Enhanced Chimical Vapor Deposition"). Preferably the deposition of the first layer 501 is a conformal deposit. The second layer 502, in turn, forms an encapsulation layer which encapsulates the second electrode 200 and the first layer 501. The thickness of the dielectric layer 500 is between 50 nm and 500 nm, preferably of the order of 300 nm. This thickness depends on the maximum height of the projecting element 250, in other words the thickness of the second electrode 200, initially deposited.
    Advantageously, the possibility of a deposition of the dielectric layer 500 is feasible, even on reductions of large dimensions (up to 10 nanometers at the foot of the projecting element 250.
    FIG. 5 illustrates a step of making a contact recovery 600 from the projecting element 250 forming the second electrode 200. To perform such a contact recovery 600, optionally a planarization step of the dielectric layer is carried out 500 in order to flatten the surface of said dielectric layer 500. According to one embodiment, the planarization is performed by a chemical mechanical polishing. This initial planarization can be continued by mechanical-chemical polishing or, preferably, by etching, preferably but not exclusively, by the dry route. Preferably, this sequence of steps is performed so as to leave a thickness for the remaining dielectric layer 500 greater than the thickness of the second electrode 200 initially deposited (the height of the projecting element 250). This thickness is taken with respect to the reference of the oxide layer 300.
    A passage 650 (commonly called via) is then formed in said dielectric layer 500 so as to form an access to the projecting element 250, forming the second electrode 200. To this end, a standard lithography step is carried out so as to forming a pattern in the dielectric layer 500. There follows a step of etching said dielectric layer 500 so as to form the access to the second electrode 200. Advantageously, the dielectric layer 300 remains protected by the remaining dielectric layer 500 and is not modified (in terms of composition, potential oxidation) by technological steps (engraving, stripping, polishing, etc.) and thus retains its integrity.
    Once the passage 650 formed in the dielectric layer 500 giving direct access to the second electrode 200, via the projecting element 250, a step is performed to fill said passage 650 with a conductive material so as to form a contact resumption 600 on the memory point. According to one embodiment, the conductive material forming the resumption of contact 600 for the second electrode 200 comprises a material based on titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), tungsten (W) for example. This filling material may consist of one or more layers.
    Alternatively, it is also possible to lower the level of the dielectric layer 500 to the memory point, then to deposit a conductive material (material nature previously specified) and to burn it to delimit the contact recovery zone.
    Advantageously, for this type of memory cell, the contact resumption 600 on the second electrode 200 and also on the first electrode is facilitated since the electrodes 100, 200 retain large areas.
    The memory cell illustrated in FIG. 5 comprises a first zone 301 where the first and second electrodes 100, 200 are separated by a distance d1, corresponding to the thickness of the dielectric layer 300 initially deposited on the first electrode 100. The memory cell comprises a second zone 302 where the first and second electrodes 100, 200 are separated by a distance d2 corresponding to the thickness of the dielectric layer 300 initially deposited on the first electrode 100 to which is added the thickness of the dielectric layer 500, preferably electrically insulating. The distance d1, as the distance d2 described below, are measured in a direction perpendicular to the main plane in which the dielectric layer 300 extends. In the figures, this direction is vertical. The distance d1 corresponds to the shortest distance separating the first and second electrodes 100, 200 in the first zone 301. The distance d2 corresponds to the shortest distance separating the first and second electrodes 100, 200 in the second zone 302.
    Due to this delimitation of a first zone 301 and a second zone 302 in the dielectric layer 300, delimitation advantageously made possible by the formation of the projecting element 250, it is possible to confine the conductive filaments in a specific zone (ie the first zone 301) of said dielectric layer 300 which potentially reduces the dispersion of the conductive filaments. The invention thus makes it possible to reduce the cycles-to-cycles variability of the resistances of the LRS and HRS states and the variability of the programming window, as well as the cell-to-cell variability. The performance of the memory cell is less degraded over time.
    In the same way, in the present invention, the surface of the second electrode 200 has been reduced so as to reduce the contact surface 251 between said second electrode 200 and the dielectric layer 300. Advantageously, by decreasing the contact surface between less an electrode 100, 200 and the dielectric layer 300, the number of stray paths is less. The conductive filaments, possibly formed, are confined following the reduction of the contact surface between the second electrode 200 and the dielectric layer 300. The reduction in the number of parasitic paths may advantageously make it possible to further reduce the instability over time of the devices. memory cells and thus reduce the variability of the performance of such devices, and also minimize the dispersion of electrical performance between the different memory cells, following the confinement of conductive filaments in a restricted area.
    A specific and non-limiting embodiment of the invention will now be described.
    According to this exemplary embodiment given as an indication, the dielectric layer is an oxide layer formed based on hafnium oxide (HfO 2) with a thickness of between 5 and 10 nm, the second electrode 200 is formed of a bi-layer comprising a first titanium-based layer 201 of a thickness of 10 nm and a second layer 202 based on titanium nitride with a thickness of 50 nm and the dielectric layer 500 is formed of a bi-layer layer comprising a first silicon-nitride-based layer 501 with a thickness of 30 nm and a second layer 502 based on silicon oxide with a thickness of 300 nm. In this embodiment, the height of the memory point, that is to say the height of the projecting element 250 (or initial thickness of the second electrode 200), is of the order of 60 nm. For this example of a memory cell device, the critical dimension (CD) at the top of the memory point (on the second surface S2 252 of the projecting element 250) is of the order of 100 nm, whereas the critical dimension ( CD) at the bottom of the memory point (ie on the first surface S1 251 of the projecting element 250) is between 10 nm and 100 nm.
    The present invention is not limited to the previously described embodiments but extends to any embodiment within the scope of the claims.
    权利要求:
    Claims (25)
    [1" id="c-fr-0001]
    1. A method of producing a resistive memory cell from a stack of layers comprising at least a first electrode (100) and a dielectric layer (300) surmounting the first electrode (100), characterized in that it comprises at least one step of forming a second electrode (200) comprising: - a step of depositing the second electrode (200) on the dielectric layer (300), - a step of defining the contour of the second electrode (200) , so that the second electrode (200) forms a projecting element (250) above the dielectric layer (300) and having flanks (255) inclined relative to the perpendicular to a plane in which s' extends mainly the dielectric layer (300) or curves so that the projecting element (250) defines a first surface S1 (251) opposite the dielectric layer (300) and a second surface S2 (252), opposite at the prem ière (251), the first surface S1 (251) being smaller than the second surface S2 (252); said surfaces S1, S2 (251, 252) extending substantially parallel to the plane in which the dielectric layer (300) extends primarily.
    [2" id="c-fr-0002]
    2. Method according to the preceding claim wherein the step of defining the contour of the second electrode (200) comprises at least one etching performed to define the flanks (255) of the second electrode (200), the etching being performed in a thickness dimension of the second electrode (200).
    [3" id="c-fr-0003]
    3. Method according to the preceding claim wherein the etching is at least partly isotropic.
    [4" id="c-fr-0004]
    4. Method according to any one of the two preceding claims wherein the etching comprises a chemical phase, preferably a dry etching.
    [5" id="c-fr-0005]
    5. Method according to any one of the two preceding claims wherein at least the etching time is modified to adjust the curvature or inclination of the flanks (255) of the second electrode (200) formed by the etching of said second electrode. electrode (200).
    [6" id="c-fr-0006]
    6. Method according to any one of the preceding claims wherein the ratio S1 / S2 between the first surface S1 (251) and the second surface S1 (252) of the second electrode (200) is less than 0.8 and is preferably between 0.01 and 0.25.
    [7" id="c-fr-0007]
    7. A method according to any preceding claim wherein the step of defining the contour of the second electrode (200) is performed so that the flanks form an acute angle with the plane in which extends mainly the dielectric layer (300).
    [8" id="c-fr-0008]
    8. Method according to the preceding claim wherein the acute angle is between 10 ° and 80 °.
    [9" id="c-fr-0009]
    9. Method according to any one of the two preceding claims wherein the projecting element (250) has a width 11 at its face in contact with the dielectric layer (300) and has a width I2 at its face. opposite to that in contact with the dielectric layer (300), and wherein the 11 is less than I2.
    [10" id="c-fr-0010]
    10. Method according to the preceding claim wherein the ratio 11/12 between the first dimension of width 11 and the second dimension of width I2 is less than 0.9 and is preferably between 0.1 and 0.5.
    [11" id="c-fr-0011]
    11. A method according to any one of the preceding claims wherein said step of depositing the second electrode (200) is performed in full plate.
    [12" id="c-fr-0012]
    The method of any of the preceding claims wherein the step of defining the contour of the second electrode (200) comprises at least one lithograph for defining the pattern of the second electrode (200), preferably ultraviolet lithography. deep.
    [13" id="c-fr-0013]
    13. A method according to any preceding claim wherein after said step of forming the second electrode (200) is deposited a dielectric layer (500) at least on the sidewalls (255) and the second surface S2 (252). ) of the protruding element (250) forming the second electrode (200) and the dielectric layer (300), the deposition of the dielectric layer (500) preferably being a compliant deposit.
    [14" id="c-fr-0014]
    14. Method according to the preceding claim comprising, after the formation of the dielectric layer (500), a step of planarization of said dielectric layer (500) performed by a chemical mechanical polishing.
    [15" id="c-fr-0015]
    15. Method according to any one of the two preceding claims, wherein a passage (650) is formed in said dielectric layer (500) to access the second electrode (200).
    [16" id="c-fr-0016]
    Memory cell comprising a stack of layers comprising a first electrode (100), a second electrode (200) and a dielectric layer (300) positioned between the first electrode (100) and the second electrode (200), characterized in that the second electrode (200) forms a projecting element (250) above the dielectric layer (300) having flanks (255) inclined with respect to the perpendicular to a plane in which the dielectric layer (300) extends predominantly ) or curves so that the projecting element (250) defines a first surface S1 (251) facing the dielectric layer (300) and a second surface S2 (252), opposite to the first (251), the first surface S1 (251) being smaller than the second surface S2 (252); said surfaces S1, S2 (251, 252) extending substantially parallel to the plane in which the dielectric layer (300) extends primarily.
    [17" id="c-fr-0017]
    17. Memory cell according to the preceding claim wherein the ratio S1 / S2 between the first surface S1 (251) and the second surface S1 (252) of the second electrode (200) is less than 0.8 and is preferably between 0.01 and 0.25.
    [18" id="c-fr-0018]
    18. A memory cell according to any one of the two preceding claims wherein the oblique or inclined sides form an acute angle with the plane in which the dielectric layer (300) extends mainly.
    [19" id="c-fr-0019]
    19. Memory cell according to the preceding claim wherein the angle a is between 10 ° and 80 °.
    [20" id="c-fr-0020]
    Memory cell according to any one of the four preceding claims, in which the projecting element (250) has a width 11 at its face in contact with the dielectric layer (300) and has a width I2 at its level. opposite side to that in contact with the dielectric layer (300), and wherein the 11 is less than I2.
    [21" id="c-fr-0021]
    21. Memory cell according to the preceding claim wherein the ratio 11/12 between the first dimension of width 11 and the second dimension of width I2 is less than 0.9 and is preferably between 0.1 and 0.5.
    [22" id="c-fr-0022]
    Memory cell according to any one of the six preceding claims, comprising a dielectric layer (500) positioned at least on the sidewalls (255) and the second surface S2 (252) of the projecting element (250) forming the second electrode (250) and on the dielectric layer (300).
    [23" id="c-fr-0023]
    23. A memory cell according to any one of the preceding claims wherein the contour of the protruding element forming the second electrode is trapezoid whose side facing the dielectric layer (300) is smaller than the side opposite the dielectric layer (300).
    [24" id="c-fr-0024]
    24. Memory cell according to any one of claims 16 to 22 wherein the contour of the protruding element forming the second electrode forms a concave profile.
    [25" id="c-fr-0025]
    25. A microelectronic device comprising a plurality of memory cells according to any one of claims 16 to 24.
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    同族专利:
    公开号 | 公开日
    FR3041808B1|2018-02-09|
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    法律状态:
    2016-09-29| PLFP| Fee payment|Year of fee payment: 2 |
    2017-03-31| PLSC| Publication of the preliminary search report|Effective date: 20170331 |
    2017-09-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-09-28| PLFP| Fee payment|Year of fee payment: 4 |
    2019-09-30| PLFP| Fee payment|Year of fee payment: 5 |
    2021-06-11| ST| Notification of lapse|Effective date: 20210506 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1559316|2015-09-30|
    FR1559316A|FR3041808B1|2015-09-30|2015-09-30|METHOD FOR MAKING A RESISTIVE MEMORY CELL|FR1559316A| FR3041808B1|2015-09-30|2015-09-30|METHOD FOR MAKING A RESISTIVE MEMORY CELL|
    US15/281,813| US10411072B2|2015-09-30|2016-09-30|Method for producing a resistive memory cell|
    EP16191723.2A| EP3151296B1|2015-09-30|2016-09-30|Method for manufacturing a resistive memory cell|
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