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    • 专利摘要:
    Semiconductor structure comprising at least: - a substrate (102), - a buffer layer (104), - a superlattice formed on the buffer layer (104), said superlattice comprising a pattern comprising two layers of different materials (106, 108), each layer (106, 108) comprising an AlxGayInwBzN type material with x + y + w + z = 1, the thickness of each layer (106, 108) being less than its critical thickness, the number with a pattern of at least 50, - a spacer layer (110) whose material has a first mesh parameter, - a layer of GaN material (112) whose mesh parameter is greater than the first mesh parameter of so that the layer of GaN material (112) is brought into compression by the interlayer (110).
    公开号:FR3041470A1
    申请号:FR1558766
    申请日:2015-09-17
    公开日:2017-03-24
    发明作者:Alexis Bavard；Matthew Charles
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    SEMICONDUCTOR STRUCTURE HAVING IMPROVED TENSION
    DESCRIPTION
    TECHNICAL FIELD AND STATE OF THE PRIOR ART
    The present invention relates to a semiconductor structure having improved voltage withstand.
    Among the various existing semiconductor materials, GaN or Gallium nitride makes it possible to produce electronic devices of good quality.
    In order to produce electronic devices comprising GaN at a reasonable cost, it is sought to produce structures comprising one or more layers of GaN on a silicon substrate.
    However, GaN and silicon do not have the same mesh parameters or thermal expansion coefficients close or equal. Thus, if no precaution is taken, the GaN obtained is not of good quality and, during cooling after the GaN deposition, cracks appear in the GaN layer or layers. In order to overcome this drawback, one or more buffer layers are interposed between the substrate and the GaN layer or layers, which impose compressive stresses in the GaN, which during cooling avoids the appearance of cracks in the layer. of GaN. In addition, the presence of the buffer layer or layers prevents the GaN from being in contact with silicon, which would otherwise cause the appearance of crystalline defects in GaN.
    The material of the buffer layer is for example ΓΑΙΝ.
    We also seek to achieve a GaN layer having sufficient thickness necessary for most applications.
    The document WO2013001014 describes a semiconductor structure comprising a thick GaN layer. This thick layer of GaN is obtained by producing, on an AlN buffer layer formed on a monocrystalline silicon substrate, a GaN 3D layer which aims to improve the quality of the GaN layers.
    A thick layer of good quality GaN can then be produced on this layer of 3D GaN after the insertion of an interlayer.
    One of the applications of semiconductor structures comprising a GaN layer is power electronics, in particular the production of high power transistors. In this application, it is sought to obtain a vertical leakage current, i.e. in the height of the stack of layers, very low.
    However, the GaN 3D layer does not provide sufficient vertical electrical insulation.
    SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor structure comprising a layer of GaN, more generally of type III-N material, with good resistance to voltage so as to be adapted for example to the realization of high power transistor while having a thick enough GaN layer, more generally of type III-N material, and of sufficient quality.
    The above-mentioned object is achieved by a semiconductor structure comprising a substrate, a buffer layer, at least one superlattice formed on the buffer layer, an interlayer, a layer of GaN placed in compression by the intermediate layer, the superlattice having a pattern comprising n layers of different materials, not being an integer greater than or equal to 2, the pattern being repeated a large number of times. Each layer of the pattern comprises a material of the AlxGaylnwBzN type with x + y + w + z = leta a thickness less than the critical thickness of the material of which it is formed. Preferably, the pattern is repeated at least 50 times.
    Very advantageously, the thickness of each layer is between 0.5 nm and 5 nm and preferably less than or equal to 1 nm. Preferably, the thickness of the pattern is less than or equal to 5 nm.
    In the present application, a superlattice is a periodic multilayer structure formed by the repetition of an elementary pattern comprising at least two chemically different successive layers.
    According to the invention, the super-network does not have the main objective of ensuring the compression of the III-N which is formed on the superlattice but to ensure the vertical electrical insulation, in particular because of a large number of interfaces between the layers of the super-network. The application of the compressive stress is provided by the so-called intermediate layer. The invention thus makes it possible to decorrelate the electrical desolation and compressive stress functions on the thick active layer of III-N, which makes it possible to optimize the electrical insulation and the compression set in a substantially independent manner.
    This decorrelation also offers a certain freedom on the composition of the network layers, which makes it possible to have aluminum-rich layers having higher energy bandwidths than that of GaN.
    In addition, the superlattice can reduce the density of dislocations, which further facilitates the formation of thick GaN on the interlayer. In addition, due to the thin thicknesses involved, there is no appearance of two-dimensional electron gas between the superlattice and the interlayer AIN, unlike a stack of GaN and AlN.
    Advantageously, at least one additional layer is provided between the intermediate layer and the III-N layer, the material of which has a mesh parameter between that of the interlayer material and the III-N layer, so that progressively increases the mesh parameter of the interlayer to the lll-N layer.
    The subject of the present invention is then a semiconductor structure comprising at least: a substrate, a buffer layer, a superlattice formed on the buffer layer, said superlattice comprising a pattern comprising n layers made of different materials. , not being at least 2, each layer comprising a material of AlxGaylnwBzN type with x + y + w + z = 1, the thickness of each layer being less than its critical thickness, the number of patterns being at least equal at 50, an interlayer whose material has a first mesh parameter, a layer of type III-N material, whose mesh parameter is greater than the first mesh parameter, so that the layer of type III material -N is put in compression by the interlayer.
    Preferably, the thickness of each layer of the superlattice is less than or equal to 5 nm, more preferably equal to 1 nm. The thickness of each pattern is advantageously less than or equal to 5 nm.
    The structure may comprise at least one layer of AlxGaylnwBzN type material with x + y + w + z = 1 between the interlayer and the type III-N material layer having a second mesh parameter greater than the first mesh parameter and less than the mesh parameter of the type III-N material
    The intermediate layer preferably has a thickness of at least 10 nm and can be an AlN layer. In a variant, the intermediate layer is a superlattice.
    The substrate may advantageously comprise monocrystalline silicon.
    According to another example, the structure comprises at least one additional layer of type III-N material interposed between the superlattice and the interlayer and / or at least one additional layer of type III-N material interposed between the interlayer and the layer of III-N material. This additional layer preferably has a thickness of at least 50 nm.
    The structure may comprise several superposed super-networks.
    Preferably, the type III-N material is gallium nitride.
    The present invention also relates to a transistor comprising at least one structure according to the invention, the latter being for example a HEMT transistor.
    The present invention also relates to a method for producing a semiconductor structure comprising the steps from a substrate: a) formation of a buffer layer, b) formation of a superlattice comprising the sub-structures. steps: b1) producing a pattern comprising n layers, not being at least 2, each layer comprising a material of AlxGaylnwBzN type with x + y + w + z = 1, the thickness of each layer being less than its critical thickness, b2) repetition of step b1) at least 50 times, c) formation of an interlayer having a first mesh parameter d) formation of a layer of lll-n material whose parameter of mesh is greater than the first mesh parameter.
    During step b), carbon is advantageously incorporated into the layers of the superlattice.
    Preferably, the layers of the structure are formed by growth, advantageously by organometallic vapor phase epitaxy.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on the basis of the following description and the appended drawings in which: FIG. 1 is a schematic representation of an example of a semiconductor structure according to the invention, FIG. 2 is a diagrammatic representation of another example of a semiconductor structure according to the invention; FIG. 3 is a schematic representation of another example of a semiconductor structure according to the invention, FIG. 4 is a diagrammatic representation of another example of a semiconductor structure according to the invention; FIG. 5 is a graphical representation of the variation of the vertical leakage current as a function of the voltage applied in a semiconductor structure; according to a particular embodiment of the invention and in a structure comprising duGaN 3D, - Figure 6 schematically shows a power transistor formed on a semiconductor structure according to a mode Particular embodiment of the invention, Figure 7 schematically shows a light emitting diode formed on a semiconductor structure according to a particular embodiment of the invention.
    The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    The following description will relate to semiconductor structures comprising a thick layer of GaN to which compressive stresses are applied. However, the present invention relates more generally to any semiconductor structure comprising a layer of III-N type material, that is to say of nitride of a material of column III of the periodic table such as boron, indium, etc. As a result, in the following description, when it is desired to produce a structure comprising a type III-N layer instead of GaN, it is sufficient to replace in the different layers of the structure the Gallium by the material of type III.
    In FIG. 1, an example of a semiconductor structure 100 according to the invention comprising a stack of several layers. The stack comprises a substrate 102 forming the base of the stack. The substrate 102 is for example monocrystalline silicon, for example of the (111) type. The thickness of the substrate is for example between 500 μιτι and 2 mm. Alternatively, the substrate 102 could be made for example sapphire, which avoids the conduction layers at the interface between GaN and sapphire. The stack also includes a buffer layer 104 formed on the substrate 102. This buffer layer 104 serves as a nucleation layer for the growth of the other layers. The buffer layer comprises, for example, AlN and has a thickness for example between 50 nm and 500 nm, and preferably between 200 nm and 300 nm. This buffer layer also acts to isolate the substrate from the GaN layer or layers that will be formed thereafter. Alternatively, the buffer layer may comprise SiC. The stack also comprises a SRI superlattice formed on the buffer layer 104.
    As indicated above, a superlattice is a periodic multilayer structure formed by the repetition, a large number of times, of an elementary pattern comprising at least two chemically different successive layers. The superlattice preferably comprises at least 50 elementary patterns.
    In the example of FIG. 1, the SRI superlattice according to the invention comprises a pattern comprising two layers, a layer AlxiGayilnwiBziN with xi + yi + wi + zi = let a layer 108 of Alx2Gay2lnW2Bz2N with X2 + y2 + W2 + Z2 = 1. The materials of two successive layers in the superlattice are different. For example, the values of x 1 and X 2 are different, y 1 and y 2 are different, w 1 and W 2 are different and z 1 and Z 2 are different.
    In addition, the layers 106 and 108 have thicknesses that are smaller than the critical thicknesses. Thus the layers 106 and 108 have very low dislocation densities. Critical thicknesses are at most 5 nm.
    For example, the thicknesses of the layers 106 and 108 are between 0.5 nm and 5 nm, and preferably less than or equal to 1 nm. Preferably, the thickness of the pattern, i.e. the sum of the thicknesses of layers 106 and 108 is less than or equal to 5 nm. The two layers may have equal or different thicknesses. The stack also comprises an intermediate layer 110 formed on the superlattice SRI capable of applying compressive stresses to a layer of GaN 112 formed on the intermediate layer 110.
    The intermediate layer 110 comprises a material having a mesh parameter lower than that of GaN in order to apply to GaN sufficient compressive stresses for producing a thick layer of GaN that does not contain cracks. The intermediate layer 110 has for example a thickness between 5 nm and 50 nm and preferably equal to 17 nm. For example, the interlayer 110 is in AlN.
    The GaN layer 112 has for example a thickness of 3 μm. By way of example, a superlattice comprising 340 repetitions of a pattern comprising a layer 106 of GaN and a layer 108 of Alo, 5Gao, 5N can be produced, each layer having a thickness of 1 nm.
    Due to the very large number of interfaces of the SRI superlattice the electrical resistance of the superlattice is very high. This therefore provides electrical insulation in the stack between the GaN layer 112 and the substrate 102.
    As indicated above, the superlattice does not have the function of compressing the GaN layer in compression but of ensuring electrical insulation between the GaN layer, more precisely the electronic component formed on the GaN layer and the substrate.
    This structure has a very good voltage strength, for example several hundred volts. Thus the current leaks in the stack are substantially reduced. The structure can then be used in high power electronics, for example to make HEMT transistors for High-electron-mobility transistor in English terminology or Schottky diodes.
    In addition, a GaN layer with high crystallographic quality, i.e., with few defects is obtained.
    In addition, thanks to the invention, the electrical insulation and the application of compression stress to the Gan layer are decorrelated, which gives greater freedom in the choice of the aluminum composition of the layers 106 and 108. It is then possible to have the elementary layer (s) rich in aluminum, which is favorable for obtaining a high electrical insulation, since the alloys AIGaN have a higher energy bandwidth than the GaN
    Furthermore, the invention advantageously makes it possible to incorporate carbon in a large quantity in the stack, which further increases the voltage withstand. For example, the carbon may be incorporated directly into the layers of the superlattice during the formation thereof in a manner known to those skilled in the art, for example during growth of the layers 106 and 108 by epitaxy in phase organometallic vapor or MOCVD (Metalorganic Chemical Vapor Deposition in English terminology). The incorporation of carbon in large quantities in the superlattice does not have the effect of deteriorating the crystalline quality unlike the structures of the state of the art. The carbon concentration is for example equal to approximately greater than 5.1018.
    In addition, it is possible to make several super-networks according to the invention, one above the other, the compositions of the layers of the patterns varying from one network to another. It may be envisaged to have super-array compositions that vary in a given sen between the super-network located closest to the substrate and that located closer to the GaN layer.
    The combination of several super-networks according to the invention makes it possible to increase the tensile strength of the structure.
    Alternatively, the spacer layer of AIN can be replaced by a superlattice capable of applying a compressive stress to the GaN layer that will be produced on the superlattice. For example, the compositions of the layers are chosen so that the average composition of the network is high in AlGaN, for example of the order of 80%. Other examples of semiconductor structures according to the invention will now be described.
    In FIG. 2, another example of a semiconductor structure 200 can be seen. The structure 200 comprises a substrate 202, for example made of Si type (111), a buffer layer 204, for example made of AlN, a similar SR2 super-network. the SRI superlattice of the structure 100, an interlayer 210 similar to the intermediate layer 110, a layer 214 whose material has a mesh parameter smaller than that of the GaN but greater than that of the material of the intermediate layer 210. inserting the layer 214 between the intermediate layer and the GaN layer, the mesh parameter difference between the interlayer 210 and the GaN is progressively reduced. The addition of the layer 214 has the effect of better preserving the compression in the layers, allowing the growth of a thicker GaN layer without cracking during cooling. For example, the layer 214 is a layer of AIGaN whose thickness is for example between 50 nm and 1000 nm, preferably equal to 200 nm.
    Alternatively, it may be possible to interpose more than one layer of AIGaN between the intermediate layer and the GaN layer 312, these layers then being arranged so that their mesh parameter is increasing of the layer in contact with the intermediate layer. 210 to the layer on which the GaN layer 212 is formed
    In addition, in the example shown, an AIGaN layer 215 is formed between the buffer layer 204 and the SR2 superlattice. The SR2 super-network plays the same role as AIGaN, that is, it helps to transmit the compression of ΓΑΙΝ to GaN. In addition, the SR2 super-network is more resistive than AIGaN, as is the case for the SRI super-network. The layer 215 has for example a thickness equal to 0.5 .mu.m.
    In the example shown, the structure also comprises a layer of GaN 216 formed on the GaN layer 212 forming a channel, a layer 218 of AIN, a layer of AIGaN 220 and a layer of GaN 222.
    Considering a superlattice comprising 340 repetitions of a pattern comprising a layer 106 of GaN and a layer 108 of Alo.sGao.sN, each layer having a thickness of 1 nm, the structure 200 has for example a thickness of 4, 8 pm.
    Alternatively, the layer 214 of AIGaN can be replaced by a superlattice which has the same function as the AIGaN layer 214.
    In FIG. 3, another example of a semiconductor structure 300 can be seen. The structure 300 comprises a substrate 302, for example made of Si type (111), a buffer layer 304, for example made of AlN, a similar SR3 super-network. at the superlattice SRI of the structure 100, a GaN layer 324 formed on the superlattice SR3, an interlayer layer 310 formed on the layer 324, the interlayer being similar to the interlayer 110, a layer 314 similar to the layer 214 .
    The GaN of the layer 324 is a layer of GaN said 2D or 2 dimensions that is to say that one does not generate roughness, there is no island "3D" and the surface remains flat. The formation of such a layer is well known to those skilled in the art. The realization of a stack of a 2D GaN layer and of an AlN layer has the advantage of revealing at the interface between GaN and AlN buried cracks which participate in the compression of the GaN layer 312.
    The GaN layer 324 has a thickness for example between 50 nm and 2000 nm, preferably equal to 500 nm.
    The pattern of the superlattice may comprise more than two layers, it may comprise n layers, n> 2, the composition of the layer n can then be written AlxnGai-xnN, xn belonging to the interval [0; 1],
    In FIG. 4, another example of a semiconductor structure 400 in which n = 4 can be seen. The structure 400 comprises a substrate 402, a buffer layer 404 and an SR4 superlattice. The pattern of the superlattice comprises four layers 406, 408, 426, 428. The layer 406 comprises the material AlxiGayilnwiBziN with xi + yi + wi + zi = 1. The layer 408 comprises the material Alx2Gay2lnW2Bz2N with X2 + y2 + W2 + Z2 = 1. The layer 426 comprises the material AIX3Gay3lnW3BZ3N with X3 + y3 + W3 + Z3 = 1. The layer 428 comprises the material AIX4Gay4lnW4BzN with X4 + y4 + W4 + Z4 = 1. The materials of two successive layers in the superlattice are different. Each layer has a thickness less than the critical thickness. The structure 400 also includes an intermediate layer 410 formed on the SR4 superlattice, the interlayer 410 being similar to the interlayer 110, a layer 414 similar to the layer 214.
    Preferably the pattern has a thickness less than 5 nm. The superlattice SR4 comprises a large number of patterns, preferably at least 50.
    FIG. 5 shows a graphical representation of the variation of the vertical leakage current I in A / mm 2 as a function of the voltage V in volts applied through the stack of a structure according to the invention (curve A) and a structure comprising GaN 3D in place of the superlattice (curve B). It can be seen that, thanks to the invention, the vertical leakage current is reduced.
    Regardless of the exemplary embodiment or the variant embodiment, the various layers of the semiconductor structure are produced by growth, for example by organometallic vapor phase epitaxy, in particular the layers of the superlattice (s), for example. chemical vapor deposition or MOCVD (Metalorganic
    Chemical Vapor Deposition in English terminology) or by molecular beam epitaxy or MBE (Molecular Beam Epitaxy in Anglo-Saxon terminology). By way of example, for the growth of the layers by MOCVD, the typical temperature is of the order of 1000 ° C., a pressure of 100 mbar, under hydrogen with a partial ammonia pressure of 30mbar.
    The GaN layer 112 obtained can be used as an active layer of semiconductor devices made from the substrate formed by the structure 200. For example, an HEMT transistor 300 can be made from the GaN layer 112, as shown diagrammatically in FIG. 6. This layer 112 is doped, for example with carbon and with a concentration for example equal to approximately 1019 cm 3. An additional layer 114 comprising a semiconductor similar to that of the layer 112 and finer that the layer 112 (thickness for example equal to about 100 nm, or between about 25 nm and 1 pm), and also comprising carbon as a dopant with a concentration for example equal to about 5.1016 cm 3, is formed on the layer 112. This additional layer 114 of GaN is intended to form the channel of the HEMT transistor 500. A spacer layer 116 comprising, for example, ΓΑΙΝ and a thickness of approximately 1 nm, is then placed on the additional layer 114 of GaN. Finally, a layer of AIGaN 118, comprising for example a gallium level equal to about 80% and making it possible to ensure the formation of a two-dimensional electron gas in the channel of the transistor 300, is formed on this spacer layer 116 The HEMT transistor 300 is then completed by conventional steps such as formation of the source 120 and drain 122 regions, metal contacts, gate 124, etc.
    It will be understood that the various embodiments and the different variants can be combined without departing from the scope of the present invention.
    The semiconductor structure according to the invention is particularly suitable for producing high power transistors because of the high voltage withstand, for example the production of HEMT. But it can also be implemented in the production of light emitting diode structure, the GaN layer 112 is used as the active layer of a light emitting diode 600 as represented for example in FIG. 7. In this case, the layer 112 may be doped n for example with silicon. A quantum well structure 126 comprising GaN barrier layers and InGaN emitting layers is then formed on the layer 112. A layer 128 of p-doped GaN, for example with magnesium may finally be carried out on the quantum well structure. 126.
    A current flowing between the layers 112 and 128 causes a wavelength corresponding to the forbidden gap of InGaN in the wells.
    权利要求:
    Claims (17)
    [1" id="c-fr-0001]
    A semiconductor structure comprising at least: - a substrate (102), - a buffer layer (104), - a superlattice formed on the buffer layer (104), said superlattice comprising a pattern comprising n layers different materials, not being at least 2, each layer (106, 108) having a material of AlxGaylnwBzN type with x + y + w + z = 1, the thickness of each layer (106, 108) being lower than at its critical thickness, the number of patterns being at least 50, - an interlayer (110) whose material has a first mesh parameter, - a layer of type III-N material (112), whose parameter The mesh size is greater than the first mesh parameter so that the layer of type III-N material (112) is compressed by the interlayer (110).
    [2" id="c-fr-0002]
    2. Semiconductor structure according to claim 1, wherein the thickness of each layer (106, 108) of the superlattice is less than or equal to 5 nm, advantageously equal to 1 nm.
    [3" id="c-fr-0003]
    3. Semiconductor structure according to claim 1 or 2, wherein the thickness of each pattern is less than or equal to 5 nm.
    [4" id="c-fr-0004]
    4. Semiconductor structure according to one of claims 1 to 3, comprising at least one layer of AlxGaylnwBzN type material with x + y + w + z = 1 between the interlayer and the layer of type III-N material having a second mesh parameter greater than the first mesh parameter and less than the mesh parameter of the lll-N material
    [5" id="c-fr-0005]
    5. Semiconductor structure according to one of claims 1 to 4, wherein the intermediate layer has a thickness of at least 10 nm.
    [6" id="c-fr-0006]
    6. semiconductor structure according to one of claims 1 to 5, wherein the intermediate layer is a layer of AlN.
    [7" id="c-fr-0007]
    7. Semiconductor structure according to one of claims 1 to 5, wherein the intermediate layer is a superlattice.
    [8" id="c-fr-0008]
    8. Semiconductor structure according to one of claims 1 to 7, wherein the substrate comprises monocrystalline silicon.
    [9" id="c-fr-0009]
    9. Semiconductor structure according to one of claims 1 to 8, comprising at least one additional layer of type III-N material interposed between the superlattice and the intermediate layer and / or at least one additional layer of plastic material. type III-N interposed between the interlayer and the layer of material III-N.
    [10" id="c-fr-0010]
    The semiconductor structure of claim 9, wherein the additional layer of III-N material is at least 50 nm thick.
    [11" id="c-fr-0011]
    11. Semiconductor structure according to one of claims 1 to 10, comprising several superposed superlattices.
    [12" id="c-fr-0012]
    12. Semiconductor structure according to one of claims 1 to 11, wherein the type III-N material is gallium nitride.
    [13" id="c-fr-0013]
    13. Transistor comprising at least one structure according to one of the preceding claims.
    [14" id="c-fr-0014]
    14. Transistor according to the preceding claim, said transistor being a HEMT transistor.
    [15" id="c-fr-0015]
    15. A method of producing a semiconductor structure comprising the steps from a substrate: a) formation of a buffer layer, b) formation of a super-network comprising the substeps: b. a pattern comprising n layers, not being at least 2, each layer comprising a material of AlxGaylnwBzN type with x + y + w + z = 1, the thickness of each layer being less than its critical thickness, b2) repetition of step b1) at least 50 times, c) formation of an interlayer having a first mesh parameter d) formation of a layer of lll-n material whose mesh parameter is greater than the first parameter mesh.
    [16" id="c-fr-0016]
    16. The production method according to claim 15, wherein in step b), carbon is incorporated into the layers of the superlattice.
    [17" id="c-fr-0017]
    17. The production method according to claim 15 or 16, wherein the layers of the structure are formed by growth, advantageously by organometallic vapor phase epitaxy.
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    FR2977260B1|2011-06-30|2013-07-19|Soitec Silicon On Insulator|PROCESS FOR PRODUCING A THICK EPITAXIAL LAYER OF GALLIUM NITRIDE ON A SILICON SUBSTRATE OR THE LIKE AND LAYER OBTAINED BY SAID METHOD|
    FR3028670B1|2014-11-18|2017-12-22|Commissariat Energie Atomique|SEMICONDUCTOR SEMICONDUCTOR LAYER STRUCTURE OF GROUP III-V OR II-VI COMPRISING CRYSTALLINE STRUCTURE WITH CUBIC OR HEXAGONAL MESH|JP6473017B2|2015-03-09|2019-02-20|エア・ウォーター株式会社|Compound semiconductor substrate|
    DE102016120335A1|2016-10-25|2018-04-26|Osram Opto Semiconductors Gmbh|Semiconductor layer sequence and method for producing a semiconductor layer sequence|
    FR3066045A1|2017-05-02|2018-11-09|Commissariat A L'energie Atomique Et Aux Energies Alternatives|LIGHT-EMITTING DIODE COMPRISING WAVELENGTH CONVERSION LAYERS|
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    FR1558766A|FR3041470B1|2015-09-17|2015-09-17|SEMICONDUCTOR STRUCTURE HAVING IMPROVED TENSION|FR1558766A| FR3041470B1|2015-09-17|2015-09-17|SEMICONDUCTOR STRUCTURE HAVING IMPROVED TENSION|
    US15/266,125| US9923061B2|2015-09-17|2016-09-15|Semiconductor structure with enhanced withstand voltage|
    EP16189001.7A| EP3144956A1|2015-09-17|2016-09-15|Semiconductor structure with improved voltage resistance|
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