 METHOD OF WRITING IN A MEMORY OF THE EEPROM TYPE AND CORRESPONDING MEMORY DEVICE
专利摘要:
According to one embodiment, it is proposed to automatically accelerate the write operation by deleting on the basis of the values of the data to be written and possibly on the basis of the values of the data present in the memory, the step of erase or the programming step, and this while possibly using a conventional write command. When the memory is equipped with an error correction code based on a Hamming code, a property of the latter makes it easy to implement this possible acceleration of write cycles within the memory. This property is that when all the byte bits of a digital word grouping n bytes are equal to zero, the control bits associated with these bytes are also all equal to zero. 公开号:FR3039922A1 申请号:FR1557577 申请日:2015-08-06 公开日:2017-02-10 发明作者:Francois Tailliet；Marc Battista 申请人:STMicroelectronics Rousset SAS； IPC主号:
专利说明:
Method of writing to a memory of the EEPROM type and corresponding memory device Embodiments and embodiments of the invention relate to the electrically programmable and erasable ROMs known as EEPROM memories, and more particularly to the operation of writing a digital word in a memory location of such a memory. At present, the aim is to produce EEPROM memories with increasingly high densities, that is to say, ever larger memory capacities, for example several megabits. But this leads to an increase in the data transfer time. In read mode, the data transfer time is determined by the transfer of data read on the bus. In writing, the transfer time of the data is determined by the transfer on the bus of the data to be written as well as by the duration of the write operation. There is therefore a need to reduce this data transfer time. One solution is to increase the frequency of the bus. However, when using a bus type I2C, that is to say, open drain, the maximum frequency is limited by the speed / consumption compromise. In practice, a value of 1 MHz is currently a maximum value for this type of bus. For a bus of the SPI type, there is not really a limit for the maximum value of the frequency, but currently a frequency of 20 MHz is the maximum frequency used in applications requiring integrated circuits powered with a 5 V supply. Generally, an operation or write cycle in an EEPROM requires two steps, namely an erase step followed by a programming step. In the erase step, an erase pulse erases all (zero) all the memory cells of the bytes to be written. In the programming step, a programming pulse selectively programs (sets to 1) the memory cells which must store a logical 1. Each of these pulses is of the order of a millisecond and this duration results from a compromise between the constraints of a manufacturing process capable of supplying high voltage (for example 15 or 16 V), the endurance of the memory (for example 4 million cycles) and the rate of breakdown of the gate oxide. Increasing the programming voltage from 16 V to 17 V could typically save a ratio 10 over the duration of the write operation but at the cost of technological constraints and reduced endurance possibly a decade and a half. grease oxide breakdown rate increased by several decades. In addition, such a fast write mode must be activated by a dedicated command ("opcode") and for a limited number of times (at the factory for example). When a large amount of data is to be written on N pages, one solution may be to simultaneously delete these N pages in a single cycle and sequentially program all the N pages one by one. However, such a programming mode again requires a dedicated command and the user must ensure that the pages concerned are in an "erased" status before receiving such a command because otherwise the new data will be combined with the old data to through a logical OR function. According to one embodiment of implementation is proposed another solution to reduce the duration and therefore the consumption of a cycle or write operation in an EEPROM memory and / or to improve the endurance of the memory. According to one embodiment of implementation it is proposed to automatically accelerate the write operation and / or to improve the endurance of the memory, by deleting on the basis of the values of the data to be written and / or the basis of the values of the data present in the memory, the erasure step and / or the programming step, and this, while possibly using a conventional writing command and avoiding any over-programming, accidental or voluntary memory cells of the memory plane. A deletion of a programming step (or an inhibition of the programming means) is understood here and in the rest of the text as an absence of generation of the programming pulse (in other words there is no programming step) which results in an acceleration of the write cycle and an improvement of the memory endurance) or else a generation of the programming pulse but without selection of the memory cells concerned. results in an improvement of the memory endurance but without acceleration of the write cycle if the erase step has remained. Thus according to one aspect there is provided a method of writing at least one digital word in at least one memory location of a memory plane of an electrically programmable and erasable read-only memory device (EEPROM), the method comprising a method particular write implemented within the memory device and including a possible deletion of the erase step and / or the programming step of the operation or write cycle based on the previous content of the memory device. memory location and / or new contents of the memory location including the digital word to be written. Indeed, in certain cases the write operation may comprise only an erasure step or only a programming step or else no erase step or programming step, which then makes it possible to accelerate the write cycle and thereby reducing its consumption and / or improving the endurance of memory. Thus, if for example the word to be written contains only "0", then only one erasing step is necessary. If in addition to the previous contents of the memory location in which we only want to write "0's", already contained only "0's", then the erase step can also be deleted. Similarly, when for example the word OF (in hexadecimal notation) must be replaced by the word 1F, or if the previous content of the memory location in which we wish to write a digital word already contains only "0", then the erasure step is useless. More generally, according to an embodiment, this particular mode of writing comprises a deletion of the erasure step if said new content of the memory location is bit-bit greater than or equal to said previous content of this memory location. , the previous content being supposed to be error free. The previous content can be assumed to be error-free (that is, no bit of this prior content is considered unreliable), for example, given the conditions of use of the memory or because this prior content has been checked and possibly corrected by an error correction code mechanism if the memory is equipped with it. If said new content of the memory location is bitwise equal to said previous contents of this memory location, then this particular write mode also includes a deletion of the programming step. Further, if said new content of the memory location is bit-to-bit greater than or equal to said previous content and at least one bit of the new content is greater than the corresponding bit of the previous content assumed to be error-free, then the particular mode includes only programming each bit of the new content higher than the corresponding bit of the previous content. This avoids any risk of accidental or deliberate over-programming of or corresponding memory cells. A particularly simple way of implementing such selective programming is to control the programming of each bit for which the result of a logic function AND applied to the new value of this bit and to the opposite of the old value of this bit. bit, is equal to 1. This particular mode of writing is implemented internally to the memory device, that is to say that it is the memory device itself that detects the values of the data to be written and / or the values of the data. data present in the memory, and which decides for the given write cycle, on the basis of the values of the data to be written and / or on the basis of the values of the data present in the memory, to delete at least one of the steps erase or programming or to preserve the classic succession step of erasure / programming step. This decision can easily be implemented by a simple combinatorial logic. In other words, it is not an element external to the memory device, for example the microcontroller which delivers the write command, which will decide to control these possible deletions of steps in view of, for example, an analysis. made by this external element, values of the data to be written and / or values of the data present in the memory. Thus, when this particular mode of writing is implemented and activated in the memory, the user of the memory does not have the hand on a decision to accelerate one or more write cycles, which allows in particular as indicated above to avoid any overprogramming, accidental or voluntary, memory cells of the memory plane. All this is particularly interesting especially for high capacity EEPROM memories. Such memories generally use an error correction code (ECC) mechanism. The particular mode of writing mentioned above can be applied to a memory equipped with an error correction code mechanism, whatever this code. However, when the error correction code is based on a Hamming code, a property of the latter makes it easy to implement a possible acceleration of the writing cycles and / or an improvement of the endurance within the device. of memory. This property is that when all the byte bits of a digital word grouping n bytes are equal to zero, the control bits (also sometimes called "parity bits" or "error correction bits") associated with these bytes are also all equal to zero. The person skilled in the art knows the characteristics and the properties of the Hamming codes. Nevertheless, it is recalled here for all practical purposes that a Hamming code is a linear correcting code, called "perfect" (that is to say that for a given code length there is no other more compact code having the same correction capability) and minimum distance (Hamming distance) equal to three. Thus, according to another aspect, there is provided a method for writing at least one digital word in at least one memory location of a memory plane of an electrically programmable and erasable read-only memory device comprising a correction code mechanism. Hamming code type error, said digital word comprising at least one byte of data and said memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as bits of data. control. Classically, the memory array of the memory device comprises memory cells connected to row selection lines and bit lines. The bit lines are grouped into columns comprising, for example, M bit lines. The memory cells connected to the same selection line form a word line and a memory location or memory word comprises for example the memory cells of the same word line connected to the M bit lines of a column. Such a memory location makes it possible for example to store a digital word of 32 data bits (4 bytes) and 6 control bits. The method according to a variant of this aspect comprises a first write mode implemented within the memory device and comprising in response to a write command of said digital word, a reading of the current content of the memory location, a calculating new control bits associated with the data of the new content of said memory location, and writing the new contents of the memory location including said digital word and the new control bits by a programming step without prior erase step if all the bits of said current content read are at 0, or by a conventional succession of an erasure step and a programming step if at least one bit of said current content read is at 1. Thus, simply reading the bits of the current content makes it possible to detect whether the current content of the memory location, that is to say the data present in this memory location before said writing, consists solely of bits equal to 0. And, if the current content of the memory location consists only of bits equal to 0, the write command of the digital word will trigger the writing of the new content including the digital word using only a programming step without any step. pre-clearing which reduces the duration of the operation or write cycle. This would not have been easily possible, if not impossible, if one had used an error correction code (different from the Hamming code) for which data bits all equal to 0 lead to control bits that are not all equal. Indeed, in such a case, the new control bits of the new contents of the memory location should have "1" located in the same places as those of the control bits of the previous contents, since a programming is not possible. only able to change a "0" to "1". It should be noted here that when the memory location is capable of storing more than one byte, this step of reading the current contents of the memory location is already implemented so does not need to be added back into the memory. process according to this aspect. The method according to another variant of this aspect comprises a second write mode implemented within the memory device and comprising in response to a write command of said digital word, a calculation of new control bits associated with the data of the memory device. new content of said memory location, and writing of the new contents of the memory location including said digital word and the new control bits by an erasure step without a subsequent programming step if all the data bits of said new content are at 0 , or by a conventional succession of an erasure step and a programming step if at least one bit of said new content is at 1. Although this is possible in particular for the sake of simplification of the state machine of the memory, it is however not necessary to test whether the new control bits are at 0, because given the particularity of the Hamming code if all the data bits of the new content are 0, then the new calculated control bits will be 0. Thus, according to this other variant, if all the bits of the future contents of the memory location are at 0, the programming step is unnecessary and it is thus possible here again to reduce the duration of the write cycle and / or to improve the endurance. It should be noted here that the triggering of the write operation without a programming step is not conditional on the current contents of the memory location, that is to say the previous data present in this memory location before said write, because the erase step is a global step for all the bits of this memory location. The reading of the current contents of the memory location is not necessary in this other variant when the digital word contains only one byte and is associated with 4 control bits. On the other hand, when the digital word comprises several bytes of data, the second write mode further comprises, prior to said calculation of the new control bits, a reading of the current contents of the memory location. The first write mode and the second write mode can of course both be implemented within the memory device. The method according to yet another variant of this aspect comprises a third write mode implemented within the memory device and comprising in response to a write command of said digital word, a reading of the current content of the memory location , and an absence of an erase step and a programming step if all the bits of said current content read are at 0 and if all the data bits of said new content, including said digital word, are at 0. In other words, according to this alternative variant which is optional, if the current content and the new content of the memory location contain only 0, the write cycle has neither an erase step nor a programming step. The first write mode, the second write mode and the third write mode may all be implemented within the memory device. When the memory is intended to be written per page, it is proposed according to another aspect a method of writing several digital words in several memory locations of a memory plane of an electrically programmable and erasable read-only memory device comprising a mechanism code error correction code Hamming code, said plurality of memory locations forming at least one page of the memory plane, each digital word having at least one byte of data and each memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits. According to a variant of this other aspect, the method comprises a first page writing mode implemented within the memory device and comprising in response to a write command of the digital words of said page, a reading of the current content of each memory location, a calculation of new control bits associated with the data of the new content of each memory location, and a writing of the new contents of each memory location including said corresponding digital word and the corresponding new control bits by a programming step without prior erase step if all the bits of each current content read are at 0, or by a conventional succession of an erase step and a programming step if at least one bit of at least one current content read is at 1. According to another variant of this other aspect, also applicable to a page mode write, the method comprises a second page writing mode implemented within the memory device and comprising in response to a write command of the digital words on said page, a calculation of new control bits associated with the data of the new content of each memory location, and a writing of the new contents of each memory location including said corresponding digital word and the corresponding new control bits by an erasure step without a subsequent programming step if all the data bits of each new content are at 0, or by a conventional succession of an erasure step and a programming step if at least one bit of at least one new content is at 1. Again, when each digital word has several bytes of data the second page write mode includes in or before each calculation of the new control bits, a reading of the current contents of each memory location. The first page write mode and the second page write mode can both be implemented, and in this case the writing of the digital words of the page requires a classic succession of an erasure step and a programming step if the respective writes of at least two digital words require different types of steps (for example a digital word requires only one deletion step while another word only requires a programming step) or if the writing of at least one digital word requires a succession of an erasure step and a programming step. According to yet another variant of this other aspect, the method comprises a third page writing mode implemented within the memory device and comprising in response to a write command of the digital words of said page, a reading of the content. current of each memory location, and no erase step and programming step if all the bits of each read current content are at 0 and if all the data bits of each new content including said corresponding digital word, are at 0. The first page write mode, the second page write mode and the third page write mode can be combined, and the writing of the digital words of the page only requires an erasure step if the writing of at least one digital word only requires an erasure step and if the writing of any other digital word does not require a programming step, only requires a programming step if the writing of at least one digital word requires only a programming step and if the writing of any other digital word does not require an erasure step, requires a conventional succession of an erase step and a programming step in all other cases. Like the particular mode of writing mentioned above, each of the three writing modes and each of the three page writing modes that have just been mentioned for memories equipped with error correction code of the Hamming type, is implemented internally to the memory device with in particular the same advantages as those mentioned for the particular mode of writing. The write command initiating the first write mode and / or the second write mode and / or the third write mode and / or the first page write mode and / or the second page write mode and / or the third page write mode can be a conventional writing command or else a specific command. The first write mode and / or the second write mode and / or the third write mode and / or the first page write mode and / or the second page write mode and / or the third mode Page write can be implemented by default within the memory device, or be activatable. Several non-limiting possibilities exist to carry out this activation. For example, it is possible to use a volatile bit or not, programmable by the user, for example a bit of the status word present in the status register of the memory. You can also use a new specific write command. According to another aspect there is provided an electrically programmable and erasable ROM memory device comprising a memory array containing memory locations, erasing means configured to erase the contents of a memory location, configured programming means for programming at least one digital word in a memory location and control means configured in response to a write command of said digital word optionally inhibiting the erasing means and / or the programming means according to the prior content of the memory location and / or new contents of the memory location including the digital word to be written. According to one embodiment, the control means are configured to inhibit the erasing means if said new content is bit-bit greater than or equal to said previous content, the previous content being assumed to be error-free. According to one embodiment, if said new content of the memory location is bit-to-bit equal to said previous content of this memory location, the control means are also configured to inhibit the programming means. According to one embodiment, if said new content of the memory location is bit-to-bit greater than or equal to said previous content and at least one bit of the new content is greater than the corresponding bit of the prior content assumed to be error free, the means control means are configured to activate the programming means so as to perform only a programming of each bit of the new content higher than the corresponding bit of the previous content. According to one embodiment, the control means are configured to control the programming of each bit for which the result of an AND logic function applied to the new value of this bit and to the opposite of the old value of this bit, is equal to 1. According to another aspect applicable in particular to EEPROM memories equipped with error-correcting codes, there is provided an electrically programmable and erasable read-only memory device, comprising a memory plane containing memory locations, a correction code mechanism of Hamming code type error, erasing means configured to erase the contents of a memory location, programming means configured to program at least one digital word having at least one byte in a memory location, said memory location being for to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits, reading means. According to a variant of this other aspect, the device further comprises first control means configured to respond to a write command of said digital word, activate the reading means to read the current contents of said memory location, activate the mechanism of error correction code for calculating new control bits associated with the data of the new content of said memory location, and activating only the programming means (MPR) if all the bits of said current content read are 0 or successively activate the means of erasing and the programming means if at least one bit of said current content read is at 1, so as to write the new content of the memory location including said digital word and the new control bits. According to another variant of this other aspect, the memory device comprises second control means configured in response to a write command of said digital word, enabling the error correction code mechanism to calculate new control bits associated with the commands. data of the new content of said memory location and activate only the erasing means if all the data bits of the new content are 0 or successively activate the erasing means and the programming means if at least one bit of the new content is at 1, so as to write the new contents of the memory location including said digital word and the new control bits. According to one embodiment, when the digital word comprises several bytes of data, the second control means are further configured to activate, prior to the activation of the error correction code mechanism, the reading means for reading the content. current of the memory location. The device may comprise the first and second control means. According to yet another variant of this other aspect, the memory device comprises third control means configured in response to a write command of said digital word, enabling the reading means to read the current contents of said memory location, n ' activate neither the erasing means nor the programming means if all the bits of said current content read are at 0 and if all the data bits of said new content including said digital word are at 0. The device may comprise the first, second and third control means. According to yet another aspect, applicable to a memory intended to be written per page, there is provided an electrically programmable and erasable memory type memory device, comprising a memory plane containing at least one page containing several memory locations, a memory mechanism. error correction code of the Hamming code type, erasing means configured to erase the content of a page, programming means configured to program several digital words in the memory locations of said page, each digital word comprising at least one byte, said corresponding memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits, reading means, and fourth control means configured to respond to a command to write digital words, activate the reading means e to read the current contents of each memory location, activate the error correction code mechanism to calculate new control bits associated with the data of the new content of each memory location and activate only the programming means if all the bits of each current contents read are at 0 or successively activate the erasing means and the programming means if at least one bit of at least one current content read is at 1, so as to write the new content of each memory location including said word corresponding numerical code and the corresponding new control bits. According to a variant of this other aspect, the device comprises fifth control means configured in response to a command for writing digital words, enabling the error correction code mechanism to calculate new control bits associated with the data of each new content of said memory location and activate only the erasing means if all the data bits of each new content are 0 or successively activate the erasing means and the programming means if at least one bit of each new content is to 1, so as to write the new contents of each memory location including said corresponding digital word and the new corresponding control bits. According to one embodiment each digital word comprises several bytes of data and the fifth control means are further configured to activate, prior to the activation of the error correction code mechanism, the reading means for reading the current content of each memory location. According to one embodiment, the device comprising control means incorporating the fourth and fifth control means, and configured to control the writing of the digital words of the page by a conventional succession of an erasure step and a step of programming if the respective writes of at least two digital words require different types of steps. According to yet another variant of this other aspect, the device comprises sixth control means configured to respond to a command for writing digital words, activate the reading means to read the current contents of each memory location, activate neither the erasing means nor the programming means if all the bits of each current content read are at 0 and if all the data bits of each new content including said corresponding digital word are at 0. Control means may incorporate the fourth, fifth and sixth control means, and be configured to control the writing of the digital words of the page only by an erasure step if the writing of at least one digital word requires only an erasure step and if the writing of any other digital word does not require a programming step, only by a programming step if the writing of at least one digital word requires only a programming step and if writing no other digital word requires an erasure step, and a conventional succession of an erase step and a programming step in all other cases. According to one embodiment the control means and / or the first control means and / or the second control means and / or the third control means and / or the fourth control means and / or the fifth control means and / or the sixth control means are activatable. Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and embodiments, in no way limiting, and the accompanying drawings, in which: FIGS. 1 to 11, essentially diagrammatic, relate to to different modes of implementation and embodiment of the invention. In FIG. 1, the reference DIS denotes an example of an EEPROM type memory device according to the invention. This device DIS comprises a memory plane PM of CEL memory cells, as well as conventional means of programming MPR and erasure MEFF comprising in particular HV means for applying a high programming or erasure voltage, line decoders and DECX and DECY columns as well as reading means comprising AMPL read amplifiers connected to an RDD data register. The device DIS also comprises, in this embodiment example, means MECC forming an error correction code mechanism of the Hamming code type, of conventional structure and known per se. The device DIS also comprises MCM control means comprising for example logic means of conventional structure capable of activating the various MPR programming means, MEFF erasure, AMPL reading and the MECC error correction code mechanism. The memory device DIS also includes here an SRG status register. This register is however optional, generally present for a memory connected to an SPI bus and in particular nonexistent for a memory connected to an I2C bus. Other conventional means present in the memory device DIS and not essential to the understanding of the invention, such as for example the shift address register, have not been deliberately represented in FIG. 1 for simplification purposes. . It is recalled here that a memory cell CEL EEPROM type comprises a transistor conventionally having a control gate, a floating gate, a drain region and a source region. Such a cell is erasable and programmable by Fowler-Nordheim effect. Conventionally, the operation or cycle of writing data in such an EEPROM type cell comprises an erasure step preceding a programming step. In the erase step, the erasure means MEFF are configured to couple the drain and the source of the transistor to ground and to apply to the control gate a control voltage having an erase value, typically order of 15 volts. In the programming step of the cell, the programming means MPR are configured to connect the control gate to ground and apply a programming voltage to the drain, typically also of the order of 15 volts. Regarding the source, the MPR programming means are configured to either leave the floating source or preload it at a non-zero precharge voltage. More precisely, the erasing means are configured to apply the control voltage to the control gate in the form of an IMPI erase pulse while the programming means are configured to apply the programming voltage to the drain under the control channel. form of a programming pulse IMP2 (Figure 2). Each erase pulse or voltage / time programming has a trapezoidal shape having a ramp followed by a PLT plate, typically at the nominal level of 15 volts. The voltage ramp controls the tunnel current of the cell. The ramp and the plateau have approximately the same durations. As indicated above, the erasure means MEFF and MPR programming comprise the HV means for generating the high voltage for generating the corresponding erasure and programming pulses. These HV means comprise for example conventionally one or more stages of charge pumps associated with a control of charge pumps comprising for example an oscillator. The regulation controls the output voltage of the charge pump. The oscillator is stopped when the output of the charge pump exceeds a high reference. The output voltage of the charge pump then begins to decrease due to charging. As soon as the output voltage of the charge pump is lower than a low reference, the oscillator restarts. The voltage difference between the low and high references (hysteresis) ensures stability. This voltage difference is for example of the order of 100 millivolts. The regulation level of the charge pump is for example the voltage level of the PLT plate, for example 15 volts. The charging ramp is for example generated by an analog integrator which receives as input the plateau voltage. The duration of the pulse (ramp + plateau) can be controlled by a timer ("timer"), analog or digital. As a guide, a digital stopwatch may include a fixed frequency oscillator connected to a counter. The meter starts when the charge pump starts and the end of the count marks the end of the pulse. As indicated above, in the erasure step, the erase pulse globally erases (resets) all the memory cells of the bytes to be written. In the programming step, the programming pulse selectively (sets to 1) the memory cells which must store a logical 1. While the write operation generally comprises an erase step followed by a programming step, it is possible, in some cases, for a single erasure or programming step to be necessary to write a word in the memory. Thus, if the word to be written contains only "0", then only one erase step is necessary. If in addition memory cells in which one wishes to write only "0", already contained only "0", then the erase step can also be deleted. Similarly, by way of non-limiting example, when the word OF (in hexadecimal notation) must be replaced by the word 1F, the erasure step is unnecessary. Thus according to one aspect there is provided a method of writing at least one digital word in at least one memory location of a memory plane of an electrically programmable and erasable read-only memory device (EEPROM), the method comprising a method particular write implemented within the memory device and including a possible deletion of the erase step and / or the programming step of the operation or write cycle based on the previous content of the memory device. memory location and / or new contents of the memory location including the digital word to be written. And this particular mode of writing is implemented internally to the memory device, that is to say that it is the memory device itself which detects the values of the data to be written and / or the values data present in the memory, and which decides for the writing cycle in question, on the basis of the values of the data to be written and / or on the basis of the values of the data present in the memory, to delete at least one of the erase or programming steps or to preserve the classic succession erase step / programming step. This decision can easily be implemented by simple combinational logic forming control means within the MCM control means. More precisely, according to an implementation mode illustrated in FIG. 3, the control means test in step 300 whether said new content of the memory location is bit-to-bit greater than or equal to said previous content of this memory location, the previous content being assumed to be error free. In the negative, the control means control the writing of the new content by activating successively (steps 310 and 320) the erasing means and the programming means. If so, this particular write mode includes a deletion of the erase step if said new content of the memory location is bit-to-bit greater than or equal to said previous content of that memory location, the previous content being assumed to be without error. The control means also tests in step 301 whether said new content of the memory location is bit-to-bit equal to said previous content of this memory location. If this is the case, this particular mode of writing also includes a deletion of the programming step. In other words, there is neither erasure nor programming (step 302), it being understood that an inhibition of the programming step is understood as a non-generation of the programming pulse or as a generation of this programming pulse but without selection of memory cells (without selection of bit lines). Further, if said new content of the memory location is bit-to-bit greater than or equal to said previous content and at least one bit of the new content is greater than the corresponding bit of the previous content assumed to be error-free, then the particular mode includes only programming each bit of the new content higher than the corresponding bit of the previous content. This avoids any risk of accidental or deliberate over-programming of or corresponding memory cells (step 303). A particularly simple way of implementing the test of step 300 is illustrated on the left-hand part of FIG. More precisely, a logic AND function is applied (step 3000) to the value of each bit of the prior CNT content and to the opposite value of each peer bit of the new NVC content (embodied by the INV1 inverters). Then (step 3001) an AND logic function is applied to the inverted outputs by the INV2 inverters of the AND function. One then tests (step 3002) if the output of the AND function is at 1. If so, said new content of the memory location is bit-bit greater than or equal to said previous content. This is not the case in the negative. A particularly simple way of implementing such selective programming is, as illustrated on the right-hand part of FIG. 4, to test (step 3031) for each bit if the result of an AND logic 3030 applied to the new value of this bit and the opposite (materialized by the inverter INV3) of the old value of this bit, is equal to 1. If yes, this bit will be programmed because a 1 will replace a 0 (the new bit will be greater than the previous bit). If not, this bit will not be programmed. As will now be described in more detail, the invention is particularly interesting for EEPROMs equipped with a MECC error correction code mechanism Hamming code type, particularly high capacity memories. Nonvolatile memories, in particular of the EEPROM type, are subject to data corruptions due to memory locations or defective memory cells commonly designated by those skilled in the art under the English name "single bit fails". These defects may be present initially on "new" memories or be absent initially but generated over time during the life of the room. These defects may be due, for example, to defectivities in the manufacturing process, to oxide breakdowns, to appearance of loss of retention on isolated memory cells. These defective memory locations lead, when reading the bits contained in these locations, to erroneous logic values. A conventional solution is to use error correction code or Ecc ("Error code correction") to correct the erroneous logical value of a bit. More precisely, with an error correcting code, if one adds s control bits (or parities) to b data bits one can correct r errors among the b + s bits. Generally, the error correction codes used in the field of memories make it possible to correct a single error (r = 1) in the word of b + s bits. Two errors in one memory may be corrected provided that the two defective locations correspond to two bits not in the same group of (b + s) bits. More precisely, as is conventional and known, the MECC error corrector code means make it possible, during the reading of a word in the memory, to determine a syndrome from the data bits b and from the set of control bits s. We recall here that a syndrome is the result of intermediate calculations performed during the error correction, to detect and locate the error. Conversely, the MECC means are also capable of computing a set of control bits from a set of data bits. Classically, the memory array of the memory comprises CEL memory cells connected to row selection lines and bit lines. The bit lines are grouped into columns comprising, for example, M bit lines. M can be for example equal to 38, thus corresponding to useful b-bit words (b = 32 corresponding to n = 4 bytes) accompanied by s (s = 6) error correction code bits or parity bits. The memory cells connected to the same selection line form a word line and the memory cells of the same word line connected to the M bit lines of a column form a memory or memory word location for storing a digital word. 32-bit and 6-bit parity. The EEPROM memories can be organized by pages (a page containing all the memory words of the same word line). The amount of data that can be written in a write cycle can vary from one word to a full page. In an EEPROM memory architecture equipped with an error correction code mechanism, whenever it is desired to write for example p new bytes in a memory location containing n bytes (with n greater than one and p greater than or equal to at one and less than or equal to n) and s control bits, one reads the current contents of the memory location, that is to say here the 38 bits of this memory location. An error correction is possibly performed by the MECC error correction code mechanism. As a result, the bit values of the current (initial) 4 bytes are known. In addition, new control bits are recalculated from the new p bytes and the other n-p other bytes. The property of a Hamming code error correcting code is used here, according to which when the byte bits of a memory location grouping n bytes are all equal to 0, then the control bits contained in this memory location are all equal to 0. Thus, in the example described here, when the 32 bits of the 4 bytes contained in the 38 bit memory location are all 0, the control bits and thus the 38 bits of the memory location are all 0. Figures 5 to 8 apply to a memory location memory location write, not to a page write. One can define, as illustrated in FIG. 5, a first write mode, in which in response to a write command of a digital word in a memory location (step 30), the reading means perform a reading 31 current contents of the corresponding memory location (the 38 bits) including the 6 control bits. The control means MCM then test, for example using a combinational logic and / or a comparator, if all the read bits are at 0 (step 32). If at least one read bit is 1, the control means activate a first time (step 35) the MECC means to correct (if necessary) the initial content of the memory location, activate a second time the MECC means to compute the new control bits (step 36) then successively activate the erasing means MEFF and the programming means MPR so as to write the new contents of the memory location including the digital word by a conventional succession of a erase step 37 and a programming step 38. If the response to the test 32 is positive, the control means can re-execute the step 35 so as to activate the MECC means a first time, activate the MECC means a second time to calculate the new control bits (step 39) then only the MPR programming means so as to proceed to write the new content of the memory location including the digital word by a programming step 40 without prior deletion step because unnecessary since all the bits of the memory location are already at 0. It should be noted that step 35 performed in the left branch of Fig. 5 is optional because all bits read at 0 correspond in the Hamming code to no bit errors. That being to execute this step 35, makes it possible to simplify the architecture of the state machine incorporated in the control means. It would also be possible to perform step 35 between steps 31 and 32. It is also possible to define, as illustrated in FIG. 6, a second write mode in which, in response to a write command of a digital word in a memory location (step 40a), the reading means perform a reading. current contents of the memory location (the 38 bits of the memory location) including the 6 control bits. Then the MECC error-correcting code mechanism corrects (if necessary) the initial contents of the memory location. The control means MCM then test, for example using a comparator, if all the data bits of the new content of the memory location are at 0 (step 43). Given the particularity of the Hamming code, if all the data bits of the new content are 0, then the new control bits calculated will be 0. If at least one data bit of said new content is 1, the MCM control means activate the error correction code mechanism MECC to perform a calculation 44 of the new control bits associated with the new content envisaged said memory location and then activate successively the erasing means MEFF and the programming means MPR so as to write the new content in the memory location including said digital word by a conventional succession of an erasure step 45 and a programming step 46. If the response to the test 43 is positive, the MCM control means can re-execute the step 44 of calculating the new control bits associated with the proposed new content of said memory location. Here again this re-execution, although preferable for a simplification of the state machine, is optional since in this case the new control bits are at 0. Alternatively, step 44 could be performed between steps 42 and 43. The control means then activate only the erasure means MEFF so as to proceed to a writing of this new content including the digital word by an erasing step 47 without subsequent programming step because unnecessary since all the bits to write are at 0. While only one of these two write modes may be available in the memory device, these two modes may be available together. In this case, as illustrated in FIG. 7, in response to a write command of a digital word in a memory location (step 50), steps analogous to steps 31 and 32 of FIG. 5 are implemented. If the answer to the interrogation of step 32 is "yes", steps analogous to steps 35, 39 and 40 of FIG. 5 are used to write the digital word. If the answer to the interrogation of step 32 is "no", steps similar to steps 42 and 43 of FIG. 6 are implemented. If the answer to the interrogation of step 43 is "yes", steps analogous to steps 44 and 47 of FIG. 6 are used to write the digital word. If the answer to the interrogation of step 43 is "no", steps analogous to steps 44, 45 and 46 of FIG. 6 are used to write the digital word. With the first and second writing modes, it is therefore possible in certain cases to reduce the duration of the writing cycle and consequently the consumption of such a cycle in a factor of up to two and / or to improve endurance. of the product. It is also possible to define, as illustrated on the left-hand part of FIG. 8, a third write mode in which, in response to a write command of a digital word in a memory location (step 60), it implements steps similar to steps 31 and 32 of Figure 5. If the answer to the interrogation of step 32 is "yes", steps analogous to steps 35 of FIG. 5 and 43 of FIG. 6 are implemented. If the answer to the interrogation of step 43 is "yes", then the control means MCM inhibit, after optionally implementing a step similar to step 44 of FIG. 6, the steps of erasing and programming, and the digital word is considered written. Indeed in this third mode we wanted to write "0" in a memory location already containing "0". In this case, if the programming step is effectively inhibited by dispensing with the generation of the programming pulse, the duration and the consumption of the write cycle are zero or almost zero. If, on the other hand, the answer to the interrogation of step 43 is "no", a step similar to step 44 of FIG. 6 is followed, followed by a step similar to step 46 of FIG. the digital word. This third write mode can also be combined with the first and second write modes as illustrated on the right side of FIG. 8. More specifically, if the answer to the interrogation of step 32 is "no", steps similar to steps 35 of FIG. 5 and 43 of FIG. 6 are implemented. If the answer to the interrogation of step 43 is "yes", steps analogous to steps 44 and 47 of FIG. 6 are used to write the digital word. If the answer to the interrogation of step 43 is "no", steps analogous to steps 44, 45 and 46 of FIG. 6 are used to write the digital word. Of course the first, second and third control means respectively functionally intended to implement the first, second and third write modes can be physically grouped within the MCM control means. When the memory is intended to be written per page, the erase pulse can erase all the content of the page globally. Likewise, the programming pulse makes it possible to program selectively and simultaneously all the memory cells of the page. In general, before the generation of an erase and / or programming pulse or the possible absence of generation of such pulses for the writing of the page, the control means go for each memory location. the page, detect the necessary operation (s) necessary to write the new contents of the considered memory location including the new digital word and the new control bits, then apply for writing the worst case page. Thus, as illustrated in FIG. 9, which is the counterpart of FIG. 5, it is proposed a first page writing mode implemented within the memory device by fourth control means incorporated in the control means MCM and providing a test 90 to determine if writing each memory location of the page requires only a programming step. If so, the writing of the page is done by a programming step 91 only. In the opposite case, the writing 92 of the page is carried out conventionally by erasure then programming. As illustrated in FIG. 10, which is the counterpart of FIG. 6, a second page write mode implemented in the memory device by fifth control means incorporated in the control means MCM and providing for a test is proposed. 100 to determine whether the writing of each memory location on the page only requires an erase step. If so, the writing of the page is done by an erase step 101 only. In the opposite case, the writing 102 of the page is carried out conventionally by erasure then programming. The part of FIG. 11 comprising steps 110 and 111 is the counterpart of the left part of FIG. 8, and illustrates a third page writing mode implemented within the memory device by sixth incorporated control means. in the MCM control means and providing a test 110 for determining whether the writing of each memory location of the page does not require an erase step or a programming step. If so, the writing 111 of the page is performed without erasure or programming. The first page write mode, the second page write mode and the third page write mode can be combined, as illustrated in the remainder of FIG. In this case, the writing of the digital words of the page only requires an erasure step 113 if the writing of at least one digital word only requires an erasure step and the writing of any other digital word does not requires a programming step (test 112), requires only a programming step 116 if the writing of at least one digital word only requires a programming step and if the writing of any other digital word does not require erase step (test 115), requires (step 114) a conventional succession of an erase step and a programming step in all other cases. The write command initiating the first write mode and / or the second write mode and / or the third write mode and / or the first page write mode and / or the second page write mode and / or the third page write mode can be a conventional writing command or else a specific command. The first write mode and / or the second write mode and / or the third write mode and / or the first page write mode and / or the second page write mode and / or the third mode Page write can be implemented by default within the memory device, or be activatable. Several non-limiting possibilities exist to carry out this activation. For example, it is possible to use a volatile or non-volatile bit that is programmable by the user, for example a bit of the status word present in the SRG status register of the memory and accessible via an SPI type bus. You can also use a new specific write command. The invention is particularly useful when initially writing the entire memory plane, for example when the memory plane must be written totally with 0. This being the case, the invention also applies when the user wants the memory plane to be viewed by the user as initially written with 1. In this case, it is sufficient to provide for a data inversion during the steps reading and programming so that a user view data is managed internally to the memory device as the complementary data. And a memory map seen by the user as initialized with 1 (FF) will be processed internally as being written with 0's. In the case where only a programming step is performed without prior erase step, the already erased bits can not be refreshed in an erased state. However, this case is not a problem because it implies that all the bits are read internally as 0. And if a bit is in error and appears internally as a 1, then the memory device would execute a cycle. complete write (erase and programming) which would then refresh the bit considered in its erased state. And if a user nevertheless wants to force a refresh of the erased state, he can always do it by entering a 1 in the data to be written (or a 0 if a reversal of data is planned internally), then by writing again the same digital word which will then cause as explained above a complete cycle of writing (erasure and programming). By construction overprogramming ("over-programming") of the EEPROM memory cells can induce functional and reliability problems (leakage, endurance for example). In conventional EEPROM memories, the erase operation is global while the programming operation is selective and always consecutive to an erase operation. As a result, the memory cells can only be over-erased but never over-programmed. The invention also avoids any over-programming of memory cells, because the presence of a programmed memory cell (containing a 1) will prohibit during the next write cycle, as explained above, a write made only with a programming step. And this is particularly interesting because the fact that the memory device automatically manages the step or steps implemented during the write cycle, avoids accidental over-programming caused by the user. It is also not possible with the invention to have a memory word containing a single error and which would not be refreshed with correct content. In fact, the implementation of a programming step without prior deletion step implies that all the bits of the memory word are at 0, and for a Hamming code, the fact that all the bits are at 0 implies absence of a single bit in error.
权利要求:
Claims (36) [1" id="c-fr-0001] 1. A method for writing at least one digital word in at least one memory location of a memory plane of an electrically programmable and erasable read-only memory device, comprising a particular mode of writing implemented within the device of memory (DIS) and optionally deleting the erasure step (310) and / or the programming step (320) of the write operation according to the previous contents of the memory location and / or new content of the memory location including the digital word to write. [2" id="c-fr-0002] The method of claim 1, wherein the particular write mode includes deleting the erase step (302, 303) if said new memory location content is bit-bit greater than or equal to said previous content from this memory location, the previous content being assumed to be error-free. [3" id="c-fr-0003] The method of claim 2, wherein if said new memory location content is bit-to-bit equal to said previous contents of said memory location, the particular write mode also includes a deletion of the programming step (302). ). [4" id="c-fr-0004] The method of claim 2 or 3, wherein if said new memory location content is bit-to-bit greater than or equal to said previous content and at least one bit of the new content is greater than the corresponding bit of the assumed prior content. to be error free, the particular mode includes only selective programming (303) of each bit of the new content greater than the corresponding bit of the previous content. [5" id="c-fr-0005] The method according to claim 3 or 4, wherein said selective programming comprises a programming of each bit for which the result of an AND logic function (3030) applied to the new value of this bit and to the opposite of the old value of this bit, is equal to 1. [6" id="c-fr-0006] 6. A method of writing at least one digital word in at least one memory location of a memory plane of an electrically programmable and erasable read-only memory device comprising a Hamming code type error correction code mechanism. said digital word comprising at least one byte of data and said memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits, the method comprising a first write mode implemented within the memory device and comprising in response to a write command of said digital word, a reading (31) of the current contents of the memory location, a calculation (36, 39) of new control bits associated with the data of the new content of said memory location and writing of the new contents of the memory location including said digital word and the new ones control bits by a programming step (40) without prior deletion step if all the bits of said current content read are at 0, or by a conventional succession of an erase step (37) and a step of programming (38) if at least one bit of said current content read is 1. [7" id="c-fr-0007] A method for writing at least one digital word in at least one memory location of a memory plane of an electrically programmable and erasable read-only memory device equipped with a code error correction code mechanism of Hamming, said digital word comprising at least one byte of data and said memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits, the method comprising a second write mode implemented within the memory device and comprising in response to a write command of said digital word, a calculation (44) of new control bits associated with the data of the new content of said memory location and a writing the new contents of the memory location including said digital word and the new control bits by an erasing step (47) without a stag e later programming if all the data bits of said new content are 0, or by a conventional succession of an erase step (45) and a programming step (46) if at least one bit of said new content is at 1. [8" id="c-fr-0008] 8. The method of claim 7, wherein the digital word comprises several bytes of data and the second write mode further comprises prior to said calculation (44), a reading (41) of the current content of the memory location. [9" id="c-fr-0009] 9. The method of claim 6 and one of claims 7 or 8, comprising the first write mode and the second write mode. [10" id="c-fr-0010] A method of writing at least one digital word in at least one memory location of a memory plane of an electrically programmable and erasable read-only memory device equipped with a code error correction code mechanism of Hamming, said digital word comprising at least one byte of data and said memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits, the method comprising a third write mode implemented within the memory device and comprising in response to a write command of said digital word, a reading (31) of the current content of the memory location, and an absence of a step of erasure and programming step if all the bits of said current content read are at 0 and if all the data bits of said new content including said digital word are at 0. [11" id="c-fr-0011] 11. The method of claims 9 and 10, comprising the first write mode, the second write mode and the third write mode. [12" id="c-fr-0012] A method of writing multiple digital words in multiple memory locations of a memory array of an electrically programmable and erasable read only memory device having a Hamming code type error correcting code mechanism, said plurality of memory locations forming at least one page of the memory plane, each digital word comprising at least one byte of data and each memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as bits control method, the method comprising a first page write mode implemented within the memory device and comprising in response to a write command of the digital words of said page, a reading of the current contents of each memory location, a calculation of new control bits associated with the data of the new content of each memory location and a write iture of the new contents of each memory location including said corresponding digital word and the corresponding new control bits by a programming step (91) without prior erase step if all the bits of each read current content are at 0, or by a conventional succession (92) of an erasure step and a programming step if at least one bit of at least one current content read is 1. [13" id="c-fr-0013] A method of writing multiple digital words in multiple memory locations of a memory array of an electrically programmable and erasable read-only memory device having a Hamming code type error correcting code mechanism, said plurality of memory locations forming at least one page of the memory plane, each digital word comprising at least one byte of data and each memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as bits control method, the method comprising a second page write mode implemented within the memory device and comprising in response to a write command of the digital words of said page, a calculation of new control bits associated with the data of the page. new contents of each memory location and write new contents of each memory location included ant said corresponding digital word and the corresponding new control bits by an erasing step (101) without a subsequent programming step if all the data bits of each new content are at 0, or by a conventional succession (102) of an erasure step and a programming step if at least one bit of at least one new content is 1. [14" id="c-fr-0014] 14. The method of claim 13, wherein each digital word comprises several bytes of data and the second page write mode further comprises prior to each calculation (42), a reading (41) of the current content of each memory location. [15" id="c-fr-0015] 15. The method according to claim 12 and one of claims 13 or 14, comprising the first page write mode and the second page write mode and in which the writing of the digital words of the page requires a conventional succession of pages. an erase step and a programming step if the respective writes of at least two digital words require different types of steps. [16" id="c-fr-0016] 16. A method of writing multiple digital words in multiple memory locations of a memory array of an electrically programmable and erasable read-only memory device having a Hamming code type error correcting code mechanism, said plurality of memory locations forming at least one page of the memory plane, each digital word comprising at least one byte of data and each memory location being intended to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as bits control method, the method comprising a third page write mode implemented within the memory device and comprising in response to a write command of the digital words of said page, a reading of the current contents of each memory location, and an absence (111) of clearing step and programming step if all the bits of each current content read are at 0 and if all the data bits of each new content including said corresponding digital word, are at 0. [17" id="c-fr-0017] 17. The method according to claims 15 and 16, comprising the first page write mode, the second page write mode and the third page write mode, and in which the writing of the digital words of the page requires only one step of erasing (113) if the writing of at least one digital word only requires an erasure step and if the writing of any other digital word does not require a programming step, only requires a programming step (116) if the writing of at least one digital word only requires a programming step and the writing of any other digital word does not require an erasure step, requires a conventional succession (114) of a erase step and a programming step in all other cases. [18" id="c-fr-0018] 18. Method according to one of the preceding claims, in which the particular mode of writing, the first mode of writing and / or the second mode of writing and / or the third mode of writing and / or the first mode. page write and / or the second page write mode and / or the third page write mode is and / or are activatable (s). [19" id="c-fr-0019] 19. Memory device of the electrically programmable and erasable ROM type, comprising a memory array (PM) containing memory locations, erasing means (MEFF) configured to erase the contents of a memory location, programming means ( MPR) configured to program at least one digital word in a memory location and control means (MCM) configured to respond to a write command of said digital word may optionally inhibit the erasing means and / or the programming means by depending on the previous content of the memory location and / or the new contents of the memory location including the digital word to be written. [20" id="c-fr-0020] 20. Device according to claim 19, wherein the control means are configured to inhibit the erasing means if said new content is bit-bit greater than or equal to said previous content, the previous content being assumed to be error-free. [21" id="c-fr-0021] The apparatus of claim 20, wherein if said new memory location content is bit-to-bit equal to said previous contents of that memory location, the control means is also configured to inhibit the programming means. [22" id="c-fr-0022] The apparatus of claim 20 or 21, wherein if said new memory location content is bit-to-bit greater than or equal to said previous content and at least one bit of the new content is greater than the corresponding bit of the assumed prior content. without error, the control means are configured to activate the programming means so as to perform only a programming of each bit of the new content greater than the corresponding bit of the previous content. [23" id="c-fr-0023] 23. Device according to one of claims 19 to 22, wherein the control means are configured to control the programming of each bit for which the result of an AND logic function (3030) applied to the new value of this bit and at the opposite of the old value of this bit, is equal to 1. [24" id="c-fr-0024] 24. Electrically programmable and erasable ROM memory device comprising a memory plane (PM) containing memory locations, a mechanism for error correction code (MECC) of the Hamming code type, erasing means (MEFF). ) configured to erase the contents of a memory location, programming means (MPR) configured to program at least one digital word having at least one byte in a memory location, said memory location being adapted to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits, reading means (AMPL), and first control means (MCM) configured to respond to a writing command of said word digital, activate the reading means (AMPL) to read the current contents of said memory location, activate the error correction code (MECC) mechanism to calculate new to the control bits associated with the data of the new content of said memory location and activate only the programming means (MPR) if all the bits of said current content read are at 0 or successively activate the erasing means (MEFF) and the programming means (MPR) if at least one bit of said current content read is 1, so as to write the new content of the memory location including said digital word and the new control bits. [25" id="c-fr-0025] 25. Electrically programmable and erasable ROM memory device comprising a memory plane (PM) containing memory locations, a mechanism for error correction code (MECC) of the Hamming code type, erasing means (MEFF ) configured to erase the contents of a memory location, programming means (MPR) configured to program at least one digital word having at least one byte in a memory location, said memory location being adapted to contain a number of bytes of data at least equal to the number of data bytes of the digital word as well as control bits, reading means (AMPL), and second control means (MCM) configured to respond to a writing command of said word digital, enable the error correction code mechanism (MECC) to compute new control bits associated with the data of the new content of said memory location e t activate only the erasing means (MEFF) if all the data bits of the new content are at 0 or successively activate the erasing means (MEFF) and the programming means (MPR) if at least one bit of the new content is at 1, so as to write the new contents of the memory location including said digital word and the new control bits. [26" id="c-fr-0026] Apparatus according to claim 25, wherein the digital word comprises several bytes of data and the second control means are further configured to activate, prior to the activation of the error correction code mechanism, the reading means ( AMPL) to read the current contents of the memory location. [27" id="c-fr-0027] 27. Device according to claim 24 and one of claims 25 or 26, comprising the first and second control means. [28" id="c-fr-0028] 28. Electrically programmable and erasable read-only memory device, comprising a memory plane (PM) containing memory locations, a mechanism for error correction code (MECC) of the Hamming code type, erasing means (MEFF ) configured to erase the contents of a memory location, programming means (MPR) configured to program at least one digital word having at least one byte in a memory location, said memory location being adapted to contain a number of bytes of data at least equal to the number of bytes of data of the digital word as well as control bits, reading means (AMPL), and third control means (MCM) configured to respond to a write command of said word digital, activate the reading means (AMPL) to read the current contents of said memory location, activate neither the erasing means (MEFF) nor the programming means (MPR) if all the bits of said current content read are at 0 and if all the data bits of said new content including said digital word are at 0. [29" id="c-fr-0029] 29. Device according to claims 27 and 28, comprising the first, second and third control means. [30" id="c-fr-0030] 30. A memory device of the electrically programmable and erasable read-only memory type, comprising a memory plane (PM) containing at least one page containing several memory locations, a mechanism (MECC) of error correction code of the Hamming code type, means erasing device (MEFF) configured to erase the content of a page, programming means (MPR) configured to program a plurality of digital words in the memory locations of said page, each digital word comprising at least one byte, said corresponding memory location being intended to contain a number of data bytes at least equal to the number of data bytes of the digital word as well as control bits, reading means (AMPL), and fourth control means (MCM) configured to in response to a write command of the digital words, activate the reading means (AMPL) to read the current contents of each memory location, a enable the error correction code mechanism (MECC) to calculate new control bits associated with the data of the new content of each memory location and activate only the programming means (MPR) if all bits of each current content read are 0 or successively activate the erasing means (MEFF) and the programming means (MPR) if at least one bit of at least one current content read is at 1, so as to write the new content of each memory location including said corresponding digital word and the corresponding new control bits. [31" id="c-fr-0031] 31. A memory device of the electrically programmable and erasable read-only memory type, comprising a memory plane (PM) containing at least one page containing several memory locations, a mechanism (MECC) of error correction code of the Hamming code type, means erasing device (MEFF) configured to erase the content of a page, programming means (MPR) configured to program a plurality of digital words in the memory locations of said page, each digital word comprising at least one byte, said corresponding memory location being intended to contain a number of data bytes at least equal to the number of data bytes of the digital word as well as control bits, reading means (AMPL), and fifth control means (MCM) configured to in response to a digital word write command, enable the error correction code (MECC) mechanism to compute new control bits the data associated with each new content of said memory location and activate only the erasing means (MEFF) if all the data bits of each new content are 0 or successively activate the erasing means (MEFF) and the means of programming (MPR) if at least one bit of each new content is 1, so as to write the new content of each memory location including said corresponding digital word and the new corresponding control bits. [32" id="c-fr-0032] Apparatus according to claim 31, wherein each digital word comprises several bytes of data and the fifth control means is further configured to activate, prior to activation of the error correction code mechanism, the reading means ( AMPL) to read the current contents of each memory location. [33" id="c-fr-0033] 33. Apparatus according to claim 30 and one of claims 31 or 32, comprising control means incorporating the fourth and fifth control means, and configured to control the writing of the digital words of the page by a conventional succession of a erase step and a programming step if the respective writes of at least two digital words require different types of steps. [34" id="c-fr-0034] 34. A memory device of the electrically programmable and erasable ROM type, comprising a memory plane (PM) containing at least one page containing several memory locations, a mechanism (MECC) of error correction code of the Hamming code type, means erasing device (MEFF) configured to erase the content of a page, programming means (MPR) configured to program a plurality of digital words in the memory locations of said page, each digital word comprising at least one byte, said corresponding memory location being intended to contain a number of data bytes at least equal to the number of bytes of data of the digital word as well as control bits, reading means (AMPL), and sixth control means (MCM) configured to in response to a write command of the digital words, activate the reading means (AMPL) to read the current contents of each memory location, n activate neither the erasing means (MEFF) nor the programming means (MPR) if all the bits of each current content read are at 0 and if all the data bits of each new content including said corresponding digital word are at 0 . [35" id="c-fr-0035] 35. Device according to claims 33 and 34, comprising control means incorporating the fourth, fifth and sixth control means, and configured to control the writing of the digital words of the page only by an erasing step if the writing of at least one digital word only requires an erasure step and if the writing of any other digital word does not require a programming step, only by a programming step if the writing of at least one digital word requires only a programming step and if the writing of any other digital word does not require an erasure step, and by a conventional succession of an erasure step and a programming step in all other cases . [36" id="c-fr-0036] 36. Device according to one of claims 19 to 35, wherein the control means and / or the first control means and / or the second control means and / or the third control means and / or the fourth means of control. control and / or the fifth control means and / or the sixth control means are activatable.
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同族专利:
公开号 | 公开日 US20170039001A1|2017-02-09| CN106448730B|2019-12-13| CN106448730A|2017-02-22| US10013208B2|2018-07-03| FR3039922B1|2018-02-02|
引用文献:
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2016-07-20| PLFP| Fee payment|Year of fee payment: 2 | 2017-02-10| PLSC| Publication of the preliminary search report|Effective date: 20170210 | 2017-07-20| PLFP| Fee payment|Year of fee payment: 3 | 2018-07-20| PLFP| Fee payment|Year of fee payment: 4 | 2019-07-22| PLFP| Fee payment|Year of fee payment: 5 | 2021-05-07| ST| Notification of lapse|Effective date: 20210405 |
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申请号 | 申请日 | 专利标题 FR1557577|2015-08-06| FR1557577A|FR3039922B1|2015-08-06|2015-08-06|METHOD OF WRITING IN A MEMORY OF THE EEPROM TYPE AND CORRESPONDING MEMORY DEVICE|FR1557577A| FR3039922B1|2015-08-06|2015-08-06|METHOD OF WRITING IN A MEMORY OF THE EEPROM TYPE AND CORRESPONDING MEMORY DEVICE| CN201610099337.1A| CN106448730B|2015-08-06|2016-02-23|Method for writing in an EEPROM memory and corresponding memory| US15/055,546| US10013208B2|2015-08-06|2016-02-27|Method for writing in an EEPROM memory and corresponding memory| 相关专利
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