METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR

专利摘要:
The invention describes a method of forming the spacers of a gate (150) of a field effect transistor (100), the gate (150) being located above a layer (146) of a semiconductor material. -conducteur, comprising a step (410) for forming a dielectric layer (152) covering the gate of the transistor. The step of modifying (430) the dielectric layer (152) is performed by placing the dielectric layer (152) in contact with a plasma formed from a gas formed of at least a first non-carbon gas component whose the dissociation generates said light ions and a second gaseous component comprising at least one species promoting the dissociation of the first component to form said light ions, wherein the ratio of gas between the first component and the second component is between 1: 19 and 19 : 1.
公开号:FR3037715A1
申请号:FR1555667
申请日:2015-06-19
公开日:2016-12-23
发明作者:Nicolas Posseme
申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
IPC主号:

专利说明:

[0001] TECHNICAL FIELD OF THE INVENTION The present invention relates generally to field effect transistors (FETs) used by the microelectronics industry and more particularly to the realization of gate spacers of metal-oxide-semiconductor type transistors (MOSFETs). ) mainly used for the production of all kinds of integrated circuits. STATE OF THE ART The relentless race to reduce dimensions that characterizes the entire microelectronics industry has been achieved only with the provision of key innovations throughout decades of development since the first integrated circuits were produced industrially in the sixties. A very important innovation that dates back to the seventies, and is still used, is to make the MOSFET transistors using a technique in which the source and drain electrodes are self aligned with those of the grid and do not therefore do not require a photoengraving operation for their definition. Combined with the use of polycrystalline silicon grids, it is the grids themselves, made first, which serve as a mask during the doping of the source and drain regions of the transistors.
[0002] Figure la is a sectional view of an example of this type of transistor 100 in progress. It contains the source and drain areas 110, generally designated source / drain zones, since they are very generally perfectly symmetrical and can play both roles depending on the electric polarizations that are applied to the transistor. The grid conventionally consists of a stack of layers 120, a large part of which is always composed of polycrystalline silicon 123. The formation of the source and drain zones is typically done by ion implantation 105 of dopants in the zones 110, the grid 120 serving mask as mentioned above, thus preventing the doping of the area of the MOSFET transistor in which, depending on the voltages applied to the gate, will be able to develop the channel 130 of conduction between source and drain. The basic technique, very briefly described above, well known to those skilled in the art as well as many variants, has been constantly improved in order to improve the electrical performance of the transistors while at the same time accommodating the successive size reductions of the transistors required by an ever increasing integration of a larger number of components in an integrated circuit.
[0003] A widely used technique currently consists in manufacturing the integrated circuits starting from elaborate substrates 140 of silicon-on-insulator type, designated by their acronym SOI, of the English "silicon on insulator". The SOI developed substrate is characterized by the presence of a thin surface layer of monocrystalline silicon 146 resting on a continuous layer 10 of silicon oxide 144, called buried oxide or BOX, acronym for "buried oxide layer". The strength and the mechanical rigidity of the assembly are ensured by the layer 142 which constitutes the body of the SOI substrate, often described as "bulk" to indicate that the starting substrate is very generally made of solid silicon. This structure 15 offers many advantages for the realization of MOSFET transistors. In particular, it allows a drastic reduction of parasitic capacitances due to the presence of the insulating continuous layer 144. With regard to the invention, it will be retained only that the surface layer of monocrystalline silicon 146 can be precisely controlled in thickness and in doping .
[0004] In particular, it is advantageous for the performance of the transistors that the channel 130 may be completely deserted from carriers, that is to say "fully depleted" (FD), an English term that is generally used to designate this state. This is achieved by realizing the transistors from SOI substrates whose surface layer 146 is very thin, which is not without disadvantage otherwise as will be seen in the description of the invention. This type of transistor is thus designated by the acronym FDSOI. An improvement in the basic self-alignment technique that has been universally adopted is the formation of spacers 150 on the flanks of the grid. The spacers 150, typically made of silicon nitride (SiN), will allow in particular the implementation of a technique called "Source and Drain elevated". In order to maintain low electrical resistance to access the source and drain electrodes, despite the size reduction of the transistors, it was indeed necessary to increase their section. This is obtained by selective epitaxy of the source / drain zones 110. During this operation, the initial layer of monocrystalline silicon 14 will be grown locally 112. The grid areas must then be protected to prevent growth from also occurring. from the polycrystalline silicon 123 of the grid. It is, among others, the role of the spacers to perform this function. They also perform a role of preserving the gate during siliciding of the contacts (not shown) which is then performed for the same purpose in order to reduce the series resistance of access to the electrodes of the transistor. The formation of the spacers 150 has become a crucial step in the formation of transistors that now reach dimensions that are commonly measured in nanometers (nm = 10-9 meters) and are generally decananometric in size. The spacers are made without involving any photoengraving operation. They are self-aligned on the gate 120 from the deposition of a uniform layer of silicon nitride 152 (SiN) which is then etched very strongly anisotropically. This etching of the SiN preferentially attacks the horizontal surfaces, that is to say all the surfaces that are parallel to the plane of the SOI substrate. It leaves in place, imperfectly, only the vertical portions of the layer 152, those substantially perpendicular to the plane of the substrate, in order to obtain in practice the patterns 150 20 whose ideal shape would obviously be rectangular. With the known solutions, the size reduction of the transistors makes it very difficult to obtain spacers that fully play their role of isolation and do not induce defects in the production of transistors from SOI substrates. Indeed, in the context of the present invention, and as will be detailed later, it has been found that several types of defect such as those mentioned below appear during the etching of the spacers using one or the other. other known methods of anisotropic etching.
[0005] Figures 1b, 1c and 1c each illustrate a type of defect observed. In particular, a type of etching is used which is said to be "dry" and which is carried out using a process which is most often referred to by its acronym RIE, of the English "reactive-ion eching", c. i.e., "reactive ionic etching". It is an etching process in which a plasma is formed in a confined space that reacts physically and chemically with the surface of the wafer to be etched. In the case of etching a layer of silicon nitride, which is, as we have seen, the preferred material for forming the spacers, the reactive gas is typically methyl fluoride (CH 3 F) which is react with the material to be etched by also introducing oxygen (02). An etching plasma based on fluorine chemistry is thus formed and often designated by its constituents: CH3F / 02 / He. In this plasma, the fluorine compound serves to etch the silicon nitride whereas the oxygen makes it possible to limit the polymerization of the methyl fluoride and also serves to oxidize the silicon when this material is reached during etching. The oxide layer formed on the silicon makes it possible to slow the etching of the silicon at the cost, however, of a surface conversion of the latter into oxide and thus of a silicon surface consumption. Helium serves as a diluent for oxygen.
[0006] The advantage of this type of etching is that it is fairly anisotropic and allows the profile of the spacers 150 to be sufficiently controlled even though the ideal rectangular shape can not be obtained in practice. The disadvantage of this type of etching is that the etch selectivity of the underlying silicon is however limited. The selectivity, that is to say the ratio of etch rates between the silicon nitride and the silicon is of the order of 10 and can reach a maximum of 15 depending on the conditions of formation of the plasma (the nitride is engraved 10 to 15 times faster than silicon). Hydrofluoric acid (HF) or phosphoric acid (H 3 PO 4) etchings are also used which have a much better selectivity, respectively, with respect to silicon or its oxide (SiO 2). but which do not however allow to control the profile of the spacers since the etching is essentially isotropic in this case. Note that this type of engraving is also called "wet cleaning" translation of the English "wet clean".
[0007] It will be noted here that there are numerous publications on the subject of etching silicon nitride and / or gate spacers in general. For example, reference can be made to the following US patents or applications: 2003/0207585; 4,529,476; 5,786,276 and 7,288,482.
[0008] FIG. 1b illustrates a first problem which is related to the insufficient etching selectivity which exists during dry etching of the CH3F / O2 / He type between the silicon nitride and the silicon of the surface layer 146. As a result, a significant fraction of the thin monocrystalline silicon surface layer 146 of the SOI substrate can then be partially consumed 147 during the anisotropic etching of the nitride. As previously mentioned, the surface layer 146 is chosen to be thin in order to improve the electrical characteristics of the transistors. It is typically less than 10 nm. The remaining thickness 145 may be very small. Under these conditions the ion implantation 105 to form the source and drain zones 110 which will follow is likely to be very damaging for the remaining monocrystalline silicon. The dopant implantation energy may be sufficient to cause complete amorphization 149 of the monocrystalline silicon, which will then in particular compromise the next epitaxial growth step 112 intended to form the raised source / drain. As previously mentioned, this last operation is made necessary because of the size reduction of the transistors in order to be able to maintain the access resistances to the source and drain electrodes at sufficiently low values so as not to impact the electrical operation of the transistors. . Growth from a partially or fully amorphous silicon layer will create many defects in the epitaxial layer. FIG. 1c illustrates another problem where there is no significant consumption of the silicon of the surface layer 146 but there is formation of "25 feet" 154 at the bottom of the remaining silicon nitride patterns on the flanks of the grid after engraving. The consequence is that the transition 114 of the junctions which are formed after ion implantation doping 105 of the source and drain zones 110, with the zone of the channel 130, is much less abrupt than when the spacers do not have feet as represented in FIG. previous figures. The presence of feet 154 affects the electrical characteristics of the transistors. It will be noted here that the formation or not of feet at the bottom of the spacers and the consumption or not of silicon of the silicon surface layer 146 of the SOI substrate, described in the previous figure, are antagonistic adjustment parameters of the etching which require a compromise can be found for which, ideally, one does not form feet and it does not significantly attack the surface layer of silicon. FIG. 1d illustrates a third problem which occurs when etching produces excessive erosion of the spacers in the upper portions of the grids and exposes polysilicon 123 in these areas 156. The consequence is that the subsequent epitaxial growth 112 for forming the raised source / drain will also occur at these locations, as well as silicidation of parasitic contacts, which may cause short circuits between the electrodes. Indeed, the etching of the spacers requires that the etching time is adjusted to etch, for example, 150% of the deposited nitride thickness. That is, a 50% overgraft is performed in this example to account for the non-uniformity of the deposit, or the etching operation itself, at a wafer. Thus, in some parts of the wafer it will be seen that there is too much overtorishing which exposes the grid areas 156. This type of defect is also referred to as "faceting". In addition, for some applications it may be necessary to provide a protective layer often based on carbon such as a mask or a photoresist (or "photoresist") or heat-sensitive to protect during the etching of the spacers of the structures formed on the substrate. This is for example the case when producing PMOS transistors close to NMOS transistors whose spacers are in progress. The known etching methods can lead to a high consumption of this protective layer during the etching of the PMOS transistor spacers. Other solutions have been proposed in documents US2014 / 0273292 and FR12 / 62962. These solutions provide for a step 30 of setting up the dielectric layer to modify it on either side of the gate, followed by a step of removing the selectively modified dielectric layer from the unmodified portions.
[0009] In practice, it turns out that with these solutions the layer underlying the dielectric layer, typically the active layer of semiconductor material is impaired which degrades the performance of the transistor.
[0010] The object of the present invention is to propose a method for forming spacers that fully plays their role of isolation and that would eliminate or limit at least some of the defects in the production of transistors, such as the consumption or the alteration of the semi material. -conductor (ie Si, SiGe) of the active layer underlying the layer to be etched, the formation of "feet" at the bottom of the patterns on the flanks of the gate of a transistor, the consumption of a layer of carbon-based protection etc. The other objects, features, and advantages of the present invention will be apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated. SUMMARY OF THE INVENTION In order to achieve this objective, one aspect of the present invention relates to a method of forming the spacers of a gate of a field effect transistor, the gate being located above a layer in one semiconductor material, comprising a step of forming a dielectric layer covering the gate of the transistor. The method comprises, after the step of forming the dielectric layer, at least one step of modifying said dielectric layer by bringing the dielectric layer into contact with a plasma comprising light ions. Plasma creates anisotropic light ion bombardment in a preferred direction parallel to flanks of the grid, the plasma conditions, in particular the light ion energy and the implanted dose being chosen so as to modify at least portions of the dielectric layer which are located on one vertex of the gate and on either side of the gate and which are perpendicular to the sidewalls of the gate while retaining non-modified portions of the dielectric layer covering the sidewalls of the gate. wire rack ; the light ions being ions based on hydrogen (H). The method also comprises at least one step of removing the modified dielectric layer with a selective etching of said dielectric layer modified with respect to the layer 5 in a semiconductor material and vis-à-vis of the unmodified dielectric layer. Particularly advantageously, the step of modifying the dielectric layer is carried out by placing the dielectric layer in the presence of a plasma formed from a gaseous mixture formed of at least a first non-carbonated gaseous component whose dissociation generates said light ions and a second gaseous component comprising at least one species promoting dissociation of the first component to form said light ions, wherein the ratio of gas between the first component and the second component is between 1: 19 and 19: 1 .
[0011] Thus, the step of modifying the dielectric layer is carried out in a plasma formed from a gaseous mixture formed of at least a first non-carbon gas whose dissociation generates said hydrogen-based ions (H) and a second gas comprising at least one species promoting dissociation of the first component to form said hydrogen-based ions (H), wherein the ratio of the first gas to the second gas is from 1: 19 to 19: 1 . Advantageously, the role of the first component is to modify, by ion bombardment, the crystalline structure of the dielectric layer in order to be able, thereafter, to differentiate the initial dielectric layer from the modified dielectric layer. The problem is that if we use a plasma based on only one component, hydrogen (H2), for example, the risk is not to uniformly modify the dielectric layer in its thickness. This results in poor control of the actual depth up to which the modified layer has significantly improved selectivity. In this case, the depth of the ion implantation in the dielectric layer is not equivalent to the thickness of the modified dielectric layer whose selectivity is significantly improved and which will be etched after the bombardment. The addition of a second component advantageously acting as a dissociation gas (such as argon, helium, xenon, nitrogen) makes it possible to facilitate the dissociation of the first component and, by this means, to promote implantation of said first dissociated component in the dielectric layer, in the form of light ions. The implanted dose is therefore higher without having to increase the maximum implantation depth. It is therefore important to find a fair ratio between the content of the first component and the second component in the plasma for modifying the dielectric layer. Advantageously, the ratio of gas between the first component and the second component is greater than 1:19 and less than 19: 1. A lower ratio, which would be the case if the flow rate of the first gas is reduced, would have the effect of limiting the efficiency of the modification of the dielectric film.
[0012] A higher ratio, which would be the case if the flow rate of the first gas is increased, would have the effect of limiting the efficiency of the second gas in terms of dissociation. Advantageously, said ratio is between 1: 19 and 19: 1. Preferably, said ratio is between 1: 9 and 9: 1. Preferably, said ratio is between 1: 5 and 5: 1. In the present patent application a ratio between two gaseous components is a ratio relating to the respective rates of introduction of the components into the chamber of the plasma, typically in the plasma reactor. Each flow is usually measured in sccm. Typically a flow rate is measured with a flowmeter associated with the reactor. In the context of the development of the invention, it has proved problematic to target a threshold depth of selectivity of the dielectric layer that is equal to the implantation depth. From this, two problems then arise: either the etching of the modified dielectric layer 30 is incomplete requiring repeated etching steps until the desired depth is obtained, or the implantation carried out in the dielectric layer extends beyond of the dielectric layer thereby causing an alteration of the underlying layer by implantation.
[0013] If the person skilled in the art had identified these problems, he would at best have reached the following solutions. According to a first alternative, the skilled person would have at best increased the duration of implantation to try to increase the dose without increasing the implanted depth. However, increasing the implantation time is not a solution, since it entails a constraint from an industrial point of view (a loss of time necessarily entailing significant costs). According to a second alternative, the skilled person would have increased the flow of light gas, the problem is that too much concentration of gas in the reactor would not result in a greater depth of implantation. In fact, beyond a certain proportion of the first gas in the plasma, this first gas no longer dissociates. The density of light ion ions in the plasma and thus the content of implanted ions no longer increase. Advantageously, the implantation is carried out from a plasma comprising said light ions. Plasma implantation has the advantage of allowing implantation to be continuous in a volume extending from the surface of the implanted layer. In addition, the use of plasma allows implantation at lower depths than the minimum depths that can be achieved with implants. Thus, a plasma implantation makes it possible to implement efficiently and relatively homogeneously or at least continuously thin layers that can then be removed by selective etching. This continuity of implantation from the implanted face 30 makes it possible to improve the homogeneity of the modification according to the depth, which leads to a constant rate of etching in time of the implanted layer. Moreover, the increase of the selectivity conferred by the implantation with respect to the other layers is effective from the beginning of the etching of the implanted layer. The plasma implantation thus allows a significantly improved control of the engraving accuracy. Plasma implantation typically allows for implantation and subsequent removal of thicknesses extending from the surface of the implanted layer and over a depth of 0 nm to 100 nm. Traditional implanters allow implantation in a volume between 30 nm and several hundred nanometers. On the other hand, conventional implanters do not make it possible to implant the species between the surface of the layer to be implanted and a depth of 30 nm. In the context of the development of the present invention, it has been noted that the implanters do not then make it possible to obtain a sufficiently constant etching rate of the modified layer from the surface of the latter, thus leading to a lower accuracy. etching compared to what the invention allows. The use of a plasma to modify the layer to be removed is therefore particularly advantageous in the context of the invention which aims to remove a thin layer of a dielectric layer, typically between 1 and 10 nm and more generally between 1 and 10 nm. and 30 nm. The modification step made from a plasma modifies the dielectric layer continuously from the surface of the dielectric layer and over a thickness of between 1 nm and 30 nm and preferably between 1 nm and 10 nm. According to a particularly advantageous embodiment, the implantation and the removal of the dielectric layer are carried out in the same plasma reactor. A modification of the layer to be removed by plasma implantation thus makes it possible to effect the modification of the layer and the etching in the same chamber, which is very advantageous in terms of simplification, time and cost of the process. Particularly advantageously, the modification of the dielectric layer by implantation of light ions, ions based on hydrogen (H), makes it possible to considerably improve the selectivity of this layer with respect to the layer in a semiconducting material. conductor, typically silicon. This implantation also causes the thickness of the modified dielectric layer to be increased faster than that of the unmodified dielectric layer. Thus, the invention is based in particular on the fact that the second component forming the plasma is able to act as a dissociation gas vis-à-vis the first component, preferably based on hydrogen. By promoting the dissociation of the first component, ie hydrogen, the density of hydrogen ions in the gas phase is increased. Thus, for the same implantation energy, the density of hydrogen contained in the dielectric layer by using the method according to the present invention is greater than that obtained from a plasma containing only hydrogen (H2). . Furthermore, and particularly advantageously, the consumption of the modified dielectric layer by hydrofluoric acid cleaning, for example, is close to the depth of the ion implantation in said modified dielectric layer. Thus, by controlling the depth of implantation in the dielectric layer, it is possible to estimate with a better precision the thickness of the modified dielectric layer which will be etched after implantation.
[0014] Particularly advantageously, the present invention allows a better control of the modification of the dielectric layer and in particular a better estimation of the thickness of the modified dielectric layer, which can be differentiated more strongly from the initial dielectric layer, thanks to a more a high dose of hydrogen-based light ions implanted in said dielectric layer. Thus, the method according to the present invention proposes a reduction of the ionic energy for a similar thickness of the dielectric layer, allowing, in a particularly advantageous manner, to reduce the faceting of the hard mask as well as the damage that can be generated on the stack Si / SiGe.
[0015] Advantageously, the modification of the dielectric layer is carried out using a carbon-free chemistry so as to avoid the formation of a residual carbon-based layer which would make it difficult to etch the dielectric layer. The etching consumes the modified dielectric layer preferentially to the layer made of a semiconductor material and to the unmodified dielectric layer. Thus, the risk of excessive consumption of the surface layer of semiconductor material is reduced or eliminated. Preferably, the modification of the dielectric layer maintains an unmodified dielectric thickness on the sidewalls of the gate. This thickness is preserved, at least in part, during the selective etching. It then defines grid spacers. The invention thus makes it possible to obtain spacers based on a dielectric material while reducing or even eliminating the problems of the solutions known and mentioned previously. The invention is particularly advantageous for the formation of spacers of FDSOI transistors for example. Also advantageously, the modification of the dielectric layer by implantation of light ions such as hydrogen (H2) also makes it possible to improve the selectivity of this modified dielectric layer with respect to the oxide of the layer in a semi-solid material. -driver.
[0016] Optionally, the method may further have at least any of the features and steps below. Preferably, the implantation parameters, in particular the implantation energy of the light ions from the first component and the implanted dose, are provided so that the modified dielectric layer can be etched selectively vis-à-vis of said semiconductor material and vis-à-vis the unmodified dielectric layer. According to a preferred embodiment, the etching of the dielectric layer is carried out using a carbon-free chemistry. This advantageously makes it possible to avoid the deposition of a carbonaceous layer which can hinder the etching of the dielectric layer.
[0017] Advantageously, the role of the first component is to modify, by ion bombardment, the crystalline structure of the dielectric layer in order to subsequently be able to differentiate the initial dielectric layer from the modified dielectric layer. The problem is that if we use a single component only plasma, hydrogen (H2), for example, the risk is not to uniformly change the dielectric layer in its thickness. This results in poor control of the actual depth of the modified dielectric layer. In this case, the depth of the ion implantation in the dielectric layer is not equivalent to the thickness of the modified dielectric layer that will be etched as a result of the bombardment. On the other hand, if the implanted dose of hydrogen is not sufficient then this also causes nonuniformity of the implanted species in the dielectric layer, thereby causing poor control of the actual depth of the modified dielectric layer.
[0018] The addition of a second component advantageously acting as a dissociation gas (such as argon, helium, xenon, nitrogen) makes it possible to facilitate the dissociation of the first component and, by this means, to promote implantation of said first dissociated component in the dielectric layer, in the form of light ions.
[0019] It is therefore important to find a fair ratio between the content of the first component and the second component in the plasma for modifying the dielectric layer. Advantageously, the ratio of gas between the first component and the second component is greater than 1: 9 and less than 9: 1. According to a preferred embodiment, the first component is selected from hydrogen (H2), silicon nitride (SiH4), hydrogen nitride (NH3) or hydrogen bromide (HBr). According to a preferred embodiment, the second component is chosen from helium (He), nitrogen (N2), argon (Ar) or xenon (Xe).
[0020] According to a preferred embodiment, during the step of modifying said dielectric layer the entire dielectric layer located on the top of the gate and on either side of the gate is modified. According to a preferred embodiment, during the step of modifying said dielectric layer, the dielectric layer situated on the sidewalls of the gate is not modified. According to a preferred embodiment, during the removal step the entire dielectric layer located on the top of the gate and on either side of the gate is removed by etching.
[0021] Particularly advantageously, the dielectric layer is formed of one or more dielectric materials whose dielectric constant k is less than or equal to 8 and preferably to 7. Thus, the present invention is not limited to a dielectric layer formed based on nitride. The present invention is also not limited to a dielectric layer of silicon nitride (SiN). The present invention advantageously extends to any spacer comprising a low k (low-k) dielectric material in which, according to one embodiment, the dielectric layer comprises a material having a dielectric constant of less than 4 and preferably less than 3.1 and preferably less than or equal to 2. The dielectric layer is advantageously a silicon-based layer (Si) .The material of the dielectric layer is preferably selected from: SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, CBN, BN, and SiO2.
[0022] According to one embodiment, the dielectric layer is a non-porous layer. According to another embodiment, the dielectric layer is a porous layer. In the context of the present invention, porous layer means a layer whose presence of vacuum in the film is greater than 5% and preferably between 5 and 10%.
[0023] According to one embodiment, the dielectric layer is made of silicon nitride and the step of forming the dielectric layer comprises a step of depositing the dielectric layer in which it is carried out followed by a step of reducing the dielectric layer. dielectric constant of the dielectric layer.
[0024] Advantageously, the step of reducing the dielectric constant of the dielectric layer comprises introducing porosity into the dielectric layer. In another embodiment, the dielectric layer is silicon nitride and the dielectric layer forming step comprises introducing precursors into the dielectric layer being deposition deposited precursor formation. Advantageously, the dielectric layer is a layer based on silicon nitride and the precursors are chosen so as to form bonds reducing the polarizability of the dielectric layer. These precursors are chosen to generate less polar bonds than silicon nitride, such as Si-F, SiOF, Si-O, C-C, C-H, and Si-CH3. Preferably, the step of modifying the dielectric layer, made from a plasma, modifies the dielectric layer continuously from the surface of the dielectric layer and over a thickness of between 1 nm (nm) and 30 nm, preferably between 1 nm and 10 nm. Advantageously, the flow rate of the first component is between 10 and 1000 sccm (cubic centimeter per minute). Advantageously, the flow rate of the second component is between 10 and 1000 sccm.
[0025] Preferably, the step of modifying the dielectric layer is performed so as to provide a polarization power or source power, at a frequency between 100 Hz (Hertz) and 5 kHz, with a duty cycle of between 10% and 90%.
[0026] According to one embodiment, the modification step comprises bringing the dielectric layer into contact with a plasma comprising the light ions in an etching reactor.
[0027] The term "light ions" means ions from materials whose atomic number in the periodic table of elements is small. In a general manner all the elements that can be implanted in the material to be etched, without causing dislocation of its atomic structure such that it would result in a spraying of the latter, and therefore without re-deposition of the material etched on the walls of the reactor or the patterns being etched themselves, are likely to be suitable. Preferably, the light ions are taken from hydrogen (H2). According to one embodiment, the step of removing the modified dielectric layer is carried out by selective wet etching at the layer of a semiconductor material. Preferably, the semiconductor material is silicon and the step of removing the modified dielectric layer is carried out by selectively wet etching with silicon (Si) and / or with silicon oxide (SiO 2). Preferably, the selective silicon etching is obtained using a solution based on hydrofluoric acid (HF) or using a phosphoric acid solution (H3PO4) for a dielectric layer based on silicon nitride (SiN). According to another embodiment, the removal step is performed by selective dry etching at the layer of a semiconductor material. Preferably, the layer made of a semiconductor material is silicon. Preferably, the step of removing the modified dielectric layer is carried out by selective dry etching with silicon (Si) and / or with silicon oxide (SiO 2). According to one embodiment, the dry etching is carried out in a plasma formed in a confined chamber from a mixture of nitrogen trifluoride (NF3), hydrogen (H2) or ammonia (NH3) to form hydrofluoric acid (HF). Advantageously, the dry etching comprises: an etching step consisting of the formation of solid salts; a step of sublimation of the solid species. This embodiment makes it possible to obtain a very good selectivity of the etching of the modified dielectric layer with respect to the unmodified dielectric layer and to the unmodified semiconductor material. In particular, this selectivity of the etching is much greater (typically a factor of at least 10) than that obtained with a solution of HF.
[0028] Preferably, a single modifying step is performed so as to modify the dielectric layer throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer throughout its thickness. on surfaces parallel to the preferred direction of the bombing.
[0029] Advantageously, the light ions comprise ions based on hydrogen (H2) taken from: H, H +, H2 +, H3 +. According to another embodiment, the light ions comprise hydrogen-based ions (H2) taken from H, H +, H2 +, H3 +. Advantageously, the implantation is carried out so as to modify the entire thickness of the dielectric layer. outside the dielectric layer disposed on the sides of the grid. Thus, etching removes the entire dielectric layer with the exception of at least a portion of the dielectric layer located on the sidewalls of the grid. Advantageously, the thickness of the modified dielectric layer on the sidewalls of the gate is zero or less than the thickness of the dielectric layer before modification by implantation. Advantageously, the implantation modifies the dielectric layer from its surface and to depth corresponding to at least part of its thickness. Preferably, the implantation modifies the dielectric layer uninterruptedly from surface. According to a particular embodiment, the method comprises a single modification step carried out so as to modify the dielectric layer throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer throughout its thickness on the surfaces perpendicular to this plane. These surfaces perpendicular to this plane, that is to say perpendicular to the layer of a semiconductor material forming a conduction channel or solid substrate are typically parallel to the sides of the gate of the transistor.
[0030] Thus, following this single modification step, a selective etching of the modified dielectric layer makes it possible to remove the dielectric layer on all the surfaces except on those parallel to the sidewalls of the grid. According to another embodiment, the method comprises several sequences each comprising a modification step and a withdrawal step. During at least one of the modifying steps, only a portion of the thickness of the dielectric layer is changed. Advantageously, the sequences are repeated until the dielectric layer disappears on all the surfaces parallel to the plane of a substrate on which the grid rests.
[0031] Only the faces parallel to the sidewalls of the grid retain a dielectric thickness, this thickness having not been modified by implantation. According to an advantageous embodiment, the dielectric layer is disposed directly in contact with the layer of a semiconductor material.
[0032] Preferably the dielectric layer is disposed directly in contact with the gate which is preferably formed of a semiconductor material. Advantageously, the gate of the transistor is located on a stack of layers forming an elaborate silicon-on-insulator (SOI) substrate. Preferably, it is disposed directly in contact with the layer forming the conduction channel. Advantageously, the use of the invention with such an SOI substrate makes it possible to preserve the integrity of the superficial layer of very thin thickness which forms the conduction channel of a transistor formed from an SOI substrate. Advantageously, the semiconductor material is silicon.
[0033] Advantageously, the etching is selective for silicon oxide (SiO 2). The semiconductor material may also be germanium (Ge) or silicon-germanium SiGe. The step of removing the modified dielectric layer 3037715 is carried out by selectively etching with Ge or SiGe or and / or with SiGe oxide or Ge oxide. According to one embodiment, the transistor is a FDSOI type transistor. Preferably, the method comprises a step of completely removing the dielectric layer outside the sidewalls and on either side of the gate to expose the layer in a semiconductor material and a step of forming zones. drain source from the layer of a semiconductor material, for example by epitaxy. Another aspect of the present invention relates to a method for etching a dielectric layer selectively with silicon (Si) and / or with silicon oxide (SiO 2) comprising: at least one step of modifying all or part of the dielectric layer by implantation of light ions such as hydrogen (H2) within the dielectric layer to form a modified dielectric layer; at least one step of removing the modified dielectric layer by selective etching of the dielectric layer modified with respect to silicon (Si) and / or silicon oxide (SiO 2).
[0034] Advantageously, the implantation, in particular its energy, the concentration and the nature of the light ions, the dose used and the duration of the implantation process, are provided so that the modified dielectric layer can be selectively etched vis-à-vis -vis the rest of the dielectric layer, that is to say the unmodified dielectric layer.
[0035] Advantageously, the modification of the silicon dielectric layer by hydrogen implantation (H2) makes it possible to improve the selectivity of this layer with respect to silicon and / or silicon oxide. Preferably, the etching is obtained, for example, using a phosphoric acid solution (H 3 PO 4) for a dielectric layer 152 based on silicon nitride or with a solution of hydrofluoric acid (HF) base.
[0036] BRIEF DESCRIPTION OF THE DRAWINGS The objects, objects, and features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which: FIGS. 1a to 1d show, on the one hand, a sectional view of an exemplary MOSFET transistor of the FDSOI type in progress, and, on the other hand, illustrate various defects that can be observed on transistor structures. FDSOI when etching spacers using one of the standard anisotropic etching processes developed by the microelectronics industry. FIGS. 2a to 2d illustrate the steps of an exemplary method according to the invention applied to the production of transistors of the FDSOI type.
[0037] FIG. 3 illustrates the ion implantation profiles obtained for different dopant species in a silicon nitride layer with an energy of 300 eV. FIGURES 4a, 4b and 4c illustrate an embodiment where a dielectric layer 152, formed on a substrate 142, is modified and then removed by etching using a method according to the prior art. FIGURES 5a, 5b and 5c illustrate an embodiment where a dielectric layer 152, formed on a substrate 142, is modified and then removed by plasma etching using a method according to an exemplary embodiment of the invention.
[0038] FIG. 6 summarizes the steps of an exemplary method of the invention for forming spacers and which do not induce or at least limit the defects described in FIGS. 1b-1d. FIG. 7 gives the thickness of the modified dielectric layer as a function of bias voltage (bias) in volts for an ICP type burner.
[0039] The accompanying drawings are given by way of example and are not limiting of the invention. These drawings are schematic representations and are not necessarily at the scale of the practical application. In particular, the relative thicknesses of the layers and substrates are not representative of reality. DETAILED DESCRIPTION OF THE INVENTION It is pointed out that in the context of the present invention, the term "over", "overcomes" or "underlying" or their equivalent does not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. by being either directly in contact with it or separated from it by another layer or another element. In the following description, the thicknesses are generally measured in directions perpendicular to the plane of the lower face of the layer to be etched or a substrate on which the lower layer is disposed. Thus, the thicknesses are generally taken in a vertical direction in the figures shown. On the other hand, the thickness of a layer covering a flank of a pattern is taken in a direction perpendicular to this flank.
[0040] FIGS. 2a to 2d describe the steps of a detailed example of a method according to the invention applied to the production of FDSOI type transistors. The principles of these steps can also be applied to the formation of spacers on the flanks of a gate of another type of transistor. FIG. 2a illustrates the step of depositing a dielectric layer 152, of thickness that is preferentially substantially uniform, on all the surfaces, vertical and horizontal, of the devices being manufactured. This step is preferably carried out using a so-called LPCVD deposition method, ie "low pressure chemical vapor deposition", that is to say "low pressure chemical vapor deposition" . This type of deposit which is practiced under atmospheric pressure indeed allows a uniform deposition on all surfaces regardless of their orientation.
[0041] Although this is not necessary for the understanding of the method of the invention, it will be noted that in this example the gate electrode is composed at this stage of the multi-layer method for certain types of transistors. In addition to the polycrystalline silicon layer 123, in the stack of layers forming the gate 120 there is first the thin insulating layer of gate oxide 121 through which an electric field will be able to develop to create the channel 130 underlying conduction between source and drain when sufficient voltage is applied to the gate. In the most recent MOSFET transistors, a technology 10 called "high-k / metal gate" is used, that is to say that the insulating layer 121 is made of a high-permittivity insulating material. (high-k) covered by a metal gate represented by the layer 122. This technology was developed in particular to reduce the leakage currents through the grid which became much too important because of the decrease in the thickness of the insulating layer 121 to atomic dimensions. At this point, the stack of layers of the grid also comprises a hard mask 124 of protection which will be removed later to allow the resumption of contact on this electrode. This hard mask, which remains in place after etching the gate, is typically made of silicon oxide (SiO2). Its role is to protect the top of the grid from any damage during the etching of the spacers. Preferably, the insulating layer 121 is disposed in contact with the layer 146 of a semiconductor material forming the conduction channel. Preferably, the layer 122 is disposed in contact with the layer 121. Preferably, the layer 123 is disposed directly in contact with the gate oxide formed by the layer 121, if the layer 122 is absent or is disposed directly at the contact of the layer 122. Preferably, the dielectric layer 152 is disposed directly in contact with the layer 123 at the sidewalls of the gate. Preferably, the dielectric layer 152 is disposed directly in contact with the layer 146 of a semiconductor material for forming the conduction channel. According to one embodiment, the dielectric layer 152 is based on nitride. According to one embodiment, the dielectric layer 152 of nitride has a thickness of between 5 and 20 nm, and typically of the order of 10 nm. According to another embodiment, the dielectric layer 152 is based on silicon nitride (SiN). According to another embodiment, the dielectric layer 152 comprises a low k (or low dielectric constant k) dielectric material, with preferably k less than or equal to 7. Thus, the present invention is not limited to a dielectric layer formed based on nitride. The present invention is also not limited to a dielectric layer of silicon nitride (SiN).
[0042] The present invention advantageously extends to any spacer comprising a dielectric material with low permittivity k (called "low-k" in English). The term "permittivity of a material", at the microscopic level, the electric polarizability of the molecules or atoms constituting said material. The permittivity of a material is a tensor magnitude (the response of the material may depend on the orientation of the crystallographic axes of the material), which is reduced to a scalar in isotropic media. The dielectric constant is denoted k in the field of integrated circuits and semiconductors, for example. The so-called "low-k" materials are dielectrics with low permittivity. They are used as insulators between the metal interconnects to reduce the coupling between them. In one embodiment, the dielectric layer 152 has or comprises a material having a dielectric constant of less than 4 and preferably less than 3.1 and preferably less than or equal to 2, thereby reducing the parasitic capacitance to possibly improve the Transistor performance. For example, the material of the dielectric layer 152 is taken from: SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH and SiO2. This reduces the parasitic capacitance and consequently improves the performance of the transistor. Preferably, but only optionally, the method of the invention comprises an optional step of reducing the dielectric constant of the dielectric layer 152. According to an advantageous embodiment, the reduction of the dielectric constant is obtained during the step depositing the dielectric layer 152.
[0043] According to one embodiment, the reduction of the dielectric constant comprises introducing into the dielectric layer 152 formation of precursors which form bonds reducing the polarizability of the dielectric layer 152. These precursors are selected to generate less polar bonds than silicon nitride, such as Si-F, SiOF, Si-O, CC, CH, and Si-CH3. According to another embodiment, alternative or combinable with the previous one, the reduction of the dielectric constant comprises the introduction into the dielectric layer 152 forming a porosity.
[0044] FIG. 2b illustrates the following step of the invention applied to the production of FDSOI transistors in which a modification 430 of the dielectric layer 152 that has just been deposited is carried out directly. Optionally, this operation may have been preceded by a conventional dry etching of type CH3F / 02 / He. The modification step 430 of the dielectric layer 152 as deposited, or of the layer remaining after a first conventional etching, is by implantation 351 of light species also designated light ions. In the context of the present invention, these ions are hydrogen-based ions (H). These ions can be implanted in a material to be etched, without causing dislocation of its atomic structure such that it would cause a spray of the latter. Typically, the modification of the dielectric layer 152 to be etched is based on the implantation of light species based on hydrogen (H) such as: H, H +, H 2 +, H 3 +. Particularly advantageously, the implantation of light species is favored by the incorporation into the plasma of a second component allowing the dissociation of the light ions and therefore the increase in the density of light ions in the plasma and the plasma. increase of the implanted dose.
[0045] These aspects will be described in detail hereinafter with reference to FIGS. 3, 4 and 5. Advantageously, the implantation parameters, in particular the energy imparted to the ions, the duration and the implantation dose are provided in such a way that they are 3037715 26 that the modified dielectric layer 158 may be selectively etched with respect to the layer 146 of a semiconductor material. Advantageously, these parameters are also adjusted so that the modified dielectric layer 158 can be etched selectively with respect to the unmodified portion of the dielectric layer 152. Advantageously, these parameters are also adjusted so that the dielectric layer modified 158 can be etched selectively with respect to a layer made of an oxide typically an oxide of said semiconductor material, the latter forming for example a layer of gate oxide. Typically, the etching is selective of the modified dielectric material by implantation of hydrogen vis-à-vis the silicon oxide. Implantation is effected for example in a plasma based on hydrogen gas (H2). More generally, all gaseous components, which can dissociate the light ions mentioned above, can be used in plasma. It will be noted here that this modification step 430 of the dielectric layer 152 to be etched can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry. Standard etching reactors are used in which low or high density plasmas can be made and the ion energy can be controlled to allow the implantation of the above light species for modifying the layer to be etched. It is also possible to use a type of so-called immersion plasma commonly used for practicing implantation of species on the surface of a device during manufacture. Finally, the implantation can also be done in a standard implanter where the ions are accelerated in an electric field to obtain their implantation in a solid. The modification operation is advantageously very anisotropic for the production of the spacers on the sidewalls of the grids because of the directionality of the ions of the plasma or the implanter. It therefore preferably affects the horizontal surfaces, that is to say all the surfaces parallel to the plane of the substrate 142. The thickness modified on the horizontal surfaces 154 is thus much larger than on the vertical surfaces 156. that is to say on all the surfaces perpendicular to the plane of the elaborated substrate 146, on which the grid is arranged. This plane is perpendicular to the plane of the section shown in Figures 2a to 2d. The prepared substrate 142 preferably forms a plate with two parallel faces. It is for example in the form of a disk, a square, a polygon, etc. The thin layer 146, the buried oxide layer 144 and the solid substrate 142 are arranged in parallel planes. Thus, a surface will be described as horizontal if it is parallel to the plane of the layer or layers forming the substrate 146, on which the grid is formed and a surface will be described as vertical if it is perpendicular to the same plane.
[0046] Typically, a thickness of 10 nm on the horizontal surfaces may be changed during this operation. A thickness 156 of the layer 152 ranging from 1 to 3 nm is however also modified on the vertical surfaces regardless of the plasma conditions. These vertical surfaces with respect to the plane of the substrate 146 are therefore parallel to the sidewalls 15 of the grid. The modified thicknesses depend on the conditions of implementation, in particular on the means employed (plasma or implanter) and also on the fact that it is desired to obtain the etching of the spacers in a single overall modification and etching step or that on the contrary repeat these operations until you obtain a complete engraving.
[0047] Thus, depending on the particular implementations of the method of the invention and the initial thickness of the dielectric layer 152, the step of modifying this layer may affect the whole of this layer where, as shown in FIG. example of Figure 2b, only part of it. In this case, the modification step 430 and the subsequent step 440 of the modified layer described hereinafter can be repeated until the dielectric material of the modified dielectric layer 158 is completely removed on all the horizontal surfaces. FIG. 2c illustrates the final result of the next step after etching, that is to say the removal of the modified dielectric layer 158 and possibly repeated, on the one hand, the modification operation described in the previous figure, and on the other hand, the operation of removing the modified dielectric layer 158.
[0048] A method used for the removal of the modified dielectric layer 158 is, as already mentioned, to use an etching solution, for example, based on hydrofluoric acid (HF) (or phosphoric acid (H3PO4) for a dielectric layer 152 based on silicon nitride). Stopping of the etching is done on the unmodified dielectric layer 152 or on the monocrystalline silicon of the layer 146 or on the hard mask 124 at the top of the grids. It will be noted here, with reference to the problem described in Figure 1b, that there is no consumption of silicon due to the use of hydrofluoric acid or phosphoric acid. Furthermore, an optimization of the modification step 430 by implantation of light species described above entails only a modification of the dielectric layer 152 and the subsequent etching operation does not therefore affect the silicon. underlying. Thus, as shown, there is very advantageously no consumption in the S / D zones 110 of the silicon layer 146.
[0049] At the end of these operations, only the vertical dielectric units are left from the initial dielectric layer 152, essentially on the sides of the stack of layers forming the gate 120. They constitute the gate spacers 150 of the transistor.
[0050] Figure 2d illustrates the formation of the drain and source regions of a FDSOI type transistor. At the end of the last or only step of removing the modified dielectric layer 158, that is to say when it has been removed on all the horizontal surfaces, a so-called cleaning operation is carried out. "Wet cleaning" most often qualified by its English term "wet clean". As already noted previously wet etching and wet cleaning are similar operations that can be advantageously combined in a single operation. The source and drain electrodes 110 can then be formed. As already mentioned, the doping which will delimit the source and drain and therefore the length of the channel 132 can be done by ion implantation before does epitaxial growth on these areas in order to increase their section and decrease their resistance. If the doping is carried out before epitaxial growth, as shown in FIG. 2d, the method is said to be an English term "first extension" used to indicate that the extensions (of source and of drain under the spacers) are carried out first, that is, before epitaxial growth. In the opposite case, which is said to be "extension last", the epitaxial growth step is carried out directly without prior doping. The doping of the source / drain zones is done only after epitaxial growth of these zones. In the case of n-channel transistors (nMOS), the implanted dopants are typically arsenic (As) or phosphorus (P). For p-channel transistors (pMOS) the dopants are boron (B) or boron difluoride (BF2). The result is illustrated in FIG. 2d which shows the doped source / drain zones 114 before epitaxial growth of the raised source / drain zones 116.
[0051] Figure 3 illustrates the ion implantation profiles obtained for different species (Argon, Helium, Hydrogen) in a silicon nitride layer with an energy of 300 eV. In order to choose the best ion species for modifying a silicon nitride layer with a thickness of the order of 10-20 nm, the profile of a range of Rp ions is produced. range ") from a layer of silicon nitride (SiN) using typical plasma conditions, making it possible to compare different species of ions, in particular argon (curve 510), helium (curve 520) , hydrogen (curve 530), hydrogen associated with another component (layer 540). The SRIM-type Monte Carlo simulation code, developed by Ziegler, was used for the estimation and the elaboration of the Rp profile. In this example, a layer is considered. of silicon nitride with a thickness of about 50 nm. It is preferred that the ions (argon, helium, hydrogen, hydrogen associated with another component), having a kinetic energy of 300 eV, reach the surface of the plate (corresponding to the self - DC bias, measured at the surface of the plate (-300 V)). The simulated Rp profile, illustrated in FIG. 3, is estimated between 2 nm, 7 nm and 12 nm using, respectively, a plasma based on argon 510, helium and hydrogen 530. argon 520 or helium 520, the consumption of the silicon nitride layer is estimated at 2 nm.min-1 under the experimental conditions of this example. Therefore, the degradation of the SiN layer, generated by the ions, is suppressed because formed by the rate of argon sputtering. When a helium-520 plasma is used, the ion implantation is deeper. Thus, the degraded modified layer can be adjusted, taking into account the consumption of said layer. Advantageously, a hydrogen-based plasma 530 does not etch the silicon nitride layer. Therefore, the use of a hydrogen plasma provides a larger process window than helium, allowing more accurate and controlled modification of the depth of the modified silicon nitride layer. Based on these results, it appears that a plasma preferably based on hydrogen offers a particularly interesting means for precise control of the etching depth. Moreover, the impact of the polarization power on the thickness of the modified Si3N4 silicon nitride layer, after a hydrogen-based plasma (with a flow rate of 300 sccm), lasting 60 seconds, has been studied using a capacitively coupled plasma by varying the polarization power between 0 and 500W and with a pressure set at 50 mTorr. Hydrofluoric acid (HF) cleaning at 1 ° C / 0 was performed to remove the modified layer. It has been observed that an increase in polarization power causes an increase in the depth of the Si3N4 layer modification, which is correlated with higher ionic energy as a function of the polarization power.
[0052] Figures 4a, 4b and 4c illustrate an embodiment according to the prior art where a dielectric layer 152, formed on a substrate 142, is modified and then removed by hydrogen-based plasma etching only. FIGS. 5a, 5b and 5c illustrate an embodiment according to the invention where a dielectric layer 152, formed on a substrate 142, is modified and then removed by hydrogen-based plasma etching associated with another component X, playing the role of dissociation gas. In the context of the dopant of the present invention, it has been observed that there is a threshold value of the hydrogen dose from which the dielectric layer 152 is sufficiently modified to be attacked by means of a cleaning based on of hydrofluoric acid, for example, or at least, to be etched with a high selectivity to the unmodified material of the dielectric layer 152. If the material of the dielectric layer 152 is changed without the dose at least equal to this threshold dose, then the modified material of the dielectric layer 152 will not be etched or will be etched with a low selectivity vis-à-vis the unmodified material. However, with plasma implantation, the known solutions do not make it possible to reach this threshold dose for the maximum implanted depth. In fact, above the depth at which the threshold dose is reached, there is a depth of about 3 to 5 nm, which is implanted but without presenting an implanted dose equal to or greater than the threshold dose. This phenomenon is illustrated in FIGS. 4a to 4c. After implantation from a hydrogen-based plasma only, the dielectric layer 152, in this example formed based on silicon nitride, is implanted by light ions H, for example. However, and as shown on the implantation profile, the modified dielectric layer 158 is not uniformly implanted over the entire maximum depth Pmax of the dielectric layer 152. Thus, only a portion of the dielectric layer 152, 25 on a threshold depth Ps is implanted with a dose greater than or equal to the threshold dose sufficient to allow selective etching of the modified dielectric layer 158. The HF cleaning performed after implantation then makes it possible to remove only the portion of the modified dielectric layer 158 comprising a sufficient dose of light ions, that is the portion having a depth Pseule. After the HF cleaning, there remains a portion (depth Prest = Pmax-Pseuil) of the modified dielectric layer 158 comprising an insufficient dose of light ions and thus could not be removed by HF cleaning. An additional etch cycle will then be required to remove the remaining modified dielectric layer 158. In order to remove the residual layer 158 without additional etch cycle, it would have been necessary to have a Pseule equal to the thickness of the initial dielectric layer 152. Pmax would then have been thicker than the thickness of the initial dielectric layer 152. The Perst part was contained in layer 142. The latter was therefore implanted on a thickness corresponding to Perst which would have altered it. One way to increase the ion dose H in the silicon nitride layer is to increase the treatment time. The problem is the time consuming (> 600 s) important to saturate the hydrogen in the SiN layer. This solution, because of the significant time required, can not therefore be implemented from an industrial point of view (high cycle time, today the treatment time for etching a nitride spacer. being less than 60 s). A problem to be solved is the removal of the modified layer, since the modified layer is removed by HF cleaning from only a light ion dose threshold value implanted in the nitride layer. Therefore, the damage caused in the nitride layer by the HF cleaning is underestimated. Thus, if we target a 15nm thickness removal of silicon nitride layer thickness by 1% HF cleaning, the risk is to damage the underlying layer (Si or SiGe), since the depth of ion implantation will be deeper than 15 nm. Advantageously, the present invention allows a better control of the modification of the dielectric layer 152 (thanks to a higher dose of H implanted in the SiN layer) and thus by a reduction of the energy of the ions (reduction of the damages which can be affected the underlying layers Si / SiGe). FIGS. 5a to 5c illustrate an embodiment according to the present invention where the method makes it possible to modify the dielectric layer 152 so that the modified dielectric layer 158 is implanted on the depth Pmax with a dose greater than the threshold dose , thus allowing precise etching of the modified dielectric layer 158 over the entire depth Pmax.
[0053] In particular, it is observed that the use of a second component acting as a dissociation gas X (with X chosen for example from: Ar, He, Xe, N2) to the chemistry of the first component H2, advantageously allows to increase the concentration of light ions in the gas phase. Therefore, for the same implantation energy, the dose H implanted in the SiN layer is greater than that obtained from a plasma based on a single component H2 only. The profile Rp (associated with the implantation depth) for implantation from a plasma based on a gas comprising at least a first non-carbon gas component (H2) and a second component (X with X selected by example, among: Ar, He, Xe, N2) dissociation gas is close to that obtained for an implantation based on a single component H (see FIG. 3). Only the implanted dose will be larger in the case of a plasma comprising a first component H and a second component X compared to a plasma comprising only hydrogen, for example. In this way, the threshold dose of implantation can be reached at the maximum depth Pmax at which the light ions are implanted. There is no longer any implanted residual thickness whose dose is lower than the threshold dose. Thus, the consumption of the modified dielectric layer 158 by the HF cleaning is close to the implantation depth Pmax of the ions. Particularly advantageously, a better accuracy is obtained for etching the dielectric layer 152, without, however, damaging the underlying layer. FIG. 6 summarizes the steps of the method of the invention intended to form spacers and which do not induce any of the defects described in particular in FIGS. 1b, 1c and 1d for the production of transistors, for example FDSOI. After LPCVD has deposited a uniform dielectric layer 152 on all the surfaces of the devices being manufactured, said modified dielectric layer 158 is removed on the surfaces which are not intended to form the spacers. This removal comprises several steps, including steps 430, 440 and optionally step 420 beforehand.
[0054] Thus, optionally, anisotropic conventional dry etching 420 is carried out of the modified dielectric layer 158. This is typically carried out in a CH3F / 02 / He type plasma previously described. The etching of the spacers is thus, according to this optional and nonlimiting embodiment, carried out in two steps comprising: a first step called "main etching" and a second finishing step generally described as "over-etching" or the term English for "over etching (0E)" having the same meaning. It is during the over-etching step (steps 440) that the dielectric material of the modified dielectric layer 158 remaining on the horizontal surfaces will be removed after having modified (step 430) the layer dielectric 152 to avoid or limit the problems described in Figures lb to 1 d. In the context of specific implementations of the invention, it may be decided to maintain or not the main etching step 420, the following steps then apply either to the dielectric layer 152 as filed or on the remaining layer after a main etching has been previously performed as in the standard method of etching the spacers. As shown in Fig. 2b, the next step 430 is to anisotropically modify all or part 154 of the remaining dielectric layer 152 by light ion implantation. Advantageously, the second component interacts with the first component to dissociate the first component and promote the creation of light ions, thereby increasing the concentration of H ions and the dose.
[0055] Depending on the applications of the process of the invention, it may be preferred to use a plasma etcher for plasma implantation, in particular for the following reasons: the cost of the apparatus is lower, the manufacturing cycle times may be shorter since The main etching step 420 and the modifying step 430 of the dielectric layer 152 can then be carried out in the same apparatus without releasing the devices being manufactured. It will be noted in particular that the modification step 430 can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry, such as 3037715 using any type of burner, for example in an ICP reactor of the English "Inductively Coupled Plasma" that is to say "inductively coupled plasma", or in a CCP type reactor of the English "Capacitive Coupled Plasma" that is to say " capacitive coupling plasma which enables the energy of the ions to be controlled. It is also possible to use a type of so-called immersion plasma commonly used for practicing implantation of species on the surface of a device during manufacture. In order to choose the implantation parameters, the person skilled in the art, in order to determine the behavior of the material to be etched in the type of plasma etcher chosen, will preferentially proceed to "full-plate" tests in order to establish behavior curves. . He will deduce the parameters of the implantation, in particular the energy and the dose of ions, that is to say the exposure time, to use to reach the desired thickness of material to be modified.
[0056] The next step 440 is that in which etching of the modified layer or at least the modified thickness of the modified dielectric layer 158 is practiced by etching. To avoid the problems of the traditional methods of etching the spacers described in FIG. 1 to 1 d, it is necessary for the etching of the modified dielectric layer 158 to be as selective as possible with respect to the silicon, in particular so as not to attack the monocrystalline silicon of the source / drain zones with the disadvantages and consequences described above. . For this purpose a wet etching, for example, based on hydrofluoric acid (HF) (or phosphoric acid (H3PO4) for a dielectric layer 152 based on silicon nitride) which, as already mentioned, combines the shrinkage. the modified dielectric layer 158 with cleaning of the wafer containing the devices being manufactured, is advantageously used. This simplifies the process and saves time. The thickness of the modified dielectric layer 158 is typically in a range of values from 1 nm to a few tens of nm. Burning times can range from seconds to minutes. They are obviously directly dependent on the thickness that has been modified. By way of example, to remove a thickness of 15 nm from the modified dielectric layer 158, it takes about 60 seconds with a 1% solution of hydrofluoric acid (HF). An etching time of the order of 45 seconds is required with phosphoric acid (H3PO4). The etching of the modified dielectric layer 158 will also be as selective with respect to the silicon oxide in other process applications as that used for making the FDSOI transistor spacers where not useful. This is particularly the case for making three-dimensional transistors FinFET type. Selective dry etching with silicon and its oxide (Si / SiO2) may then also be practiced for this step of removing the modified dielectric layer 158. An alternative is therefore to perform a step of the dry removal of the layer. dielectric which has been modified by implantation, preferably hydrogen. The method is that described by H. Nishini and his coauthors in an English publication entitled "Damage-free selective etching of Si native oxides using NH3 / NF3 and SF6 / H2O down flow etching" published in the Journal of Applied Physics. volume 74 (2), July 1993. The principle of dry removal of the modified dielectric layer 158 is identical to that described in the above publication. The difference is that, in the case of the invention, no silicon oxide is etched but a modified dielectric layer 158 having undergone a hydrogen-based implantation. The mechanism is however the same and comprises the following steps which take place in a reaction chamber where a plasma is formed, that is to say in a plasma reactor. The thicknesses treated are typically between 1 nm and a few tens of nanometers. A first step 610 consists of generating the etching product in the plasma according to the following chemical reaction: NF3 + NH3 NH4F + NH4F.HF which reacts nitrogen trifluoride (NF3) with ammonia (NH3) or with Hydrogen (H2) to form hydrofluoric acid (HF). Etching is carried out during a second step 620, at a temperature of the order of 30 ° C. and more generally between 10 ° C. and 50 ° C., in the form of a salt formation according to the following chemical reaction : NH4F or NH4F.HF + SiNH (NH4) 2SiF6 (solid) + H2 during an operation which lasts between a few seconds and a few minutes and which is carried out under a pressure of between a few milli Torr and a few Torr. More precisely, this operation lasts between 20 seconds and 25 minutes and is carried out under a pressure of between 500 milli Torr and 3 Torr. The solid species which are formed during this operation are then sublimed 630 at a temperature above 100 ° C for a few tens of seconds according to the following reaction: (NH4) 2SiF6 (solid) SiF4 (g) + NH3 (g) + For example, to remove 10 nm of the modified dielectric layer 158, the nitrogen trifluoride (NF3) and ammonia (NH3) streams are 50 sccm and 300 sccm respectively at 30 ° C. 45 seconds for the salt forming step 620 which is followed by the sublimation step 630 which is carried out at 180 ° C for 60 seconds.
[0057] This embodiment makes it possible to obtain a very good selectivity of the etching of the modified nitride relative to the unmodified nitride and to the unmodified semiconductor material. In particular, this selectivity of the etching is much greater (typically a factor of at least 10) than that obtained with a solution of HF.
[0058] It will be noted here that there are etching reactors for performing implantation, for example hydrogen, from a plasma which can be followed, in the same system, by the removal of the modified dielectric layer 158 from the plasma. using a dry etching as described above. Thus, it is possible in this case to chain the cycles of modification and removal of the dielectric layer 152 selectively Si or SiO2, without venting the wafer. This is an additional incentive to use an etching reactor to implement the invention rather than using a standard implanter whenever possible.
[0059] As already mentioned, the modification operations 430 of the dielectric layer 152 and the recess 440 of the modified dielectric layer 158 may optionally be repeated 450 until the dielectric layer 158 has disappeared from all the horizontal surfaces. The following process steps are not different from the corresponding ones of the standard methods where the extensions of the source / drain zones 460 are possibly carried out by ion implantation of dopants before epitaxial growth of the raised source / drain 470 of FDSOI transistors. The following table gives typical conditions for implementing step 430 of modifying the dielectric layer 152 in the case of use of a standard plasma etching reactor. These conditions are largely dependent on the thickness to be modified in the dielectric layer 152. This is only a particular example of the implementation of step 430 for modifying the layer to be etched. As already mentioned, other means can be used for the implantation of light species, 15 H, used to modify the layer to be etched. In particular, it will be possible to use low or high density plasmas or plasmas by immersion. Advantageously, any type of dry etching device is potentially usable and especially those said ICP of the English "inductively coupled plasma" that is to say "inductively coupled plasma" or CCP of English "Capacitively coupled plasma", that is, "capacitively coupled plasma". These devices have the advantage of being able to achieve not only etchings, but also carbon deposits (C) in the same device.
[0060] 3037715 39 Burning Reactor: The values below apply more specifically to the ICP burner type, although any type of dry burning device is potentially usable. Thickness from 1 nm to several tens of nm, typically 15 nm modified: Chemistry based on the chemistry of a first component based on hydrogen (H2, HBr, NH3, SiH4) and a second component: gas allowing dissociation the first hydrogen-based ion component (H) selected from argon, nitrogen, xenon, helium. Flow 1 component 10 sccm - 1000 sccm (cubic centimeters per minute) Flow 2nd component 10 sccm - 1000 sccm Power of the source: 0 - 2000 W Power of 20 V - 500 V polarization: Frequency 100 Hz - 500 kHz Cycle 10% - 90% operating Pressure: 5 milli - 100 milli Torr Temperature: 10 ° C - 100 ° C Time: a few seconds to a few hundred seconds Figure 7 gives for the standard material used to form the spacers, that is to say the silicon nitride (SiN) in this example, the thicknesses of modified layers obtained according to different conditions of implementation of the step of implantation of light species in a standard plasma etching reactor. FIG. 7 gives the modified thickness as a function of the bias voltage (bias) in volts for an ICP type burner and under the following conditions, for FIG. 7: flow rate of the first component of 50 sccm; flow of the second sccm component; power of 10 the source 500 watts; pressure 10 milli Torr. For example, to modify a thickness of 10 nm of silicon nitride, the ionic energy (or bias voltage) required for a plasma formed from a first hydrogen-based component (H2) (curve 630) combined with a second helium-based component (He) is 150V for a time = 60 s. Note that the observed trend is the same if one replaces the second component with nitrogen (N2), xenon (Xe) or argon (Ar), for example. If hydrogen (H) alone is used (curve 610) to form the plasma, the required bias voltage is then 200 V for a time of 60 s. Advantageously, the dissociation of the first component by its interaction with the second component makes it possible to increase the concentration of hydrogen-based ions in the plasma, and therefore to increase the dose of implanted hydrogen. In another example, to modify a thickness of 16 nm of silicon nitride, the ionic energy (or bias voltage) required for a plasma formed from a first hydrogen-based component (H2) combined with a Second helium-based component (He) 630 is 300V for a time = 15 60 s. If only hydrogen (H) 610 is used to form the plasma, then the required bias voltage is 400 V for a period of 60 s. Particularly advantageously, by reducing the ion energy for a similar thickness of a silicon nitride layer removed by hydrofluoric acid (HF) cleaning, the faceting of the hard mask and the damage are reduced. can be generated on the Si / SiGe stack, compared to a hydrogen based plasma (H2) only. The invention is not limited to the only embodiments and embodiments described above, but extends to all embodiments in accordance with its spirit.

权利要求:
Claims (33)
[0001]
REVENDICATIONS1. A method of forming the spacers of a gate (150) of a field effect transistor (100), the gate (150) having a vertex and flanks and being located above a layer (146) in a conductive seed material, comprising a step (410) for forming a dielectric layer (152) covering the gate of the transistor, the method comprising: after the step of forming the dielectric layer (152), at least one modifying step (430) of said dielectric layer (152) by contacting the dielectric layer (152) with a plasma creating light anisotropic ion bombardment in a preferred direction parallel to sides of the gate (120), the conditions plasma, in particular the light ion energy and the implanted dose being selected so as to modify at least portions (158) of the dielectric layer (152) which are located on the top of the grid and on the side and other of the grid (120) and which perpendicular to the sidewalls of the grid (120) while maintaining unmodified portions of the dielectric layer (152) covering the sidewalls of the grid (120); the light ions being ions based on hydrogen (H); At least one step of removing (440) the modified dielectric layer (158) by selectively etching said modified dielectric layer (158) with respect to the layer (146) in a semi material -conductor and vis-à-vis the dielectric layer (152) unmodified; Characterized in that the plasma used in the step of modifying (430) the dielectric layer (152) is formed from a gas comprising at least a first non-carbon gas component whose dissociation generates said light ions and a second gaseous component comprising at least one species promoting dissociation of the first component to form said light ions, wherein the ratio of gas between the first component and the second component is between 1: 19 and 19: 1. 3037715 42
[0002]
2. Method according to the preceding claim wherein said ratio is between 1: 9 and 9: 1 and preferably between 1: 5 and 5: 1.
[0003]
3. Method according to any one of the preceding claims wherein the parameters of the implantation, in particular the implantation energy of the light ions from the first component and the implanted dose, are provided so that the modified dielectric layer (158 ) can be selectively etched on the layer (146) of a semiconductor material and vis-à-vis the unmodified dielectric layer (152).
[0004]
4. Method according to any one of the preceding claims wherein the first component is selected from hydrogen (H2), silicon nitride (SiH4), hydrogen nitride (NH3) or hydrogen bromide (HBr). ).
[0005]
5. Method according to any one of the preceding claims wherein the second component is selected from helium (He), nitrogen (N2), argon (Ar) or xenon (Xe).
[0006]
The method according to any one of the preceding claims wherein the dielectric layer (152) is formed of one or more dielectric materials whose dielectric constant k is less than or equal to 8 and preferably
[0007]
7. 7. Method according to the preceding claim wherein the dielectric layer (152) comprises a material having a dielectric constant of less than 4 and preferably less than 3.1 and preferably less than or equal to 2.
[0008]
The method of any of the preceding claims wherein the dielectric layer (152) is a silicon-based (Si) layer.
[0009]
The method of any of the preceding claims wherein the material of the dielectric layer (152) is selected from: SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, and SiO2. 3037715 43
[0010]
The method of any of the preceding claims wherein the dielectric layer (152) is a porous layer.
[0011]
The method of any one of claims 1 to 9 wherein the protective layer (152) is a non-porous layer. 5
[0012]
A method according to any one of the preceding claims, wherein the dielectric layer (152) is silicon nitride and the forming step (410) of the dielectric layer (152) comprises a step of depositing the dielectric layer. (152) during which a step of reducing the dielectric constant of the dielectric layer (152) is performed. 10
[0013]
13. Method according to the preceding claim wherein the step of reducing the dielectric constant of the dielectric layer (152) comprises introducing a porosity in the dielectric layer (152).
[0014]
The method of any one of the two preceding claims wherein the dielectric layer (152) is silicon nitride and the forming step (410) of the dielectric layer (152) comprises introducing precursors into the dielectric layer (152) during said step of the dielectric layer (152).
[0015]
15. A method according to the preceding claim wherein the dielectric layer is a silicon nitride layer and wherein the precursors are selected to form bonds reducing the polarizability of the dielectric layer (152).
[0016]
The method of any of the preceding claims wherein the step of modifying (430) the dielectric layer (152) made from a plasma changes the dielectric layer (152) continuously from the surface of the dielectric layer (152). the dielectric layer (152) and a thickness between 1 nm (nm) and 30 nm, preferably between 1 nm and 10 nm. 3037715 44
[0017]
17. A method according to any one of the preceding claims wherein the flow rate of the first component is between 10 and 1000 sccm (cubic centimeter per minute).
[0018]
18. A method according to any one of the preceding claims wherein the flow rate of the second component is between 10 and 1000 sccm.
[0019]
The method of any preceding claim wherein the step of modifying (430) the dielectric layer (152) is performed to provide a bias power or source power at a frequency of 100 Hz (Hertz) and 5 kHz, with a duty cycle of between 10% and 90%.
[0020]
The method of any of the preceding claims wherein the step of removing (440) the modified dielectric layer (158) is performed by selective wet etching at the layer (146) of a semiconductor material.
[0021]
A method according to any one of the preceding claims wherein the layer (146) of a semiconductor material is silicon and wherein the step of removing (440) the modified dielectric layer (158) is performed by etching selectively wet with silicon (Si) and / or silicon oxide (SiO 2) (121, 740).
[0022]
22. Method according to the preceding claim wherein the selective silicon etching is obtained using a solution based on hydrofluoric acid (HF).
[0023]
23. The method of any one of claims 1 to 19 wherein the removing step (440) is performed by selective dry etching at the layer (146) of a semiconductor material.
[0024]
24. The method according to the preceding claim wherein the layer (146) of a semiconductor material is silicon and wherein the step (440) of removing the modified dielectric layer (158) is performed by selective dry etching silicon (Si) and / or silicon oxide (SiO2).
[0025]
25. Process according to claim 1, in which the dry etching is carried out in a plasma formed in a confined chamber from a mixture of nitrogen trifluoride (NF3) and hydrogen (H2) or ammonia (NH3). ).
[0026]
26. A process according to any one of the preceding claims wherein the dry etching comprises: - an etching step (620) consisting of the formation of solid salts; a sublimation step (630) of the solid species.
[0027]
A method according to any one of the preceding claims comprising a single modification step (430) performed so as to modify the dielectric layer (152) throughout its thickness on all the surfaces parallel to the plane of a substrate (142) on which rests the grid (150) and not to modify the dielectric layer (152) throughout its thickness on the surfaces parallel to said preferred direction.
[0028]
28. A method according to any one of claims 1 to 26 comprising a plurality of sequences each comprising a modification step (430) and a withdrawal step (440), and wherein during at least one of the steps of modification (430), only a portion of the thickness of the dielectric layer (152) is changed.
[0029]
29. Method according to the preceding claim wherein the sequences are repeated (450) until the dielectric layer (152) disappears on all the surfaces parallel to the plane of a substrate (142) on which the grid (150) rests. .
[0030]
30. The method as claimed in claim 1, in which the gate (150) of the transistor is located on a stack of layers forming an elaborated silicon-on-insulator (SOI) substrate. 3037715 46
[0031]
31. A method according to any preceding claim wherein the etching is selective to silicon oxide (SiO2).
[0032]
32. The method according to any one of the preceding claims, wherein the light ions comprise hydrogen-based ions (H2) taken from: H, H +, H2 +, H3 +.
[0033]
33. The method as claimed in claim 1, in which the transistor is a FDSOI type transistor. 10

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2016-12-23| PLSC| Search report ready|Effective date: 20161223 |

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2017-06-27| PLFP| Fee payment|Year of fee payment: 3 |

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2018-06-27| PLFP| Fee payment|Year of fee payment: 4 |

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2020-06-30| PLFP| Fee payment|Year of fee payment: 6 |

优先权:

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FR1555667A|FR3037715B1|2015-06-19|2015-06-19|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|FR1555667A| FR3037715B1|2015-06-19|2015-06-19|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|

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EP16174868.6A| EP3107125B1|2015-06-19|2016-06-16|Method for forming spacers of a transistor gate|

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US15/185,446| US9947768B2|2015-06-19|2016-06-17|Method for forming spacers for a transistor gate|