• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention provides a complementary logic circuit which comprises a first logic cell composed of back gate transistors, the first cell having at least a first input for receiving at least a first input signal and having an output for outputting a first signal output, and a second logic cell complementary to the first cell, composed of backgate transistors, the second cell having as many inputs as the first cell, each input being able to receive an input signal complementary to the respective input signal the first cell, the second cell having an output for providing a second output signal complementary to the first output signal of the first cell. The circuit is arranged so that the first output signal of the first cell is applied to the rear gate of each transistor of the second cell, and the second output signal of the second cell is applied to the rear gate of the second cell. each transistor of the first cell.
    公开号:FR3034930A1
    申请号:FR1553096
    申请日:2015-04-10
    公开日:2016-10-14
    发明作者:Gilles Fernand Jacquemod；Foucauld Emeric De；Alexandre Benjamin Fonseca；Yves Leduc；Philippe Bernard Pierre Lorenzini
    申请人:De Nice, University of；Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The invention lies in the field of integrated circuits, and in particular that of multi-gate circuits of FinFET or FDSOI type. State of the art Each year, new microelectronic technologies are available, bringing innovations and improvements to our daily lives. All this is possible thanks to circuits with higher and higher performances and more and more complex functions. This increase in performance has been made possible by the miniaturization of the elementary components, namely the transistors. Current technologies make it possible to design chips having transistors with atomic dimensions. As the size of the transistors is reduced to around ten nanometers, the variation of the dopants in the channel region directly causes a variation of the threshold voltage VTH between two identical and adjacent transistors on the same chip. New MOSFET transistor structures have recently been proposed to reduce component variability below 22nm, some using FinFet technology that uses multi-gate non-planar transistors, and others using FDS01 "Fully Depleted Silicon" technology. On Insulator. FDS01 (Fully Depleted Silicon on Insulator) technology is based on a thin layer (5 to 20nm) of silicon on a thin layer (5 to 50nm) of buried oxide 2 3034930 (Buried Oxide -B0x) . The transistors are built on the thin layer of undoped silicon (depleted in charges) which has several advantages over Bulk. As the channel is completely depleted, the random variation of the dopants that touched the Bulk CMOS is reduced, which improves the lower VDD performance. The FDS01 claims an improvement in the ratio Consumption / Performance of the order of 30 to 40% against CMOS Bulk 20nm. However, the variability of the manufacturing processes remains constraining for the integrated circuits and introduces mismatches of the transistors. Thus on the same chip, transistors assumed identical will not have the same characteristics. This difference in characteristics may introduce malfunctions of the final circuit, which may then no longer verify for certain applications the specifications required. In the specific case of analog electronics, some cells require that the transistors be identical, that is to say paired. Circuit calibration techniques have become necessary for a majority of applications. However, the known approaches for implementing the calibration lead to an increase in the surface of the final circuit by adding electronics, therefore to an increase in consumption and to an increase in overall cost. Also a problem to be solved is that of proposing a circuit calibration solution which does not increase the circuit surface, and which has an immunity to the variability of the processes.
    [0002] The FDS01 technology which does not need doping to control the threshold voltage, and which also offers the transistors a rear gate 3034930, makes it possible to propose a calibration solution based on the control of the back gate of the transistors. However, in the case of differential analog circuits, such as current mirrors or differential pairs, it is important that the transistors have the same characteristics. Similarly, to make oscillators, including ring oscillators based on inverters, it is also important that the transistors (and inverters) have the same characteristics to reduce the jitter phenomenon ("jitter" in English). there is no such thing as a simple solution in FDSOl technology known to this problem. There is then the need for a solution that overcomes the disadvantages of known approaches. The present invention meets this need. This invention applies to all digital circuits using complementary logic. SUMMARY OF THE INVENTION According to one embodiment, a complementary logic circuit comprises: a first logic cell composed of back gate transistors, the first cell having at least a first input for receiving at least a first input signal and having an output for outputting a first output signal; and a second complementary logic cell of the first cell, composed of backgate transistors, the second cell having as many inputs as the first cell, each input being able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for outputting a second output signal complementary to the first output signal of the first cell. The circuit is characterized in that said first output signal of the first cell is applied to the rear gate of each transistor of the second cell, and that said second output signal of the second cell is applied to the second cell. back gate of each transistor of the first cell. In one embodiment, the first cell is a first CMOS inverter capable of delivering an inverse output of its input, and the second cell is a second CMOS inverter adapted to receive a complementary input from the input of the first inverter and to be delivered. an output complementary to the output of the first inverter, the output of the first inverter being applied to the rear gate of the NMOS and PMOS transistors of the second CMOS inverter and the complementary output of the second inverter being applied to the rear gate of the NMOS and PMOS transistors of the first CMOS inverter. In a variant, the first inverter and the second inverter are connected directly between a high voltage and a low voltage. In another variant, the first inverter and the second inverter comprise a current generator between the PMOS transistor and a high voltage.
    [0003] According to another variant, the first inverter and the second inverter comprise a current generator between the NMOS transistor and a low voltage.
    [0004] In one embodiment, the first cell comprises CMOS transistors able to perform one of the functions (AND, NAND, OR, NOR) with two inputs (A, B) and the second cell comprises CMOS transistors adapted to perform one of the same functions (AND, NAND, OR, NOR) with two complementary inputs (A, e) of the first cell.
    [0005] Advantageously, a voltage controlled oscillator comprising an even number of circuits of the invention may be implemented. In one implementation, such an oscillator may comprise four identical outputs of the same amplitude, of the same frequency and of 5 regularly spaced phases. Advantageously, the transistors are transistors in silicon technology completely depleted on "FDSOI" insulator or "FinFet" double gate transistors.
    [0006] DESCRIPTION OF THE FIGURES Various aspects and advantages of the invention will appear in support of the description of a preferred embodiment of the invention, but not limiting, with reference to the figures below: FIG. 1 is a representation in conventional logic of an inverter and its implementation using the different possible polarizations of the back gate of the two transistors component; FIG. 2 is a representation in complementary logic zo of an inverter cell according to one embodiment of the invention; Figure 3 shows a preferred implementation of the inverter cell of Figure 2 according to one embodiment; Figure 4 shows an alternative implementation of the inverter cell of Figure 2 in another embodiment of the invention; Figure 5 shows a ring oscillator in one embodiment of the invention; FIG. 6 shows an exemplary implementation of a two-input NAND function according to one embodiment of the invention; Figures 7a to 7e illustrate exemplary implementations of logic functions according to embodiments of the invention. DETAILED DESCRIPTION OF THE INVENTION Reference is made to FIG. 1, in which a conventional logic representation 100 of an inverter circuit having an input 'I = A' and delivering a complementary output `S = A 'is shown. Some nonlimiting examples of implementations of such an inverter in a back gate transistor technology, such as FDS01 CMOS technology are illustrated, where the rear gates of the transistors can be connected to the same voltages (102, 104) or different voltages (106, 108). FIG. 2 illustrates, in a representation of an inverter circuit, the general principle of the invention which is to symmetrize the operation of the circuit according to a complementary logic. The inverter circuit 200 of the invention comprises a complementary input and a complementary output. The input of the circuit receives a first signal 'A' and a second signal 'A' complementary to the first signal. The complementary output 20 delivers a first signal `S = À` inverse of the first input signal 'A', and a second complementary signal` S = A ', inverse of the second input signal. The transistors of the circuit are of the type having a back gate, in SOI technology, FDSOI, or CMOS with bulk, double-well or triple-well. The transistors may also be of the double gate type in FinFet technology, or any other technology providing on a transistor a gate for controlling the threshold voltage of the transistor. According to the principle of the invention, the characteristics of the transistors are modified according to the characteristics of the output of the circuit by modifying the value on the back gate or the double gate of the transistors. The output signal is a complementary signal balanced by a control of the threshold voltages of the transistors.
    [0007] FIG. 3 shows an exemplary implementation of the inverter circuit of FIG. 2 in CMOS FDSOI technology. In general, the circuit 300 comprises a first cell 300-1 for receiving on a first input a first input signal 'A' and delivering on a first output a first output signal 'S'. It comprises a second cell 300-2 in complementary logic for receiving on a second input a second input signal 'A' complementary to the first input signal, and delivering on a second output, a second output signal 'S' which is complementary to the first output signal of the first cell. Since the transistors of the first and second cells have rear gates, the novel and inventive principle of the present invention is that the output of each cell is looped back to the rear gate of all the transistors performing the logic function of the other cell. Thus, the output of the first cell is applied to the rear gates of the transistors of the second cell, and the output of the second cell is applied to the back gate of the transistors of the first cell. There is then a symmetrization of the two stages of the inverter circuit that occurs and because of this, the effects related to the variability of the process will diminish.
    [0008] In the detail of the implementation of FIG. 3, the first cell 300-1 of the inverter 300 comprises an NMOS type transistor 302, a PMOS type transistor 304, an input 306 for receiving a signal of value. A 'and an output 308 for outputting an inverted value signal' To '. In the example described, the transistors (302, 304) are of the FDS01 type and comprise a rear gate which is connected to the output 318 of the second cell. In a symmetrical manner, the second cell 300-2 of the inverter 300 comprises an NMOS transistor 312, a PMOS transistor 314, an input 316 to receive a signal of value 'A' complementary to the value 'A' of the first cell, and an output 318 for outputting an inverted value signal 'A', which is complementary to the output value of the first cell. Similar to the first cell, the transistors (312, 314) are of FDS01 type and include a back gate which is connected to the output 308 of the first cell. In operation, when the output `S 'of the inverter of the second cell 300-2 switches from top to bottom (ie the input has switched from bottom to top, from Vss to VDD), this is the NMOS transistor 312 which drives. During the same time the output 'S' of the inverter of the first cell switches from bottom to top, and it is the PMOS transistor 304 which drives. In fact, advantageously by looping the outputs of each cell on the back gate of the transistors of the other cell, the slowest cell will slow the faster and the faster will accelerate the slowest. Thus propagation times "tpHL" and "tpui" within the circuit 300 will balance (offset or calibrate). It will be understood by those skilled in the art that the transistors are connected to high and low voltage sources (VDD, Vss) that are not useful to further describe, and that different implementations of the described example may be performed according to that the transistors are connected directly to the supply voltage or via a current generator for example as illustrated in FIG. 4. It should be noted that the elements identical to those of FIG. 3 retain the same references, like the transistors (302, 304) and (312, 314) of each inverter cell. FIG. 4 shows an inverter circuit in one embodiment of the invention comprising a current generator controlled in each inverter cell. The current generator is composed of a transistor (402, 404) placed between the PMOS transistor (304, 314) of each cell and the VDD power supply and controlled by a defined voltage Vtunel '. In an implementation variant, a second current generator may be added by a transistor placed between the NMOS transistor (302, 312) and the low voltage VSS.
    [0009] Thanks to the rear gate of the transistors mounted as a current generator, it is possible for a finer adjustment or an additional calibration to polarize this electrode via a defined voltage Vtune2 '. Advantageously, since the invention proposes the production of complementary logic gates, such a device makes it possible to provide a ring oscillator circuit whose duty cycle will tend towards 50%, which is very important for a number of applications in telecommunications. Still advantageously, the principle of the present invention makes it possible to produce voltage controlled oscillator circuits (VCO) having an even number of inverters as illustrated in FIG. 5, where the control of the VCO corresponds to the voltage Vtunel '. In an advantageous implementation, such an oscillator with an even number of inverters makes it possible to produce a quadrature oscillator (QVCO) having 4 outputs of the same amplitude and same frequency, but at different regularly distributed phases (0 °, 90 °, 180 °). ° and 270 °). This quadrature VCO topology - QVCO - is advantageously used in radiofrequency receiver architectures with image frequency rejection. More generally, the principle of the invention can be extended and applied to all digital cells using complementary logic. FIG. 6 shows an exemplary implementation of a two-input NAND function (NAND2) according to an embodiment of the invention in FDSOI technology. The circuit 600 is composed of a first cell 600-1 and a second complementary cell 600-2. Each cell includes transistors for performing a two-input NAND function. According to the principle of the invention, the output of each cell is looped back to the back gate of the transistors of the other cell, thus making the cells more robust to the technological variations of the manufacturing process and to the hazards of operation (in particular for the synthesis asynchronous circuits).
    [0010] The first NAND cell comprises a first input 602 for receiving a first signal 'A' applied to the input of two NMOS transistors 604 and PMOS 606. The first NAND cell further comprises a second input 608 for receiving a second signal 'B' applied to the input of two NMOS transistors 610 and PMOS 612. The second cell 600-2 carrying the complementary NAND gate 5 comprises a first input 614 for receiving a first signal 'A' complementary to the first signal of the first cell, and applied to the input of two NMOS transistors 616 and PMOS 618. The second cell also comprises a second input 620 for receiving a second signal 'e' complementary to the second signal 'B' of the first cell, and applied to the input of two NMOS transistors 610 and PMOS 612. The first NAND cell 600-1 provides an output signal 'S' corresponding to the NAND function of the inputs 'A' and 'B'. The second complementary cell 600-2 makes it possible to deliver an output signal `S 'corresponding to the NAND function of the inputs' To' and 'e'. The output 'S' of the first cell is applied to the back gate of all the transistors (616, 618, 622, 624) of the second cell, and the output 'S' of the second cell is applied to the back gate of all the transistors (604, 606, 610, 612). of the first cell. The logic output of the differential circuit NAND2 according to the principle of the invention is then: {S,} = {A, A}. {B + S = AB (NAND) and S = AB = A + B (NOR) The FIGS. 7a to 7e illustrate examples of implementations of complementary logic circuits according to embodiments of the invention. Figure 7a illustrates a differential circuit consisting of two symmetrical cells for performing a two-input AND function. Figure 7b illustrates a differential circuit consisting of two symmetrical cells for performing a NOR function with two inputs. Figure 7c illustrates a differential circuit consisting of two symmetrical cells for performing a two-input OR function. The cells of FIGS. 7d and 7e, 3034930 perform other logic functions with two inputs. Thus, the present description illustrates a preferred implementation of the invention, but is not limiting. Some examples have been described to allow a good understanding of the principles of the invention, and a concrete application, but they are in no way exhaustive and should allow the skilled person to make modifications and implementation variants. keeping the same principles.
    权利要求:
    Claims (5)
    [0001]
    REVENDICATIONS1. A differential logic circuit comprising: a first logic cell composed of backgate transistors, the first cell having at least a first input for receiving at least a first input signal (A) and having an output for outputting a first input signal; exits) ; and a second complementary logic cell of the first cell, composed of backgate transistors, the second cell having as many inputs as the first cell, each input being able to receive an input signal (A) complementary to the input signal respective of the first cell, the second cell having an output for providing a second output signal (S) complementary to the first output signal (S) of the first cell; the circuit being characterized in that said first output signal (S) of the first cell is applied to the rear gate of each transistor of the second cell, and in that said second output signal (S) of the second cell is Applied to the back gate of each transistor of the first cell.
    [0002]
    2. The circuit of claim 1 wherein the first cell is a first CMOS inverter adapted to output an inverse output of its input, and the second cell is a second CMOS inverter adapted to receive a complementary input of the input of the first. inverter and to deliver a complementary output of the output of the first inverter, the output of the first inverter being applied to the rear gate 30 of the NMOS and PMOS transistors of the second CMOS inverter 3034930 13 and the complementary output of the second inverter being applied to the rear gate NMOS and PMOS transistors of the first CMOS inverter.
    [0003]
    3.
    [0004]
    The circuit of claim 2 wherein the first inverter and the second inverter are directly connected between a high voltage and a low voltage. The circuit of claim 2 wherein the first inverter and the second inverter comprise a current generator between the PMOS transistor and a high voltage. The circuit of claim 2 or 4 wherein the first inverter and the second inverter comprise a current generator between the NMOS transistor and a low voltage. A voltage controlled oscillator comprising an even number of circuits according to any one of claims 1 to
    [0005]
    5. The oscillator of claim 6 comprising four identical outputs of the same amplitude, the same frequency and evenly distributed phases. The circuit of claim 1 wherein the first cell comprises CMOS transistors capable of performing an AND function of two inputs (A, B) and the second cell comprises CMOS transistors capable of performing a function of two complementary inputs. (A, B) of the first cell. 9. The circuit of claim 1 wherein the first cell comprises CMOS transistors capable of performing a NAND function of two inputs (A, B) and the second cell comprises CMOS transistors capable of performing a NAND function of the two complementary inputs ( A, B) of the first cell. 10. The circuit of claim 1 wherein the first cell comprises CMOS transistors capable of performing a two-input OR function (A, B) and the second cell comprises CMOS transistors capable of performing an OR function of the two inputs. complementary (A, B) of the first cell. 11. The circuit according to claim 1, in which the first cell comprises CMOS transistors able to perform a NOR function of two inputs (A, B) and the second cell comprises CMOS transistors able to perform a NOR function of the two complementary inputs. (A, B) of the first cell. 12. The circuit of any one of claims 1 to 5 and 8 to 11 wherein the transistors are fully depleted silicon transistor transistors on "FDS01" insulator. The circuit of any one of claims 1 to 5 and 8 to 11 wherein the transistors are double gate "FinFet" transistors.
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    法律状态:
    2016-04-29| PLFP| Fee payment|Year of fee payment: 2 |
    2016-10-14| PLSC| Publication of the preliminary search report|Effective date: 20161014 |
    2017-04-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-04-26| PLFP| Fee payment|Year of fee payment: 4 |
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    2020-04-30| PLFP| Fee payment|Year of fee payment: 6 |
    2022-01-07| ST| Notification of lapse|Effective date: 20211205 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1553096|2015-04-10|
    FR1553096A|FR3034930B1|2015-04-10|2015-04-10|METHOD AND DEVICE FOR SELF-CALIBRATING MULTI-GRID CIRCUITS|FR1553096A| FR3034930B1|2015-04-10|2015-04-10|METHOD AND DEVICE FOR SELF-CALIBRATING MULTI-GRID CIRCUITS|
    US15/094,163| US10164573B2|2015-04-10|2016-04-08|Method and device for auto-calibration of multi-gate circuits|
    EP16164459.6A| EP3079260B1|2015-04-10|2016-04-08|Method and device for self-calibration of multi-gate circuits|
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