• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    The invention relates to a method for manufacturing light-emitting diode optoelectronic devices (10) comprising the following steps: a) forming a first integrated circuit chip (11) comprising light-emitting diodes (16); b) bonding a second integrated circuit chip (12) to a first face (13) of the first chip; c) reducing the thickness of the first chip on the opposite side to the first face to form a second face (15) opposite the first face; d) sticking to the second face a cover (14) comprising a silicon wafer provided with recesses facing the light-emitting diodes; e) reducing the thickness of the second chip; f) reducing the thickness of the silicon wafer before step d) or after step e), each recess being filled with a photoluminescent material; and g) cutting the structure obtained in step f) into several separate optoelectronic devices.
    公开号:FR3033939A1
    申请号:FR1552348
    申请日:2015-03-20
    公开日:2016-09-23
    发明作者:Hubert Bono；Ivan-Christophe Robin
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The present application relates to an optoelectronic device comprising at least one light-emitting diode, in particular for lighting systems, and its method of manufacture. BACKGROUND OF THE PRIOR ART In general, the manufacture of a light emitting diode optoelectronic device comprises the fabrication of light-emitting diodes on a substrate which is then cut into individual chips. Each individual chip is then mounted on a support. Various elements may, in addition, be fixed to the individual chip or to the support for carrying out various functions, in particular the transformation of the electromagnetic radiation emitted by the light-emitting diode into a radiation having the desired spectrum, the evacuation of the heat supplied by the electroluminescent diode, the electrical control of the light emitting diode, the electrical connection of the optoelectronic device to an external system and the protection of the device vis-à-vis the external environment. The various known methods for manufacturing, encapsulating and mounting light-emitting diodes involve the implementation of a very large number of steps, some of which are complex, involving, in particular, postponements of chips and the use of multiple handles. SUMMARY An object of an embodiment is to overcome some or all of the disadvantages of light emitting diode optoelectronic devices and their previously described fabrication methods. Another object of an embodiment is that the manufacture and encapsulation of the light-emitting diodes 10 are made collectively by a method which is particularly simple to implement and which ensures that the mounting of the light-emitting diodes can be done in optimal conditions of heat dissipation. Thus, an embodiment provides a method of manufacturing light-emitting diode optoelectronic devices comprising the steps of: a) forming a first integrated circuit chip comprising light-emitting diodes; b) pasting a second integrated circuit chip to a first face of the first integrated circuit chip; c) reducing the thickness of the first integrated circuit chip from the opposite side to the first face to form a second face opposite to the first face, the first integrated circuit chip having, after step c), a first thickness between 100 nm and 50 μm; d) sticking, on the second face, a cover comprising a silicon wafer provided with recesses facing the light-emitting diodes, the cover possibly comprising, in addition, a transparent plate fixed to the silicon wafer; E) reducing the thickness of the second integrated circuit chip, the second integrated circuit chip having a second thickness less than or equal to 150 gm after step e); f) reducing the thickness of the silicon wafer before step d) or after step e), the thickness of the cover, optionally comprising the transparent plate, being greater than or equal to 100 gm after the step f), each recess being filled with a photoluminescent material; and g) cutting the structure obtained in step f) into a plurality of separate optoelectronic devices each comprising at least one of the light-emitting diodes. According to one embodiment, the light emitting diodes have a mesa structure. According to one embodiment, the recesses are filled with the photoluminescent material before step d). According to one embodiment, the recesses are non-through before step f), and are through after step f), the method further comprising the step of filling each recess of the photoluminescent material after the step f). According to one embodiment, steps b), c) and d) are successive. According to one embodiment, step a) comprises forming the light-emitting diodes on a substrate and step c) comprises removing, partially or completely, the substrate. According to one embodiment, the second integrated circuit chip is attached to the first integrated circuit chip by direct bonding and is electrically connected to the light emitting diodes. An embodiment also provides an optoelectronic device comprising: a first integrated circuit chip having first and second opposing faces having a thickness of between 100 nm and 50 gm and including at least one light emitting diode; a cover fixed to the first face, the cover comprising at least one through recess delimited by a silicon frame and containing a block of a photoluminescent material, the cover further comprising, optionally, a transparent plate, the thickness of the cover , optionally comprising the transparent plate, being greater than or equal to 100 gm; and a second integrated circuit chip attached to the second face and having a thickness less than or equal to 150 pin. According to one embodiment, the light emitting diode has a mesa structure.
    [0002] According to one embodiment, the photoluminescent block is laterally surrounded by a reflecting wall. BRIEF DESCRIPTION OF THE DRAWINGS These features and advantages, as well as others, will be set forth in detail in the following description of particular embodiments made without implied limitation in connection with the accompanying figures in which: FIGS. 1-7 are partial sectional and schematic views of embodiments of an optoelectronic device; Figures u. at 8N are sectional, partial and schematic views of structures obtained at successive steps of an embodiment of a method for manufacturing the optoelectronic device shown in FIG. 1; and Figures 9A. to 9D are sectional, partial and schematic views of structures obtained at successive stages of an embodiment of a method of manufacturing the optoelectronic device shown in FIG. 7. Detailed Description For the sake of clarity, the same elements have been designated with the same references in the various figures and, moreover, as is customary in the representation of integrated circuits, the various figures are not drawn to scale. In addition, in the remainder of the description, the terms "substantially", "about" and "approximately" mean "within 10%". In addition, only the elements useful for understanding the present description have been shown and are described. In particular, the polarization means of a light emitting diode of an optoelectronic device are well known and are not described.
    [0003] In the rest of the description, the "active zone" of a light-emitting diode is the region of the light-emitting diode from which the majority of the electromagnetic radiation supplied by the electroluminescent diode is emitted. FIG. 1 represents an embodiment of an optoelectronic device 10 comprising a light-emitting diode. The device 10 comprises a first integrated circuit chip 11, a second integrated circuit chip 12 fixed to a first face 13 of the chip 11 and a cover 14 fixed to a second face 15 of the chip 11, opposite to the first face 13 In operation, the device 10 is adapted to emit electromagnetic radiation from the optoelectronic chip 11 through the cover 14, that is to say downwards in FIG. 1. The first integrated circuit chip 11 comprises at least one 16 and is called optoelectronic circuit or optoelectronic chip in the following description. In FIG. 1, the optoelectronic device represented comprises only one light-emitting diode 16. The second integrated-circuit chip 12 provides the connection between the optoelectronic chip 11 and a support, not shown, of the device placed on the side of the second chip. integrated circuit 12 opposite to that on which the optoelectronic chip 11 is mounted. The second integrated circuit chip 12 may comprise electronic components, not shown, in particular transistors, used for the control or protection of the light-emitting diode 16 of the first integrated circuit chip 11. The second integrated circuit chip 12 is called interposer or control chip in the following description. The optoelectronic chip 11 is fixed to the interposer 12. Depending on the type of fixing, inserts may possibly be present between the optoelectronic chip 11 and the interposer 12. The thickness of the optoelectronic chip 11 is between 100 nm and 50 nm. pine, preferably between 1 gm and 30 gm, for example about 10 gm. The thickness of the interposer 12 is less than or equal to 150 μm, preferably between 1 μm and 150 μm, more preferably between 10 μm and 100 μm, for example approximately 30 μm. The cover 14 may comprise a transparent plate 5, for example a glass plate. The thickness of the cover 14, including any transparent plate, is greater than or equal to 100 pin. According to one embodiment, the light-emitting diode 16 comprises a stack of semiconductor layers 10 each containing at least one III-V compound. According to a first example, the light-emitting diode 16 has the structure described in the patent application FR14 / 50077. In a second example, the light emitting diode 16 has the structure described in the publication titled "III-nitride micro-emitter arrays: development and applications" in the names of Z.Y. Fan, J.Y. Lin, and H.X. Jiang (Journal of Physics D: Applied Physics, Volume 41, Number 9, pages 094001, 2008). According to one embodiment, the light-emitting diode 16 has a two-dimensional structure, also called a mesa structure, insofar as it is formed by a stack of substantially planar semiconductor layers and comprises an active area which projects above the substrate following a step of etching its flanks. According to one embodiment, the optoelectronic chip 11 comprises a semiconductor layer 18 delimited by the face 15 and an opposite face 20. The light-emitting diode 16 rests on the face 20 of the layer 18. The layer 18 is, for example, a highly doped semiconductor layer of a first type of conductivity, for example of N-type. The layer 18 is, for example, to a III-V compound, especially a III-N compound. Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. The thickness of the layer 18 may be between 500 nm and 50 μm, preferably between 1 μm and 6 μm. The face 15 may comprise embossed patterns 21 which improve the extraction of the light emitted by the light-emitting diode 16. The maximum thickness of the relief patterns 21 may be greater than 500 rua. The density of the patterns may be greater than 107 / cm 2. The light-emitting diode 16 comprises a stack 5 of semiconductor layer portions comprising, from the bottom upwards in FIG. 1: a semiconductor portion 24 doped with the first type of conductivity, for example doped with N-type, in contact with the face 20 of the layer 18; An active area 26; and a doped semiconductor portion 28 of a second conductivity type opposite to the first conductivity type, for example doped P-type. According to another embodiment, the semiconductor layer 18 may not be present. According to one embodiment, the active zone 26 and the semiconductor portions 24 and 28 each mainly comprise at least one III-V compound, especially a III-N compound. Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions. The active zone 26 and the semiconductor portions 24 and 28 may each comprise a dopant. Active zone 26 may comprise a single quantum well. It may then comprise a semiconductor material different from the semiconductor material forming the semiconductor portions 24 and 28 and having a band gap lower than that of the semiconductor portions 24 and 28. The active area 26 may comprise multiple quantum wells. It then comprises a stack of semiconductor layers forming an alternation of quantum wells and barrier layers. The thickness of the semiconductor portion 24 may be between 0.1 gm and 20 pin. The thickness of the semiconductor portion 28 may be between 50 nm and 20 μm. The thickness of the active zone 26 may be between 10 nm and 500 nm. The width of the light emitting diode 16 may be less than 30 μm, preferably 5 μm to 30 μm.
    [0004] For each light-emitting diode 16, an electrically conductive portion 30 covers the semiconductor portion 28. The conductive portions 30 are, for example, aluminum or silver. The thickness of each conductive portion 30 is, for example, between 3 nm and 400 nm. The optoelectronic chip 11 comprises a connection element 32 which electrically connects the conductive portion 30 to the interposer 12. The interposer 12 comprises a conductive portion 34 in contact with the connection element 32. The lateral flanks of the semiconductor portion 28, 15 of the active zone 26 and at least a portion of the semiconductor portion 24 are covered with an insulating portion 36. The thickness of the insulating portion 36 may be chosen so that the insulating portion 36 has a current acceptable leakage.
    [0005] The optoelectronic chip 11 comprises a connection element 37 which electrically connects the layer 18 to a conductive portion 39 of the interposer 12. The connection element 37 is electrically insulated from the semiconductor portion 28 and the active zone 26 by the Insulating portion 36. The connecting element 37 is in contact with the face 20 of the layer 18. The connection element 37 may, in addition, be in contact with a part of the semiconductor portion 24. The elements of FIG. 32 and 37 are electrically isolated from each other by an insulating region 38 which extends the insulating portion 36. The connection elements 32, 37 and the insulating region 38 delimit the face 13 of the optoelectronic chip 11. cover 14 comprises at least one photoluminescent block 40 on the face 15 of the layer 18 vis-à-vis the light-emitting diode 16, a single photoluminescent block 40 being shown in FIG. 1. The photoluminescent block 40 is surrounded 3033939 9 of a frame 42 resting on the face 15 of the layer 18. The frame 42 may be made of an insulating material, semiconductor or conductor. For example, the frame 42 is made of silicon. The thickness of the photoluminescent block 40 is between 50 μm and 200 μm, preferably between 75 μm and 150 μm, for example about 100 μm. The width of the photoluminescent block 40 is between 20 μm and 200 μm, preferably between 75 μm and 150 μm, for example about 100 μm. The photoluminescent block 40 may comprise a photoluminescent material, including, for example, a matrix in which phosphors, for example yttrium aluminum garnet (YAG), are activated. trivalent cerium ion, also called YAG: Ce or YAG: Ce3 +. According to one embodiment, the side walls of the frame 42 oriented towards the photoluminescent block 40 are covered with a coating 44 adapted to reflect the radiation emitted by the photoluminescent blocks 40. The coating 44 is, for example, a film of Aluminum having a thickness of between 10 nm and 20 preferably the interposer 12 is mainly of a material that is a good conductor of heat. According to one embodiment, the interposer 12 mainly comprises a semiconductor substrate. The interposer 12 may comprise conductive portions 46 on the opposite side of the optoelectronic chip 11 to allow the mechanical and / or electrical connection of the interposer 12 to a carrier, not shown. According to one embodiment, the interposer 12 comprises a connecting element, not shown, connecting the conductive portion 34 to one of the conductive portions 46 and a connecting element, not shown, connecting the conductive portion 34 to another Conductive portions 46. According to one embodiment, the interposer 12 comprises a semiconductor substrate and the connecting elements comprise conductive vias, isolated from the substrate, and passing through the substrate over its entire thickness. According to another embodiment, the interposer 12 comprises electronic components, in particular transistors, for performing particular functions, for example the control of the light-emitting diode 16 or the protection of the electroluminescent diode 16 against electrostatic discharges. .
    [0006] FIG. 2 shows another embodiment of an optoelectronic device 50 in which the connecting element 37 is replaced by conductive fingers 52, three fingers 52 being shown in FIG. 2, which extend through the portion semiconductor 28, the active zone 26 and a portion 10 of the semiconductor portion 24. Each finger 52 is surrounded by an insulating sheath 54 which electrically isolates it from the semiconductor portion 28 and the active zone 26. The end of each finger 52 is in contact with the semiconductor portion 24. FIG. 3 shows another embodiment of an optoelectronic device 55 in which the connection between the optoelectronic chip 11 and the interposer 12 is made by conducting balls. Electrically 56. Preferably, the gap 57 between the optoelectronic chip 11 and the interposer 12 is, furthermore, filled with an electrically insulating material but a good conductor of the chopper. their. The filler material may be graphite or diamond powder. Preferably, the maximum thickness of the gap 57 is less than 5 μm, preferably less than 2 μm. In the previously described embodiments, the optoelectronic device comprises a single light emitting diode. Alternatively, the optoelectronic device may include a plurality of light-emitting diodes that may be connected in series and / or in parallel. FIGS. 4 and 5 illustrate embodiments in which the optoelectronic device comprises several light-emitting diodes 16. FIG. 4 represents an embodiment of an optoelectronic device 58 comprising three light-emitting diodes 16 connected in series, additional connection elements 59 for connecting between them two adjacent LEDs 16. FIG. 5 shows another embodiment of an optoelectronic device 60 comprising four light-emitting diodes 16 connected in parallel. In FIG. 5, the conductive portions 39 associated with each light-emitting diode 16 are not visible. FIG. 6 represents another embodiment of an optoelectronic device 61 in which the lateral dimensions of the interposer 12 are greater than those of the optoelectronic chip 11. The electrical connection of the interposer 12 to another electronic device, for example according to a wire connection, can then be performed on the face 62 of the interposer in contact with the face 13 of the optoelectronic chip 11. In Figure 6, there are shown two conductive portions 63 on the face 62 which can be used for electrical connection by wires. This embodiment advantageously makes it possible to fix the interposer on the whole of the face 64 opposite the face 62 on a radiator and thus to improve the evacuation of the heat produced by the optoelectronic chip 11 via the interposer 12.
    [0007] FIG. 7 shows another embodiment of an optoelectronic device 65 in which the cover 14 comprises a transparent plate 66, for example a glass plate fixed to the frame 42, the photoluminescent block 40 being located between the optoelectronic chip 11 and the transparent plate 66. The thickness of the cover 14 including the transparent plate 66 is greater than or equal to 100 μm, preferably greater than 200 μm, for example approximately 500 μm. In FIG. 7, the side walls of the frame 42, oriented toward the photoluminescent block 40, are inclined so as to improve the reflection of the light supplied by the light-emitting diodes 16 towards the outside of the optoelectronic device 65. FIGS. 8A. 8N illustrate an embodiment of a method for manufacturing the optoelectronic device 10 shown in FIG. 1 in which the method of forming the light emitting diodes corresponds to that described in the patent application FR14 / 50077. FIG. 8A shows the structure obtained after forming, on a substrate 67, a stack of semiconductor layers from which a plurality of electroluminescent diodes 16 will be made, the conductive portions 30 on the stack and dielectric portions 68 on The conductive portions 30. The substrate 67 may correspond to a one-piece structure or may correspond to a layer covering a support made of another material, for example glass or metal. The substrate is, for example, a semiconductor substrate, such as a substrate made of silicon, germanium, silicon carbide or a compound III-V, such as GaN or GaAs, in a compound II-VI, such as than ZnO. Preferably, the substrate 67 is made of silicon, in particular monocrystalline silicon or polycrystalline silicon. The substrate 67 may be an insulating substrate, for example a sapphire substrate. The initial thickness of the optoelectronic chip 11 is between 200 μm and 2 mm. The stack comprises, from bottom to top in FIG. 8A: an N-type doped semiconductor layer 69, for example based on GaN, which comprises a first more heavily doped part forming the semiconductor layer 18, covering the substrate 67, and covered with a less heavily doped portion forming an N-doped semiconductor layer 70. Alternatively, the two layers 18 and 70 may correspond to two layers of different materials. By way of example, the layer 18 may be based on GaN and the layer 70 may be based on InGaN. In addition, since the two layers 18 and 70 correspond to two layers of different materials or to a single layer of the same material, the doping levels of the two layers 18 and 70 may be similar or different; active layers 71 corresponding to an alternating stack of one or more quantum well emissive layers, for example based on InGaN, and barrier layers, for example based on GaN; and a semiconductor layer 72, for example p-type doped GaN. The conductive portions 30 are, for example, formed by deposition of a layer of electrically conductive material, for example aluminum or aluminum. silver, followed by lithography and engraving. The conductive portions 30 and the dielectric portions 68 each have a shape and dimensions, in the plane of the upper face of the semiconductor layer 72 on which they are made, substantially similar to those desired for the light-emitting diodes 16, for example a disc-shaped section. FIG. 8B shows the structure obtained after having etched the semiconductor layer 72, the active layers 71, and a first portion of the semiconductor layer 70 in the pattern defined by the dielectric portions 67, forming, for each light-emitting diode 16, a structure mesa, for example of cylindrical shape, comprising the active zone 26 disposed between the semiconductor portions 24 and 28. This etching is stopped at a depth level located in the semiconductor layer 70 so that a portion of the layer 70 is retained at the bottom of each of the engraved areas of the stack. The etching step forms empty spaces 73 between the light-emitting diodes 16. The etching used is dry etching, for example via a C12-based plasma or reactive ion etching (RIE). The minimum distance between two light-emitting diodes is preferably greater than 15 μm, preferably greater than or equal to 20 μm. FIG. 8C shows the structure obtained after having conformally deposited a dielectric layer 74, for example based on SiN, for example between about 3 nm and 100 nm, on the dielectric portions 68 and along the walls of the void spaces. 73, and thus covering in particular the sidewalls of the conductive portions 30, the semiconductor portions 28, the active zones 26 and a portion of the semiconductor portions 24. FIG. 8D represents the structure obtained after anisotropic etching, by For example, dry etching removes portions of the dielectric layer 74 at the bottom of the voids 73 and the dielectric portions 68. The dielectric portions 36 are thus obtained. FIG. 8E shows the structure obtained after having etched the rest of the semiconductor layer 70 at the bottom of the empty spaces 73 to the semiconductor layer 18, after having etched the dielectric portions 68. FIG. 8F represents the structure obtained after having deposited an electrically conductive material 78 which fills the empty spaces 73 and covers the light-emitting diodes 16. By way of example, the conductive material 78 is formed by the conformal deposition of a first titanium layer of thickness, for example equal to about 10, followed by deposition of a second aluminum layer so as to completely fill the empty spaces 73. The maximum thickness of the conductive material 78 between the bottom of the empty spaces 73, in contact with the semiconductor layer 18, and the upper face of the conductive material 78 is, for example, equal to about 1 pin. FIG. 8G shows the structure obtained after carrying out a planarization step, such as a chemical mechanical planarization (CMP), and / or an etching step, such as an RIE etching, of the electrically conductive material 78 until to reach the upper faces of the conductive portions 30 and the dielectric portions 36. The remaining portions of the conductive material 30 disposed between the light-emitting diodes 16 correspond to the connection elements 37. FIG. 8H shows the structure obtained after having formed the connecting elements 32 and 37. FIG. 81 shows the structure obtained after having fixed the interposer 12 to the optoelectronic chip 11 on the side of the connecting elements 32. The initial thickness of the interposer 12 is greater than or equal to 100 μm, for example between 100 gm and 10 cm. The attachment of the interposer 12 to the optoelectronic chip 11 can be achieved by direct bonding, without the use of inserts such as connection microbeads. Direct bonding may comprise a direct metal-to-metal bonding of the metal areas 32 of the optoelectronic chip 11 and metal areas 34 the interposer 12 and a dielectric-dielectric bonding of the dielectric regions at the surface of the optoelectronic chip 11 and the dielectric regions at the surface of the interposer 12. The attachment of the interposer 12 to the optoelectronic chip 11 can be achieved by a thermocompression process in which the optoelectronic chip 11 is pressed against the interposer 12 with application of a pressure 15 and with heating. FIG. 8J shows the structure obtained after removing the substrate 67 so as to expose the face 15 of the semiconductor layer 18. When the substrate 67 is made of a semiconductor material, the substrate 67 can be removed by a planarization step, such as a chemical mechanical planarization (CMP), and / or an etching step, such as a RIE etching. When the substrate 67 is made of an insulating material such as sapphire, the substrate 67 can be removed by laser ablation. A step of forming patterns in relief on the face 15 may be provided. After the thinning step, the thickness of the optoelectronic chip 11 may be between 100 nm and 50 μm, preferably between 1 μm and 30 μm, for example about 10 μm. FIG. 8K illustrates a step of manufacturing the cover 14 and represents the structure obtained after having etched, in a substrate 80, non-through openings 82 which are intended to be placed vis-à-vis the light-emitting diodes 16 and after having covered the side walls of the openings 82 with the reflective coating 44, for example an aluminum film. The dimensions of the openings 82 correspond to the desired dimensions of the blocks 40 of semiconductor nanocrystals. The reflective coatings 44 may be formed by deposition of a metal layer over the entire substrate 80 and anisotropic etching of the metal layer to retain the metal coating 44 only on the sidewalls of the apertures 82. of the cover 14 can be performed independently of the steps described above. The initial thickness of the cover 14 may be greater than or equal to 100 μm, for example between 100 gm and 5 cm. Alternatively, the openings 82 may be through.
    [0008] FIG. 8L shows the structure obtained after having formed the semiconductor nanocrystals blocks 40 in at least some of the openings 82 and after having fixed the substrate 80 to the optoelectronic chip 11. The photoluminescent blocks 40 can be formed by filling some openings 82 with A photoluminescent material. The photoluminescent material may comprise a matrix in which photoluminescent particles are dispersed. The method of forming the blocks 40 may correspond to a so-called additive process, for example by direct printing of the photoluminescent material at the desired locations, for example by ink jet printing, photogravure, screen printing, flexography, spray coating. spray coating) or drop-casting. The matrix of the photoluminescent material may be a resin which is polymerized after the photoluminescent material has been deposited by printing. By way of example, the polymerization of the matrix can be obtained by exposing the photoluminescent blocks 40 to electromagnetic radiation, in particular ultraviolet radiation. The attachment of the substrate 80 to the optoelectronic chip 11 can be performed by direct bonding or thermocompression. In the case where the photoluminescent material is not the same for all the photoluminescent blocks 40, the filling of the openings 82 can be made in several successive stages, at each stage, openings 82 being filled with a photoluminescent material while the other openings are obscured by resin. FIG. 81v1 shows the structure obtained after a step of thinning the interposer 12 and a step of forming the conductive portions 46 on the face of the interposer 12 opposed to the optoelectronic chip 11. The thickness of the Interposer 12 after the thinning step is less than or equal to 150 μm, preferably between 1 μm and 150 μm, more preferably between 10 μm and 100 μm, for example about 30 μm. The mechanical strength of the structure is then at least partly filled by the cover 14. FIG. 8N represents the structure obtained after a step of thinning the substrate 80, from the side of the substrate 90 opposite the light-emitting diodes 16 to expose the blocks 40 of semiconductor nanocrystals. Thinning can be achieved by mechanical and chemical planarization. The cover 14 may comprise a transparent plate, for example a glass plate. The thickness of the cover 14, including the optional transparent plate, is, after the thinning step, greater than or equal to 100 μm. The next step of the method comprises cutting the structure shown in FIG. 8N, for example along the lines 84. The monolithic devices obtained after cutting then each have the structure shown in FIG.
    [0009] According to another embodiment, the photoluminescent blocks 40 are formed after the step of fixing the cover 14 to the optoelectronic chip 11 and the step of thinning the cover 14 in which the recesses 82 become through.
    [0010] The embodiments of the method of manufacturing the optoelectronic device described above have the advantage of not requiring the use of a temporary handle for handling integrated circuit chips. There is therefore no step of removing a temporary handle. In addition, the interposer 12 may be attached to a support, for example 3033939 18 by a "Flip-Chip" connection. The electrical connection of the interposer 11 can be implemented without the use of connection wires. Figures 9A. to 9D are sectional, partial and schematic views of structures obtained at successive steps of an embodiment of a method of manufacturing the cover 14 of the optoelectronic device 65 shown in FIG. 7. FIG. 9A. is a figure similar to Figure 8K with the difference that the openings 82 have sloping flanks.
    [0011] FIG. 9B shows the structure obtained after fixing the transparent plate 66, in particular a glass plate, to the substrate 80, on the side of the openings 82, for example by an electrostatic glass / silicon bonding. FIG. 9C shows the structure obtained after a step of thinning the substrate 80, from the side of the substrate 90 opposite to the transparent plate 66, to expose the openings 82. Thinning can be achieved by mechanical and chemical planarization . The thickness of the cover 14, comprising the transparent plate 66, is, after the thinning step, greater than or equal to 100 μm. FIG. 9D shows the structure obtained after filling the apertures 82 with a photoluminescent material to form the photoluminescent blocks 40. In the case where the photoluminescent material is not the same for all the photoluminescent blocks 40, the filling of the apertures 82 can be made in several successive steps, at each step, openings 82 being filled with a photoluminescent material while the other openings are obscured by the resin. Subsequent steps of the method include fastening the cover 14 to the optoelectronic chip 11, for example as previously described in connection with Fig. 8L and cutting the resulting structure. The monolithic devices obtained after cutting then each have a cover 14 having the structure shown in FIG.
    [0012] Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although, in the embodiments described above, each optoelectronic device 5 comprises a single photoluminescent block 40, it is clear that the optoelectronic device may comprise several photoluminescent blocks, each photoluminescent block being, for example, opposite a light emitting diode. Various embodiments with various variants have been described above. It is noted that one skilled in the art can combine various elements of these various embodiments and variants without being creative. In particular, the structure shown in FIG. 6, in which the electrical connection between the interposer 12 and another electronic device 15 is made on the face 62 of the interposer 12 in contact with the optoelectronic chip 11, can be implemented with the other embodiments of the optoelectronic device 10, 50, 55, 58, 60 and 65 described in connection with FIGS. 1, 2, 3, 4, 5 and 7. In addition, the structure shown in FIG. the cover 14 comprises a transparent plate 66 may be implemented with the other embodiments of the optoelectronic device 10, 50, 55, 58, 60 and 64 described in connection with Figures 1, 2, 3, 4, 5 and 6 .
    权利要求:
    Claims (10)
    [0001]
    REVENDICATIONS1. A method of manufacturing light-emitting diode optoelectronic devices (10; 50; 55; 58; 59) comprising the steps of: a) forming a first integrated circuit chip (11) comprising light-emitting diodes (16); b) pasting a second integrated circuit chip (12) to a first face (13) of the first integrated circuit chip; c) reducing the thickness of the first integrated circuit chip from the opposite side to the first face to form a second face (15) opposite to the first face, the first integrated circuit chip having, after step c ), a first thickness of between 100 nm and 50 gm; d) adhering, on the second face, a cover (14) comprising a silicon wafer (80) provided with recesses (82) facing the light-emitting diodes, the cover optionally comprising, in addition, a transparent plate (66) attached to the silicon wafer; e) reducing the thickness of the second integrated circuit chip, the second integrated circuit chip having a second thickness less than or equal to 150 gm after step e); f) reducing the thickness of the silicon wafer (80) before step d) or after step e), the thickness of the cover, possibly comprising the transparent plate, being greater than or equal to 100 gm after the step f), each recess 25 being filled with a photoluminescent material; and g) cutting the structure obtained in step f) into several separate optoelectronic devices each comprising at least one of the light-emitting diodes.
    [0002]
    The method of claim 1, wherein the light emitting diodes (16) have a mesa structure.
    [0003]
    The method of claim 1 or 2, wherein the recesses (82) are filled with the photoluminescent material prior to step d). 3033939 B13591 - DD15606JBD 21
    [0004]
    The method of claim 1 or 2, wherein the recesses (82) are non-through before step f), and are therethrough after step f), the method further comprising the step of filling each recess of the photoluminescent material after step f).
    [0005]
    5. Process according to any one of claims 1 to 4, wherein steps b), c) and d) are successive.
    [0006]
    The method of any one of claims 1 to 5, wherein step a) comprises forming the light emitting diodes (16) on a substrate (67) and step c) comprises removing, partially or completely , of the substrate.
    [0007]
    The method according to any one of claims 1 to 6, wherein the second integrated circuit chip (12) is attached to the first integrated circuit chip (11) by direct bonding and is electrically connected to the light emitting diodes (16). ).
    [0008]
    An optoelectronic device (10; 50; 55; 58; 59) comprising: a first integrated circuit chip (11) having opposing first and second faces (13,15) having a thickness of between 100 nia and 50 gm and comprising at least one light emitting diode (16); a cover (14) fixed to the first face, the cover comprising at least one through recess (82) delimited by a frame (42) of silicon and containing a block (40) of a photoluminescent material, the cover comprising, in in addition, possibly a transparent plate (66), the thickness of the cover, possibly comprising the transparent plate, being greater than or equal to 100 gm; and a second integrated circuit chip (12) attached to the second face and having a thickness of less than or equal to 150 pin.
    [0009]
    An optoelectronic device according to claim 8, wherein the light emitting diode (16) has a mesa structure. 3033939 B13591 - DD15606JBD 22
    [0010]
    Optoelectronic device according to claim 8 or 9, wherein the photoluminescent block (40) is laterally surrounded by a reflecting wall (44).
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    法律状态:
    2016-03-25| PLFP| Fee payment|Year of fee payment: 2 |
    2016-09-23| PLSC| Publication of the preliminary search report|Effective date: 20160923 |
    2017-03-31| PLFP| Fee payment|Year of fee payment: 3 |
    2018-03-29| PLFP| Fee payment|Year of fee payment: 4 |
    2020-03-31| PLFP| Fee payment|Year of fee payment: 6 |
    2021-12-10| ST| Notification of lapse|Effective date: 20211105 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1552348|2015-03-20|
    FR1552348A|FR3033939B1|2015-03-20|2015-03-20|OPTOELECTRONIC DEVICE WITH ELECTROLUMINESCENT DIODE|FR1552348A| FR3033939B1|2015-03-20|2015-03-20|OPTOELECTRONIC DEVICE WITH ELECTROLUMINESCENT DIODE|
    EP16160762.7A| EP3070752B1|2015-03-20|2016-03-16|Process of manufacturing of an optoelectronic device with a light-emitting diode|
    KR1020160032747A| KR20160113042A|2015-03-20|2016-03-18|Optoelectronic device comprising a light-emitting diode|
    US15/074,980| US9735139B2|2015-03-20|2016-03-18|Optoelectronic device comprising a light-emitting diode|
    JP2016057295A| JP2016178307A|2015-03-20|2016-03-22|Photoelectric device having light emission diode|
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