THERMALLY STABLE LOAD TRAP LAYER FOR USE IN THE MANUFACTURE OF SEMICONDUCTOR STRUCTURES ON INSULATIO

专利摘要:
A monocrystalline semiconductor carrier substrate for use in the fabrication of a semiconductor-on-insulator (eg, silicon on insulator (SOI)) structure is etched to form a porous layer on the front surface of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished so that it can be bonded to a semiconductor donor substrate. Layer transfer is performed on the polished surface, thereby creating a semiconductor-on-insulator (eg, silicon-on-insulator (SOI)) structure having four layers: the support substrate, the composite layer comprising filled pores, a dielectric layer (eg, buried oxide), and a device layer. The structure can be used as an initial substrate for the manufacture of radio frequency chips. The resulting chips suppressed spurious effects, particularly, no conductive channel induced below the buried oxide.
公开号:FR3033933A1
申请号:FR1652151
申请日:2016-03-15
公开日:2016-09-23
发明作者:Alex Usenko
申请人:SunEdison Semiconductor Pty Ltd；
IPC主号:

专利说明:

[0001] 1 THERMALLY STABLE LOAD TRAPPING LAYER FOR USE IN THE MANUFACTURE OF SEMICONDUCTOR STRUCTURES ON INSULATION CROSS REFERENCE TO RELATED APPLICATION The present application includes a priority claim of US Provisional Patent Application No. 62/134179 filed The present invention relates generally to the field of manufacturing semiconductor wafers. More specifically, the present invention relates to a method for preparing a support substrate for use in the manufacture of a semiconductor-on-insulator (eg, silicon-on-insulator) structure, and more particularly a method for producing a charge trapping layer in the support wafer of the semiconductor-on-insulator structure. BACKGROUND OF THE INVENTION Semiconductor wafers are generally prepared from a monocrystalline ingot (eg, a silicon ingot) which is cut and polished to include one or more dishes or notches for proper wafer orientation in the following procedures. The ingot is then cut into individual slices. Although it is referred to here, semiconductor wafers made from silicon, other materials can be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon-germanium gallium arsenide, and other alloys of group III and group V elements, such as gallium nitride or indium phosphide, or alloys of group II and group IV elements, such as cadmium sulphide or zinc oxide. Semiconductor wafers (for example: silicon wafers) can be used in the preparation of composite layer structures. A composite layer structure (for example, a semiconductor on insulator structure, and more particularly a silicon on insulator (SOI) structure) generally comprises a wafer or a support layer, a device layer, and an insulating film (this is that is, dielectric) (usually an oxide layer) between the support layer and the device layer Generally, the device layer has a thickness between 0.01 and 20 microns, for example a thickness between 0.05 and 20 micrometers Thick film device layers may have a thickness between about 1.5 micrometers and about 2 micrometers Thin film device layers may have a thickness between about 0.01 micrometer and about 0.20 microns. In general, the structures of composite layers, such as silicon on insulator (SOI), silicon on sapphire (SOS) and silicon on quartz, are produced by placing two slices in close contact with each other. t, thereby initiating a link by the van der Waal forces, followed by a heat treatment to strengthen the link. Annealing can convert the silanol end groups to siloxane bonds between the two interfaces, thereby strengthening the bond. After thermal annealing, the bonded structure undergoes additional treatment to remove a substantial portion of the donor wafer to effect a layer transfer.
[0002] For example, slice thinning techniques, for example etching or polishing, may be used, often referred to as BES01 (back etch SOI), in which a silicon wafer is bonded to the support wafer and then etched slowly. until only a thin layer of silicon remains on the support wafer. See, for example, U.S. Patent No. 5,189,500. This method is time consuming, expensive, wastes one of the substrates, and generally does not have an appropriate thickness uniformity for the layers whose thickness is less than a few microns. Another common method for carrying out a layer transfer is hydrogen implantation followed by thermally induced layer separation. Particles (ionized atoms or atoms, for example, hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth below the front surface of the donor wafer. . The implanted particles form a cleavage plane in the donor wafer at the specified depth to which they have been implanted. The surface of the donor wafer is cleaned to remove organic compounds or other contaminants, such as boron compounds, deposited on the wafer during the implantation process. The front surface of the donor wafer is then bonded to a carrier wafer to form a bonded wafer by a hydrophilic bonding process. Prior to binding, the donor wafer and / or the support wafer are activated by exposing the wafer surfaces to a plasma containing, for example, oxygen or nitrogen. Plasma exposure modifies the surface structure in a process often referred to as surface activation, which activation process renders the surfaces of one of the donor wafer and the carrier wafer or both hydrophilic. The surfaces of the slices can be chemically activated by wet treatment, such as etching with SOI or hydrofluoric acid. The wet treatment and plasma activation can take place in any order, or the slices can be subjected to a single treatment. The slices are then pressed against each other, and a link is formed between them. This link is relatively fragile, because of the van der Waal forces, and needs to be strengthened before further processing can take place. In some processes, the hydrophilic bond between the donor wafer and the wafer (i.e., a bonded wafer) is enhanced by heating or annealing the pair of bonded wafers. In some processes, the slices can be bonded at low temperatures, such as between about 300 ° C and 500 ° C. The high temperatures cause the formation of covalent bonds between the adjoining surfaces of the donor wafer and the support wafer, thereby solidifying the bond between the donor wafer and the wafer. Simultaneously with heating or annealing of the bonded wafer, particles implanted earlier in the donor wafer weaken the cleavage plane. A portion of the donor wafer is then separated (i.e., cleaved) along the cleavage plane of the bonded wafer to form the SOI wafer. Cleavage may be effected by placing the bonded wafer in a fastener wherein a mechanical force is applied perpendicularly to the opposite sides of the bonded wafer to separate a portion of the donor wafer from the bonded wafer. According to some methods, suction cups are used to apply the mechanical force. Separation of the portion of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the level of the cleavage plane to initiate propagation of a crack along the cleavage plane. . The mechanical force applied by the suction cups then pulls the portion of the donor wafer from the bonded wafer, thereby forming a wafer of SOI. According to other methods, the bonded pair may instead be subjected to a high temperature for a period of time to separate the portion of the donor wafer from the bonded wafer. Exposure to high temperature causes crack initiation and propagation along the cleavage plane, thereby separating a portion of the donor wafer. The crack is formed due to the formation of voids from the implanted ions, which develop by Ostwald ripening. The voids are filled with hydrogen and helium. Voids become platelets. The pressurized gases in the wafers propagate micro-cavities and micro-cracks, which weaken the silicon on the implantation plane. If annealing is stopped at the appropriate time, the weakened bonded slice can be cleaved by a mechanical process. However, if the heat treatment is continued for a longer time and / or at a higher temperature, the propagation of micro-cracks reaches the level where all the cracks merge along the cleavage plane, thus separating part of the donor slice. This method provides improved uniformity of the transferred layer and allows for recycling of the donor wafer, but generally requires heating of the bonded pair that has been implanted at temperatures approaching 500 ° C; The use of high resistivity semiconductor on insulator (eg, silicon on insulator) wafers for radio frequency (RF) related devices, such as antenna switches, offers advantages over conventional substrates in terms of cost and integration. In order to reduce parasitic power loss and minimize the inherent harmonic distortion when using conductive substrates for high frequency applications, it is necessary, but not sufficient, to use substrate slices with a high frequency. Resistivity. Therefore, the resistivity of the carrier wafer for an RF device is generally greater than about 500 Ohm-cm. With reference to FIG. 1, a silicon on insulator structure 2 comprises a very high resistivity silicon wafer 4, a buried oxide layer (BOX) 6, and a silicon device layer 10. Such a substrate is subject to the formation of high conductivity charge reversal or accumulation layers 12 at the BOX / carrier interface causing the generation of free carriers (electrons or holes), which reduce the effective resistivity of the substrate and cause parasitic power losses and non-linearity of the devices when the devices are operated at RF frequencies. These inversion / accumulation layers may be due to BOX charge, oxide entrapped charge, entrapped charge in the interface, and even continuous bias applied to the devices themselves. A method is therefore necessary to trap the charge in the induced inversion or accumulation layers so that the high resistivity of the substrate is maintained even in the region very close to the surface. It is known that charge trapping layers (CTL) between high resistivity support substrates and buried oxide (BOX) can improve the performance of RF devices manufactured using SOI slices. A number of methods have been suggested for forming these high resistivity interface trapping layers. For example, with reference to FIG. 2, one of the methods of creating a semiconductor on insulator (for example, a silicon on insulator, or SOI) with a CTL for RF device applications is based on the depositing an undoped polycrystalline silicon film 28 on a silicon substrate having a high resistivity 22 and then forming a stack of an oxide 24 and an upper silicon layer 26 thereon. A polycrystalline silicon layer 28 acts as a layer having many defects between the silicon substrate 22 and the buried oxide layer 24. See FIG. 2, which shows a polycrystalline silicon film for use as a layer a method of entrapping charges between a high resistivity substrate 22 and the buried oxide layer 24 in a silicon-on-insulator structure 20. Another method involves the implantation of heavy ions to create a damage layer. close to the surface. Devices, such as radio frequency devices, are incorporated in the upper silicon layer 26. It has been shown in academic studies that the polycrystalline silicon layer between the oxide and the substrate improves the isolation of devices, decreases transmission line losses and reduces harmonic distortions. See, for example, H. S. Gamble et al. "Low-loss CPW lines on surface stabilized high resistivity silicon", Microwave Guided Wave Lett., 9 (10), 395-397, 1999; D. Lederer, R. Lobet and J.-P. Raskin, "Enhanced high resistivity SOI wafers for RF applications", IEEE Int SOI Conf., Pp. 46 and 47, 2004; D. Lederer and J.-P. Raskin, "New substrate passivation method dedicated to high resistivity SOI wafer fabrication with enhanced substrate resistivity", IEEE Electron Device Letters, vol. 26, No. 11, pp. 805-807, 2005; D.
[0003] Lederer, B. Aspar, C. Laghae, and J.-P. Raskin, "Performance of RF Passive Structures and SOI MOSFETs Passivated HR SOI substrate," IEEE International SOI Conference, pp. 29 and 30, 2006; and Daniel C. Kerret and others, "Silicon Monolithic Integrated Circuits in RF Systems, 2008, SiRF 2008 (IEEE Topical Meeting), 20 pages. The properties of the polycrystalline silicon charge trapping layer depend on the heat treatments applied to the semiconductor on insulator (for example, silicon on insulator). A problem with these methods is that the density of defects in the layer and the interface tends to disappear and become less efficient for charge trapping while the wafers are subjected to the thermal processes necessary to achieve the slices and install the devices on these. Therefore, the effectiveness of polycrystalline silicon CTL depends on the heat treatments applied to the SOI. In practice, the thermal cost of SOI fabrication and device processing is so high that charge traps in conventional polycrystalline silicon are essentially eliminated. The charge trapping efficiency of these films becomes very poor. SUMMARY OF THE INVENTION In one aspect, the object of the present invention is to provide a method for manufacturing semiconductor on insulator wafers (eg, silicon on insulator) with thermally stable charge trapping layers. which preserve the charge trapping efficiency and significantly improve the performance of the finished RF devices. In summary, the present invention relates to a multilayer structure. The multilayer structure comprises a monocrystalline semiconductor support substrate comprising two generally parallel major surfaces, one of which is a front surface of the single crystal semiconductor support substrate and the other is a back surface of the monocrystalline semiconductor support substrate, a circumferential edge joining the front and rear surfaces of the monocrystalline semiconductor support substrate, a central plane between the front surface and the back surface of the monocrystalline semiconductor support substrate 10, a front surface region having a depth D, as measured from the front surface and towards the central plane, and a body region between the front and rear surfaces of the monocrystalline semiconductor support substrate, wherein the front surface region comprises pores, each of the pores comprising a bottom surface and a sidewall surface, and further wherein the pores are filled with an amorphous semiconductor material, a polycrystalline semiconductor material, or a semiconductor oxide; a dielectric layer in contact with the front surface of the monocrystalline semiconductor support substrate; and a monocrystalline semiconductor device layer in contact with the dielectric layer. The present invention further relates to a method of forming a multilayer structure. The method comprises: contacting a front surface of a monocrystalline semiconductor carrier substrate with an etching solution to thereby etch pores in a front surface region of the monocrystalline semiconductor support substrate; wherein the monocrystalline semiconductor support substrate comprises two generally parallel major surfaces, one of which is the front surface of the single crystal semiconductor support substrate and the other is a back surface of the monocrystalline semiconductor support substrate, an edge circumferential joining the front and rear surfaces of the monocrystalline semiconductor support substrate, a central plane between the front surface and the back surface of the monocrystalline semiconductor support substrate, the front surface region having a depth D, as measured from of the front surface and towards the central plane, and a body region between the front and rear surfaces of the substrate monocrystalline semiconductor medium, wherein each of the pores comprises a bottom surface and a sidewall surface; oxidation of the bottom surface and the sidewall surface of each of the pores; filling each of the pores having the oxidized bottom surface and the oxidized sidewall surface with an amorphous semiconductor material, a polycrystalline semiconductor material, or a semiconductor oxide; and bonding a dielectric layer on a front surface of a monocrystalline semiconductor donor substrate to the front surface of the monocrystalline semiconductor support substrate to thereby form a bonded structure, wherein the donor substrate Monocrystalline semiconductor comprises two generally parallel main surfaces, one of which is the front surface of the semiconductor donor substrate and the other is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and rear surfaces. of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate. Other objects and features of the present invention will be partly obvious and partly indicated below. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a representation of a silicon on insulator wafer comprising a high resistivity substrate and a buried oxide layer.
[0004] FIG. 2 is a representation of a silicon-on-insulator wafer according to the prior art, wherein the SOI wafer comprises a polycrystalline silicon charge-trapping layer between a high-resistivity substrate and a buried oxide layer. Figure 3 is a representation of a silicon on insulator wafer according to the present invention, the SOI wafer comprising a porous charge trapping layer between a high resistivity substrate and a buried oxide layer. Figs. 4A to 4C show the process for preparing a semiconductor-on-insulator structure according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENT (S) OF THE INVENTION According to the present invention, a method is provided for producing a charge trapping layer on a monocrystalline semiconductor support substrate, for example, a monocrystalline semiconductor carrier wafer. , such as a monocrystalline silicon support wafer. The monocrystalline semiconductor carrier wafer comprising the charge trapping layer is useful in producing a semiconductor-on-insulator (eg, silicon on insulator) structure. According to the present invention, the charge trapping layer in the monocrystalline semiconductor carrier wafer is formed at the region near the oxide interface. Advantageously, the method of the present invention provides a charge trapping layer which is stable with respect to a heat treatment, such as, for example, the following thermal process steps in the production of the semiconductor on insulator substrate and device manufacture.
[0005] In some embodiments of the present invention, and with reference to Fig. 3, a monocrystalline semiconductor support substrate 42 (i.e., a monocrystalline silicon support substrate) is prepared for use in the manufacture of a semiconductor on insulator structure (for example, silicon on insulator) 40.
[0006] In some embodiments, the monocrystalline semiconductor carrier substrate 42 is etched to form a porous layer 44 in the front surface region of the substrate 42. The etching process increases the surface area exposed in the surface region In certain embodiments, the monocrystalline semiconductor support substrate 42 is etched electrochemically to form a porous layer in the surface region before a substrate. Upon drying and exposing the etched surface to an ambient atmosphere comprising oxygen (e.g., air), the exposed etched surface of the porous film is oxidized. Exposure to air during drying may be, in some embodiments, sufficient for the oxidation of pore surfaces. In some embodiments, the pores may be anodically oxidized or thermally oxidized. In some embodiments, the etched porous region, optionally including an oxide film, is filled with a semiconductor material. In some embodiments, the etched porous region, optionally including an oxide film, is filled with a semiconductor material of the same type as the monocrystalline semiconductor support substrate. In some embodiments, the monocrystalline semiconductor support substrate comprises a monocrystalline silicon support substrate, and the etched porous region is filled with silicon. In some embodiments, polycrystalline silicon is deposited to fill the pores in the porous layer. In some embodiments, amorphous silicon is deposited to fill the pores in the porous layer. In some embodiments, the etched porous region may be oxidized to thereby fill the pores with a semiconductor oxide, for example, silicon dioxide. The surface of the structure comprising the filled pores can be polished so that the surface can be bonded. For example, the filled structure may comprise an excess layer of filler material on the front surface of the monocrystalline semiconductor support substrate. The excess layer of filler material can be polished so that the front surface of the support substrate can be bonded. The resulting support substrate 42 is suitable for use in the manufacture of a semiconductor-on-insulator (eg, silicon-on-insulator) structure 40. A layer transfer is performed on the polished surface, thereby creating a structure semiconductor on insulator (eg, silicon on insulator) comprising the support substrate 42, the composite layer comprising the filled pores 44, a dielectric layer 46 (for example, buried oxide), and a layer monocrystalline semiconductor device 48 (e.g., a silicon layer derived from a monocrystalline silicon donor substrate). The semiconductor-on-insulator (eg silicon-on-insulator) structure 40 of the present invention can be used as the initial substrate for the manufacture of radio frequency chips. The resulting chips do not show any parasitic effects. In particular, a semiconductor-on-insulator (eg silicon-on-insulator) structure 40 comprising support substrates 42 prepared according to the method of the present invention does not have a conductive channel 10 induced beneath the buried oxide. . According to the method of the present invention, a composite film 44 in the front surface region of the monocrystalline semiconductor support substrate 42 is obtained by making a porous layer, oxidizing the exposed walls of the pores, and refilling the pores with a semiconductor (eg silicon) deposited or refilling the pores with a semiconductor oxide (eg, silicon dioxide). The resulting composite film 44 is suitable for use as a thermally stable rich entrapment layer in an SOI wafer. Thermal stability is a fundamental difference between ordinary polycrystalline silicon, which is a conventional charge trapping layer, and composite film 44 in the present invention. In this regard, the annealing of a structure comprising a conventional charge trapping layer, which may take place during the subsequent thermal process steps, brings the system into a lower free energy state. When polycrystalline silicon is in the charge-trapping layer, energy is associated with the grain boundaries, which is reduced to a minimum by minimizing the area of the grain boundaries. This reduces the overall efficiency of polycrystalline silicon as a charge trapping layer. When a composite film of the present invention is prepared as a charge trapping layer, the oxide walls divide the film into grains, and magnification requires the dissolution of the walls. This requires temperatures above 1,100 ° C. Therefore, the composite film in the front surface region of the monocrystalline semiconductor support substrate is thermally stable in the desired temperature range. The substrates for use in the present invention comprise a semiconductor substrate, for example a monocrystalline semiconductor carrier wafer and a semiconductor donor substrate, for example a monocrystalline semiconductor donor wafer. The semiconductor device layer 48 in a semiconductor-on-insulator composite structure 40 is derived from the monocrystalline semiconductor donor wafer. The semiconductor device layer 48 may be transferred to the semiconductor support substrate 42 by slice thinning techniques such as etching a semiconductor donor substrate 5 or by cleaving a semi donor substrate -conductor comprising a plan of damage. In general, the monocrystalline semiconductor carrier wafer and the monocrystalline semiconductor donor wafer comprise two generally parallel major surfaces. One of the parallel surfaces is a front surface of the substrate, and the other parallel surface is a back surface of the substrate. The substrates 10 include a circumferential edge joining the front and rear surfaces, a body region between the front and rear surfaces, and a central plane between the front and rear surfaces. The substrates further include an imaginary central axis perpendicular to the central plane and a radial length extending from the central axis to the circumferential edge. In addition, because semiconductor substrates, for example, silicon wafers, generally exhibit some variation in total thickness (TTV), some warping, and some bending, the center point between each point on the front surface and each point on the back surface may not fall accurately into a plane. In practice, however, TTV, warping and bending are generally so small that, as a first approximation, it can be said that the center points fall into an imaginary central plane which is approximately equidistant between the surfaces. front and rear. Before any operation as described herein, the front surface and the rear surface of the substrate may be substantially identical. A surface is referred to as a "front surface" or "back surface" simply for convenience and generally to distinguish the surface on which the process operations of the present invention are carried out. In the context of the present invention, a "front surface" of a monocrystalline semiconductor carrier substrate, for example, a monocrystalline silicon wafer, refers to the main surface of the substrate which becomes an inner surface of the substrate. linked structure. It is on this surface before the charge trapping layer is formed. In addition, the monocrystalline semiconductor support substrate may be considered to have a front surface region having a depth D as measured from the front surface of the support substrate and toward the central plane. Length D defines the depth of the porous composite layer region 44 formed in accordance with the method of the present invention. The depth D may range from about 0.1 micrometer to about 50 micron, for example, from about 0.3 micrometer to about 20 micron, for example, from about 1 micron to about 10 micron, for example, from about 1 micron. and about 5 micrometers, as measured from the front surface of the monocrystalline semiconductor support substrate to the central plane. A "back surface" of a monocrystalline semiconductor carrier substrate, for example, a carrier wafer, refers to the main surface which becomes an outer surface of the bonded structure. Similarly, a "front surface of a monocrystalline semiconductor donor substrate, for example, a monocrystalline silicon donor wafer, refers to the main surface of the monocrystalline semiconductor donor substrate which becomes an inner surface of the monocrystalline semiconductor donor wafer. linked structure. The front surface of a monocrystalline semiconductor donor substrate 10 often includes a dielectric layer 46 comprising one or more insulating layers. The dielectric layer 46 may comprise a layer of silicon dioxide, which forms the buried oxide layer (BOX) in the final structure 40. A "back surface" of a monocrystalline semiconductor donor substrate, e.g. a monocrystalline silicon donor wafer, refers to the main surface which becomes an outer surface of the bonded structure. At the end of the conventional wafer bonding and thinning steps, the monocrystalline semiconductor donor substrate forms the semiconductor device layer 48 of the composite semiconductor-on-insulator (eg, silicon on insulator) structure. 40. The monocrystalline semiconductor support substrate and the monocrystalline semiconductor donor substrate may be monocrystalline semiconductor slices. In preferred embodiments, the semiconductor wafers comprise a semiconductor material selected from the group consisting of silicon, silicon carbide, silicon-germanium, gallium arsenide, gallium nitride, phosphide, and the like. indium, indium gallium arsenide, germanium, and combinations thereof. The monocrystalline semiconductor wafers, for example, the monocrystalline silicon wafer wafer and the single crystal silicon donor wafer, of the present invention generally have a nominal diameter of at least about 150 mm, at least about 200 mm, d at least about 300 mm, or at least about 450 mm. The wafer thicknesses can range from about 250 micrometers to about 1,500 micrometers, for example, from about 300 micrometers to about 1,000 micrometers, suitably in the range of about 500 micrometers to about 1,000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers. In particularly preferred embodiments, the monocrystalline semiconductor wafers comprise monocrystalline silicon wafers that have been cut in a monocrystalline ingot obtained according to conventional Czochralski crystal growth methods or by methods of growth. floating area. These methods, as well as standard techniques for slicing, etching, etching and polishing silicon are presented, for example, in F. Shimura, Silicon Crystal Technology Semiconductor, Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier ed.) Springer-Verlag, NY, 1982. Preferably, the slices are polished and cleaned by standard methods known to those skilled in the art. See, for example, W.C. O'Mara et al., Silicon Technology Handbook of Semiconductor, Noyes Publications. If desired, the slices can be cleaned, for example, in a standard SC1 / SC2 solution. In some embodiments, the monocrystalline silicon wafers of the present invention are monocrystalline silicon wafers that have been cut in a monocrystalline ingot obtained by conventional Czochralski crystal ("Cz") growth methods, generally having a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. Preferably, both the monocrystalline silicon wafer and the single crystal silicon wafer have surfaces that have been previously mirror polished so that they are free of surface defects, such as large particles, etc. The thickness of the wafers may vary from about 250 micrometers to about 1,500 micrometers, for example, from about 300 micrometers to about 1,000 micrometers, suitably in the range of about 500 micrometers to about 1,000 micrometers. In some specific embodiments, the slice thickness may be about 725 micrometers. In some embodiments, the monocrystalline semiconductor support substrate and the monocrystalline semiconductor donor substrate, i.e., the noncocrystalline semiconductor carrier wafer and the monocrystalline semiconductor donor wafer, comprise interstitial oxygen at concentrations which are generally achieved by the Czochralski growth method. In some embodiments, the semiconductor wafers comprise oxygen in a concentration of between about 4 PPMA and about 18 PPMA. In some embodiments, the semiconductor wafers comprise oxygen in a concentration of between about 10 PPMA and about 35 PPMA. Preferably, the monocrystalline silicon support wafer comprises oxygen in a concentration of not more than about 10 PPMA. The interstitial oxygen can be measured according to the standard SEMI MF 1188-1105.
[0007] The monocrystalline semiconductor carrier substrate may have any resistivity obtainable by Czochralski's methods or by floating zone.
[0008] In some embodiments, the monocrystalline semiconductor carrier substrate has a relatively low minimum resistivity, such as less than about 100 ohm-cm, less than about 50 ohm-cm, less than about 1 ohm-cm, less than about 0.1 ohm-cm, or even less than about 0.01 ohm-cm. In some embodiments, the monocrystalline semiconductor carrier substrate has a relatively low minimum volume resistivity, such as less than about 100 ohm-cm, or about 1 ohm-cm to about 100 ohm-cm. Low resistivity slices may comprise electrically active dopants, such as boron (p-type), gallium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (type n).
[0009] In some embodiments, the monocrystalline semiconductor support substrate has a relatively high minimum volume resistivity. The high resistivity slices are generally cut into monocrystalline ingots obtained by the Czochralski process or the floating zone method. High resistivity slices may include electrically active dopants, such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type) , phosphorus (n-type), antimony (n-type), and arsenic (n-type), in generally very low concentrations. The silicon wafers developed by the Cz process can be thermally annealed at a temperature of from about 600 ° C to about 1000 ° C in order to annihilate the oxygen-generated thermal donors that are incorporated during growth. crystal. In some embodiments, the monocrystalline semiconductor carrier wafer has a minimum volume resistivity of at least 100 ohm-cm, at least about 500 ohm-cm, at least about 1,000 ohm-cm, or even greater than at least about 3,000 ohm-cm, for example about 100 ohm-cm to about 100,000 ohm-cm, or about 500 ohm-cm to about 100,000 ohm-cm, or about 1,000 ohm-cm to about 100,000 ohm cm, or between about 500 ohm-cm and about 10,000 ohm-cm, or between about 750 ohm-cm and about 10,000 ohm-cm, between about 1,000 ohm-cm and about 10,000 ohm-cm, between about 2,000 ohm-cm and about 10,000 ohm-cm, from about 3,000 ohm-cm to about 10,000 ohm-cm, or from about 3,000 ohm-cm to about 5,000 ohm-cm. In some embodiments, the high resistivity monocrystalline semiconductor support substrate may comprise a p-type dopant, such as boron, gallium, aluminum, or indium. In some embodiments, the high resistivity monocrystalline semiconductor carrier substrate may comprise an n-type dopant, such as phosphorus, antimony, or arsenic. Methods for making high resistivity slices are known in the art, and these high resistivity slices can be obtained from commercial suppliers such as SunEdison Semiconductor Ltd. (St. Peters, MO; formerly MEMC Electronic Materials, Inc.). In some embodiments, the monocrystalline semiconductor carrier wafer surface could be intentionally damaged by an abrasive blasting process or by caustic etching. Due to the use of a high resistivity semiconductor, for example, high resistivity silicon, as a substrate support material, in some embodiments, a p-type dopant can be implanted in a region. on the back side of the support substrate prior to the formation of porous silicon to promote the formation of 10 holes required for the formation of porous silicon. This can be accomplished by implanting dopants, such as boron, at shallow depth on the back side of the wafer and subjecting the wafer to implant annealing. The depth of the implant is sufficiently low and the thickness of the wafer is sufficiently large that, during the heat treatment of the multilayer semiconductor on insulator structure, for example, silicon on insulator, in the line device, the dopant does not diffuse sufficiently close to the charge trapping layer interface to reduce the resistivity of silicon in this region, which is necessary for good RF performance. For n-type substrates with very high resistivity, backside illumination may be required to produce holes for porous silicon formation. In some embodiments, low-doped n-type slices are used in this application, and illumination from the back side can be advantageously used to control the average pore diameter. Without illumination, the pores could have an excess diameter greater than 100 nm. For n-type doped silicon, the pore size and the spacing between the pores can be reduced to about 5 nm, and the pore network generally seems very homogeneous and interconnected. As lighting increases, pore sizes and pore spacing increase, while the specific surface area decreases. The structure becomes anisotropic, with long voids extending perpendicular to the surface.
[0010] In some embodiments, the front surface of the semiconductor carrier wafer is treated to form a porous layer. The porous layer may be formed by contacting the front surface of a monocrystalline semiconductor support substrate with an etching solution. In some embodiments, the etching solution comprises an aqueous solution of hydrofluoric acid. Alcohols, such as ethyl alcohol or isopropyl alcohol, and surfactants, such as sodium lauryl sulfate and CTEC, can be added. While porous silicon (p-Si) is produced at the anode of the cell, gaseous hydrogen bubbles are produced. These bubbles adhere to the surface of the developing p-Si surface. These bubbles act as masks, blocking the flow of current and the access of hydrofluoric acid. Alcohols, such as ethyl alcohol or isopropyl alcohol, and surfactants, such as sodium lauryl sulphate and CETC, help reduce this effect. A typical electrolyte may have a 1: 1: 1 ratio (hydrofluoric acid: water: alcohol), other examples have a 3: 1 ratio (hydrofluoric acid: alcohol). In some embodiments, the carrier wafer is etched electrochemically in a solution of hydrofluoric acid, for example, in a Teflon cell. One such commercially available cell is the dual wet etch cell for porous silicon etching available from AMMT GmbH. The electrochemical etching takes place under conditions sufficient to etch pores in a front surface region of the monocrystalline semiconductor support substrate. The properties of the porous silicon, such as porosity, thickness, pore diameter and microstructure, depend on the anodizing conditions. These conditions include hydrofluoric acid concentration, current density, wafer type and resistivity, anodizing time, lighting, temperature and drying conditions. The choice of the good conditions for obtaining a desired porosity and pore size is described in the prior art, for example "Porous silicon: a quantum sponge structure for silicon based optoelectronics" by O. Bisi, S. Ossicini, L. Pavesi, Surface Science Reports, Vol. 38 (2000) pages 1-126. In some embodiments, the current density may be in the range of about 5 mA / cm 2 to about 800 mA / cm 2. In some embodiments, the duration of the etching may be between about 1 minute and about 30 minutes. The bath temperature is generally maintained at room temperature. Porosity, i.e., pore density, generally increases as the current density increases. In addition, for a fixed current density, porosity decreases with increasing hydrofluoric acid concentration. With fixed hydrofluoric acid concentration and current density, porosity increases with thickness and depth porosity gradients occur. This occurs because of the further chemical dissolution of the porous silicon layer of hydrofluoric acid. The thicker the layer, the longer the anodization time, and the longer the Si residence time in hydrofluoric acid, the higher the mass of chemically dissolved porous silicon. This effect is much more important for the weakly doped Si, while it is almost negligible for the heavily doped Si, due to the smaller specific surface area.
[0011] The front surface region may be etched at an average depth between about 0.1 micrometer and about 50 micrometers, for example between about 0.3 micrometer and about 20 micrometer, for example, between about 1 micrometer and about 10 micrometer, for example. for example, between about 1 micrometer and about 5 micrometers as measured from the front surface of the monocrystalline semiconductor support substrate to the bottom surfaces of the pores. Each of the pores has a substantially tubular or cylindrical shape, for example the pores comprise a bottom surface and a sidewall surface. The shape of the pores can vary significantly from one pore to another. See FIG. 4A for a representation of a front surface region 10 of a monocrystalline semiconductor support substrate 100 comprising a plurality of pores 102. This figure shows macro-porous silicon. The pores with a roughly cylindrical shape can be considered to have an average diameter between about 1 nanometer and about 1,000 nanometers, for example between about 2 nanometers and about 200 nanometers, as measured at any point along the lateral wall of the pores. In some embodiments, the front surface region may be characterized by a pore density, i.e., the total pore volume as a percentage of the total volume of the front surface region between about 5% and about 80%, for example between about 5% and about 50%. In some embodiments, the front surface region may be characterized by a pore density, i.e., the total pore volume as a percentage of the total volume of the front surface region between about 5 and about 35%, for example between about 5% and about 25%. In a specific embodiment, a wafer can be electrochemically etched in a solution of 50% ethanol / 50% hydrofluoric acid (48 wt.%) With a current density of 20 mA / cm 2 and then rinsed in with water. deionized water. The etching time varies from 1 to 20 minutes, thus resulting in layer thicknesses of between about 0.3 and 1.5 microns. The films usually have a deep black color. Other electrolyte compositions may be properly selected by one skilled in the art as described in the reviews cited above. In some embodiments, the monocrystalline semiconductor support substrate comprising a porous layer in the front surface region may be subjected to drying in an oxygen-containing ambient atmosphere. The drying operation is optionally preceded by wet cleaning and rinsing, and may optionally be preceded by multiple rinses and cleanings. In some embodiments, the support substrates are rinsed, followed by transfer to a wet cleaning and rinsing station, rinsed with deionized water, then dried in an oxygen-containing ambient atmosphere. for example, air or purified oxygen. During drying, the entire pore sidewall surfaces are oxidized, resulting in a so-called native oxide, which has a thickness of about 1 nm. If the drying / oxidation is carried out at room temperature, it usually takes a little time, for example, up to one hour, since after the hydrofluoric bath, the surface is hydrophobic, being terminated with hydrogen . In addition, hydrogen is gradually desorbed from the surface, allowing it to oxidize. Cleaning can also be performed in wet cleaning solutions used in the semiconductor industry such as RCA-clean, Piranha clean, or in ozonated water. In this case, a chemical oxide is formed on the pore wall surfaces, which is generally thicker than the native oxide, up to several nanometers. In some embodiments, the native oxide layer may further be oxidized to form a thicker oxide layer. This can be accomplished by means known in the art, such as thermal oxidation (in which some portion of the exposed semiconductor material will be consumed), chemical vapor phase oxide deposition, or chemical vapor deposition. plasma oxide. In some embodiments, the monocrystalline semiconductor support substrate, for example, a monocrystalline silicon wafer, comprising pores, may be thermally oxidized in an oven such as an A400 ASM. The temperature can range from 750 ° C to 1,200 ° C in an ambient oxidation atmosphere.
[0012] The ambient oxidation atmosphere may be a mixture of inert gases, such as Ar or N 2, and O 2. The oxygen content may vary from 1 to 10%, or more. In some embodiments, the ambient oxidation atmosphere can reach 100% ("dry oxidation"). In an exemplary embodiment, the semiconductor carrier slices can be loaded in a vertical furnace, such as an A400. The temperature is brought to the oxidation temperature with a mixture of N 2 and O 2. After the desired oxide thickness has been obtained, the O 2 supply is cut off and the oven temperature is reduced and the slices are discharged from the oven. Thermal oxidation can be used to fill porous films with low porosity with a semiconductor oxide, for example, silicon dioxide.
[0013] The thermal oxidation of highly porous films is undesirable since it could result in the rupture of silicon walls between neighboring pores, thus lowering productivity. Plasma oxidation can be used, resulting in thicknesses of silicon dioxide film on the pore sidewalls of 10 to 20 nm, depending on plasma conditions such as frequency and power.
[0014] Plasma oxidation consists of producing an oxygen plasma in a closed chamber (usually under vacuum). The plasma can be produced by a microwave plasma generator, r.f. (radio frequency), or c.c. (direct current). This can also be called plasma enhanced chemical vapor deposition reactor (PECVD reactor). In some embodiments, an oxide film on the porous silicon may be produced by anodic oxidation (generally referred to as anodizing, for example, aluminum anodizing). This is done using the same electrochemical cell of porous silicon. However, the electrolyte is replaced by dilute sulfuric acid (concentrated sulfuric acid is used for aluminum anodization). For porous silicon, the literature suggests the use of 1 M H2SO4. If the current is very high, arc formation may occur. Oxidation of the sidewall and bottom surfaces of the pores under high current conditions in oxidation electrolytes, such as sulfuric acid, is referred to as plasma electrolytic oxidation. However, the current is a direct current, and there is no frequency. In certain embodiments in which the front surface region has a relatively low porosity, for example a pore density of between about 5% and about 25%, thermal oxidation can be performed to fill the entire pore with a semiconductor oxide. conductor, for example, silicon dioxide. The surface of the wafer thus prepared is packaged to allow bonding of the wafer, as described below, and filling of the pores with a semiconductor material is not necessary. Additional layer transfer is performed, resulting in an SOI slice. This slice also has an additional 4th layer which serves as a parasitic oscillation elimination system if RF chips are made on these slices. This parasitic oscillation elimination film does not have a high trap density, but it is still effective in suppressing RF parasitic oscillations since it has a very high resistivity, i.e. say, semi-insulating properties. According to some embodiments of the method of the present invention, a semiconductor material is deposited in the pores formed in the front surface region of the monocrystalline semiconductor carrier wafer. See Fig. 4B showing a monocrystalline semiconductor support substrate 100 comprising pores which are filled with a semiconductor material 104. The pore surfaces, for example, the side and bottom wall surfaces, may comprise a layer of semiconductor material. native oxide or can be further oxidized by thermal oxidation or plasma. A semiconductor material suitable for filling the pores is optionally of the same composition as the high resistivity monocrystalline semiconductor support substrate. This semiconductor material may be selected from the group consisting of silicon, silicon carbide, silicon-germanium, gallium arsenide, gallium nitride, indium phosphide, arsenide, and the like. indium-gallium, germanium, and combinations thereof. These materials include polycrystalline semiconductor materials and amorphous semiconductor materials. In some embodiments, materials that may be polycrystalline or amorphous include silicon (Si), silicon-germanium (SiGe), silicon carbide (SIC), and germanium (Ge). A polycrystalline material, for example polycrystalline silicon, indicates a material comprising small silicon crystals having random crystalline orientations. The polycrystalline silicon grains may be about 20 nanometers in size. According to the method of the present invention, the smaller the size of the crystalline grains of the deposited polycrystalline silicon, the greater the presence of defects in the charge trapping layer. The amorphous silicon comprises a non-crystalline allotropic form of silicon, which lacks short range and long range order. Silicon grains having a crystallinity not exceeding about 10 nanometers can also be considered essentially amorphous. The silicon-germanium comprises a silicon-germanium alloy in any molar ratio of silicon and germanium. Silicon carbide comprises a silicon and carbon compound whose molar ratio of silicon and carbon may vary. Preferably, the charge trapping layer comprising the filled pores has a resistivity of at least about 1,000 Ohm-cm, or at least about 3,000 Ohm-cm, such as between about 1,000 Ohm-cm and about 100,000 Ohm-cm. Ohm-cm, between about 1,000 Ohm-cm and about 10,000 Ohm-cm, between about 2,000 Ohm-cm and about 10,000 Ohm-cm, between about 3,000 Ohm-cm and about 10,000 Ohm-cm, or between about 3,000 Ohm-cm and about 5,000 Ohm-cm. The material for filling the pores in the front surface region of the monocrystalline semiconductor carrier wafer may be deposited by means known in the art. For example, the semiconductor material can be deposited using a metallo-organic chemical vapor deposition (MOCVD), a physical vapor deposition (PVD), a chemical vapor deposition (CVD), a chemical deposition low pressure vapor phase (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors for LPCVD or PECVD include methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHC13), silicon tetrachloride (SiCl4), among others. For example, polycrystalline silicon may be deposited on the surface oxidation layer by pyrolysis of the silane (SiH4) in a temperature range between about 550 ° C and about 690 ° C, for example, between about 580 ° C and about 650 ° C. The pressure of the chamber can range from about 70 to about 400 mTorr. Amorphous silicon can be deposited by plasma enhanced chemical vapor deposition (PECVD) at temperatures generally from about 75 ° C to about 300 ° C. Silicon germanium, particularly amorphous silicon-germanium, can be deposited at temperatures up to about 300 ° C by chemical vapor deposition including organogermanium compounds, such as isobutylgermane, alkylgermanium trichlorides, and dimethylaminogermanium trichloride. Silicon carbide can be deposited by thermal plasma vapor deposition in epitaxial reactors using precursors such as silicon tetrachloride and methane. Suitable carbon precursors for CVD or PECVD include methylsilane, methane, ethane, ethylene, among others. For LPCVD deposition, methylsilane is a particularly preferred precursor since it provides both carbon and silicon. For PECVD, preferred precursors include silane and methane. In some embodiments, the silicon layer may comprise a carbon concentration of at least about 1% on an atomic basis, for example between about 1% and about 10%. The overall thickness of the charge trapping layer comprising the filled pores is dictated by the etching process as described above. Therefore, the front surface region of the monocrystalline semiconductor substrate may comprise a charge trapping layer comprising filled pores having a mean depth of between about 0.1 micrometer and about 50 micrometer, for example, about 0.3 micrometer. and about 20 micrometers, for example between about 1 micrometer to about 10 microns, for example, from about 1 micrometer to about 5 microns, as measured from the front surface of the monocrystalline semiconductor support substrate to the bottom surfaces of the microcrystalline semiconductor substrate. pores. The step of filling pores serves several purposes. One goal is to allow additional layer transfer. That is, layer transfer to a porous surface is not desired since it will be difficult to make a wafer bond therewith. Furthermore, once bonded, this slice 30 should serve as a stiffener, thus allowing cleavage in the donor wafer and in the final slice of SOI and possible layer transfer. Another objective is to create a layer that does not evolve in subsequent high temperature annealing steps in the finish of the SOI wafer and in the fabrication of semiconductor devices. After filling the pores, the monocrystalline semiconductor support substrate comprising the filled pores can be chemically mechanically polished ("CMP"). Chemical mechanical polishing can take place by methods known in the art. See Fig. 4C, which shows a monocrystalline semiconductor support substrate 100 CMP polished on the wafer surface. The objectives of this step are (1) to reduce the surface roughness to a level at which it can be bonded to the donor wafer, and (2) to remove an uninterrupted portion of the polycrystalline silicon film, since the portion uninterrupted does not exhibit the desired thermal stability. According to the method of the present invention, the front surface of the support substrate comprising filled pores can be oxidized after CMP polishing. In some embodiments, the front surface may be thermally oxidized (where a portion of the deposited semiconductor material film will be consumed) or the semiconductor oxide film (eg, silicon dioxide ) can be developed by chemical vapor deposition of oxide. The oxide layer may have a thickness between about 0.1 micrometers and about 10 micrometers, for example between about 0.1 micrometers and about 4 microns, for example between about 0.1 micrometers and about 2 micrometers, or about 0.1 micrometer and about 1 micrometer. After the steps described above, wafer cleaning is optional. If desired, the slices can be cleaned, for example, in a standard SC1 / SC2 solution. In addition, the slices, particularly the silicon dioxide layer on the charge trapping layer, may be subjected to chemical mechanical polishing (CMP) to reduce the surface roughness, preferably to the level at which 1 11, n RMS2x2 micrometers2 is less than about 5 angstroms, where Rq eff = the roughness profile contains ordered points, regularly spaced along the plot, and yi is the vertical distance from the mean line to the data point.
[0015] The monocrystalline semiconductor carrier wafer prepared according to the method described herein to include a charge trapping layer is then bonded to a monocrystalline semiconductor donor substrate, for example, a monocrystalline semiconductor donor wafer, which is prepared in accordance with conventional layer transfer methods. The monocrystalline semiconductor donor substrate may be a monocrystalline semiconductor wafer. In preferred embodiments, the semiconductor wafer comprises a semiconductor material selected from the group consisting of silicon, silicon carbide, silicon-germanium, gallium arsenide, gallium nitride, indium, indium gallium arsenide, germanium, and combinations thereof. Depending on the desired properties of the final integrated circuit device, the monocrystalline (e.g. silicon) semiconductor donor wafer may comprise a dopant selected from the group consisting of boron, arsenic and phosphorus. The resistivity of the monocrystalline (e.g. silicon) semiconductor donor wafer may range from 1 to 50 ohm-cm, typically from 5 to 25 ohm-cm. The monocrystalline semiconductor donor wafer may be subjected to standard process steps including oxidation, implantation, and post-implantation cleaning. Therefore, a semiconductor donor substrate, such as a monocrystalline semiconductor wafer of a material which is conventionally used in the preparation of multilayer semiconductor structures, for example, a monocrystalline silicon donor wafer, which has been etched and polished and optionally oxidized, is ion implanted to form a damage layer in the donor substrate. The damage layer forms the final cleavage plane. In some embodiments, the semiconductor donor substrate 15 comprises a dielectric layer, i.e., an insulating layer. Suitable dielectric layers may comprise a material selected from silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide , barium oxide, and a combination thereof. In some embodiments, the dielectric layer has a thickness of at least about 10 nanometers, for example, between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, for example about 50 nanometers, 100 nanometers, or 200 nanometers. In some embodiments, the dielectric layer comprises one or more insulating materials selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and any combination thereof. In some embodiments, the dielectric layer has a thickness of at least about 10 nanometers, for example, between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, for example about 50 nanometers, 100 nanometers, or 200 nanometers. In some embodiments, the dielectric layer comprises multiple layers of insulating material. The dielectric layer may comprise two insulating layers, three insulating layers, or more. Each insulating layer may comprise a material selected from silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide , Barium oxide, and any combination thereof. In some embodiments, each insulating layer may comprise a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and any combination thereof. Each insulating layer may have a thickness of at least about 10 nanometers, for example between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, for example about 50 nanometers, 100 nanometers, or 200 nanometers.
[0016] In some embodiments, the front surface of the monocrystalline semiconductor donor substrate (e.g., a monocrystalline silicon donor substrate) may be thermally oxidized (whereby a portion of the deposited semiconductor material film will be consumed) to prepare the semiconductor oxide film, or the semiconductor oxide film (eg, silicon dioxide) can be developed by chemical vapor deposition of oxide. In some embodiments, the front surface of the monocrystalline semiconductor donor substrate may be thermally oxidized in an oven such as ASM A400 in the same manner as described above. In some embodiments, the donor substrates are oxidized to provide an oxide layer on the front surface layer of a thickness of at least about 10 nanometers, for example, between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, or between about 100 nanometers and about 800 nanometers, for example about 600 nanometers. Ion implantation may be performed in a commercially available instrument, such as Applied Materials Quantum II, Quantum LEAP, or Quantum X.
[0017] Implanted ions include He, H, H2, or combinations thereof. Ion implantation is performed with sufficient density and time to form a damage layer in the semiconductor donor substrate. The implantation density may range from about 10 12 ions / cm 2 to about 10 17 ions / cm 2, for example from about 10 14 ions / cm 2 to about 10 17 ions / cm 2, for example from about 10 15 ions / cm 2 to about 10 16 ions / cm 2. ions / cm2. The implantation energies may range from about 1 keV to about 3,000 keV, for example from about 5 keV to about 1,000 keV, or from about 5 keV to about 200 keV, or from 5 keV to about 100 keV, or from 5 keV to about 80 keV. The depth of implantation determines the thickness of the monocrystalline semiconductor device layer in the final SOI structure. In some embodiments, it may be desirable to subject the single crystal semiconductor donor wafers, for example, monocrystalline silicon donor wafers, to post-implantation cleanup. In some preferred embodiments, the cleaning could include Piranha cleaning followed by deionized water rinsing and SC1 / SC2 cleansings. In some embodiments of the present invention, the monocrystalline semiconductor donor substrate having an ion implantation region therein formed by the implantation of helium ions and / or hydrogen ions is annealed at a temperature sufficient to form a thermally activated cleavage plane in the monocrystalline semiconductor donor substrate. An example of a suitable tool could be a simple electric furnace, such as a Blue M model. In some preferred embodiments, the monocrystalline semiconductor donor substrate in which ions have been implanted is annealed at a temperature of 20 ° C. about 200 ° C to about 350 ° C, from about 225 ° C to about 350 ° C, preferably about 350 ° C. Thermal annealing can take place for a time of about 2 hours to about 10 hours, for example about 2 hours. Thermal annealing in these temperature ranges is sufficient to form a thermally activated cleavage plane. After thermal annealing to activate the cleavage plane, the surface of the monocrystalline semiconductor donor substrate is preferably cleaned. In some embodiments, the monocrystalline semiconductor donor substrate in which ions have been implanted and optionally cleaned and optionally annealed is subjected to surface activation by oxygen plasma and / or nitrogen plasma. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, such as those available from EV Group, such as EVG®810LT Low Temp Plasma Activation System. The monocrystalline semiconductor donor wafer into which ions have been implanted and optionally cleaned is loaded into the chamber. The vacuum is made in the chamber and it is refilled with 02 or N2 at a pressure lower than the atmospheric pressure to thereby create the plasma. The monocrystalline semiconductor donor wafer is exposed to this plasma for the desired time, which can range from about 1 second to about 120 seconds. Oxygen or nitrogen plasma surface oxidation is performed to render the front surface of the hydrophilic and manageable monocrystalline semiconductor donor substrate for binding to a monocrystalline semiconductor support substrate prepared according to the method described herein. -above. After plasma activation, the activated surface is rinsed with deionized water. The slice is then dewatered before binding.
[0018] The hydrophilic front surface layer of the monocrystalline semiconductor donor substrate and the front surface of the monocrystalline semiconductor support substrate, which is optionally oxidized, are then brought into close contact to thereby form a bonded structure. The bonded structure comprises a dielectric layer, for example, a buried oxide, with a portion of the dielectric layer constituted by the oxidized front surface of the monocrystalline semiconductor support substrate and a portion of the dielectric layer formed by the oxidized front surface of the monocrystalline semiconductor donor substrate. In some embodiments, the dielectric layer, for example, the buried oxide layer, has a thickness of at least about 10 nanometers, for example between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers or between about 100 nanometers and about 800 nanometers, for example about 600 nanometers. Since the mechanical bond is relatively fragile due to its retention by the van der Waal forces, the bonded structure is further annealed to solidify the bond between the donor wafer and the support wafer. In some embodiments of the present invention, the bonded structure is annealed at a temperature sufficient to form a thermally activated cleavage plane in the monocrystalline semiconductor donor substrate. An example of a suitable tool could be a simple electric furnace, such as the Bue M model. In some preferred embodiments, the bonded structure is annealed at a temperature of about 200 ° C to about 350 ° C, about 225 ° C to about 350 ° C, preferably about 350 ° C. Thermal annealing can take place for a time of about 0.5 hours to about 10 hours, preferably about 2 hours. Thermal annealing in these temperature ranges is sufficient to form a thermally activated cleavage plane. After thermal annealing to activate the cleavage plane, the bonded structure can be cleaved. After thermal annealing, the bond between the monocrystalline semiconductor donor substrate and the monocrystalline semiconductor support substrate is sufficiently resistant to initiate a layer transfer through the cleavage of the plan-bound structure. cleavage. Cleavage can be performed according to techniques known in the art. In some embodiments, the bonded structure may be placed in a conventional cleavage station attached to fixed suction cups on one side and attached to additional suction cups on an articulated arm on the other side. A crack is started near the attachment of the suction cups and the movable arm pivots around the joint, dividing the wafer. The cleavage removes a portion of the semiconductor donor wafer, thereby leaving a semiconductor device layer, preferably a silicon device layer, on the semiconductor-on-insulator composite structure.
[0019] Following cleavage, the cleaved structure may be annealed at a high temperature to further enhance the bond between the transferred device layer and the monocrystalline semiconductor support substrate. An example of a suitable tool could be a vertical furnace, such as an ASM A400. In some preferred embodiments, the bonded structure is annealed at a temperature of about 1,000 ° C to about 1,200 ° C, preferably about 1,000 ° C. Thermal annealing can take place for a time of about 0.5 hours to about 8 hours, preferably about 2 to 4 hours. Thermal annealing in these temperature ranges is sufficient to enhance the bond between the transferred device layer and the single crystal semiconductor support substrate. After cleavage and annealing at high temperature, the bonded structure can be subjected to a cleaning process to remove the thin particles of thermal oxide and cleaning the surface. In some embodiments, the monocrystalline semiconductor donor wafer can be brought to the desired thickness and regularity by subjecting it to a hydrochloric acid vapor phase etching process in a single wafer epitaxial reactor. horizontal flow using H2 as a carrier gas. In some embodiments, an epitaxial layer may be deposited on the transferred device layer. The finished SOI wafer comprises the high resistivity monocrystalline semiconductor support substrate (e.g., a monocrystalline silicon support substrate), a charge trapping layer, a dielectric layer (e.g., a buried oxide layer) prepared from the oxidation of the monocrystalline semiconductor donor substrate, and the semiconductor device layer (prepared by thinning the donor substrate), can then be subjected to metrology inspections at the end of the line and cleaned at a 25 final time using a typical SC1-SC2 process. Radio-frequency chips of improved quality can be manufactured from this SOI slice. The oxide walls distributed in the porous silicon prevent growth of the grains during the annealing of the polycrystalline silicon. Therefore, the parasitic oscillation elimination film maintains a large area of grain boundaries, and therefore a high density of charge traps. Finally, in RF chips, the parasitic conducting channels are not induced, even if high temperature processing steps are used in the manufacture of RF chips. As the invention has been described in detail, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims.
[0020] Given that various changes could be made in the compositions and processes above without departing from the scope of the invention, it is intended that any subject contained in the above description be interpreted as illustrative and not in a limiting sense.
[0021] When presenting elements of the present invention or the preferred embodiment or embodiments thereof, the articles "a", "the", and "said" are intended to mean that there is one or more many of the elements. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the items listed. 10

权利要求:
Claims (47)
[0001]
REVENDICATIONS1. A multilayer structure comprising: a monocrystalline semiconductor support substrate comprising two generally parallel major surfaces, one of which is a front surface of the monocrystalline semiconductor support substrate and the other is a back surface of the monocrystalline semiconductor support substrate, a circumferential edge joining the front and rear surfaces of the monocrystalline semiconductor support substrate, a central plane between the front surface and the back surface of the monocrystalline semiconductor support substrate, a front surface region having a depth D, as measured from the front surface and towards the central plane, and a body region between the front and rear surfaces of the monocrystalline semiconductor support substrate, wherein the front surface region comprises pores, each of the pores comprising a bottom surface and a surface of side wall, and further wherein the pores are filled with a maté amorphous semiconductor material, a polycrystalline semiconductor material, or a semiconductor oxide; a dielectric layer in contact with the front surface of the monocrystalline semiconductor support substrate; and a monocrystalline semiconductor device layer in contact with the dielectric layer.
[0002]
The multilayer structure of claim 1, wherein the single crystal semiconductor support substrate and the monocrystalline semiconductor device layer comprise silicon.
[0003]
The multilayer structure of claim 1, wherein the single crystal semiconductor support substrate comprises a silicon wafer cut in a monocrystalline silicon ingot obtained by the Czochralski method or the floating zone growth method.
[0004]
The multilayer structure of claim 1, wherein the single crystal semiconductor carrier substrate has a volume resistivity of from about 500 Ohm-cm to about 100,000 Ohm-cm, or from about 1,000 Ohm-cm to about 100,000 Ohm-cm, or between about 1,000 Ohm-cm and about 10,000 Ohm-cm, or between about 2,000 Ohm-cm and about 10,000 Ohm-cm, or between about 3,000 Ohm-cm and about 10,000 Ohm-CM.
[0005]
The multilayer structure of claim 1, wherein the monocrystalline semiconductor carrier substrate has a volume resistivity of between about 3,000 Ohm-cm and about 5,000 Ohm-cm. 3033933 29
[0006]
The multilayer structure of claim 1, wherein the front surface region of the single crystal semiconductor support substrate has a depth, D, of between about 0.1 micrometer and about 50 micrometer, as measured from the front surface of the monocrystalline semiconductor support substrate. monocrystalline semiconductor carrier substrate to the bottom surfaces of the pores.
[0007]
The multilayer structure of claim 1, wherein the front surface region of the monocrystalline semiconductor support substrate has a depth, D, of between about 0.3 micrometers and about 20 microns, between about 1 micrometer and about 10 microns, or between about 1 micron and about 5 micrometers, as measured from the front surface of the monocrystalline semiconductor support substrate to the bottom surfaces of the pores.
[0008]
The multilayer structure of claim 1, wherein the front surface region of the monocrystalline semiconductor support substrate comprises pores with a pore density between about 5% and about 80%, or between about 5% and about 50%. .
[0009]
The multilayer structure of claim 1, wherein the pores have an average depth of between about 1 micrometer and about 10 microns, as measured from the front surface of the single crystal semiconductor support substrate to the bottom surfaces of the pores. 20
[0010]
The multilayer structure of claim 1, wherein the pores have an average depth of between about 1 micrometer and about 5 microns, as measured from the front surface of the single crystal semiconductor support substrate to the bottom surfaces of the pores.
[0011]
The multilayer structure of claim 1, wherein the pores have an average diameter between about 1 nanometer and about 1,000 nanometers, as measured at any point along the pore side wall, or between about 2 nanometers and about 200 nanometers, as measured at any point along the pore sidewall.
[0012]
The multilayer structure of claim 1, wherein the bottom surface and the sidewall surface of each of the pores comprise a semiconductor oxide film.
[0013]
The multilayer structure of claim 1, wherein the pores are filled with an amorphous semiconductor material.
[0014]
The multilayer structure of claim 1, wherein the pores are filled with amorphous silicon. 3033933 30
[0015]
The multilayer structure of claim 1, wherein the pores are filled with a polycrystalline semiconductor material.
[0016]
The multilayer structure of claim 1, wherein the pores are filled with polycrystalline silicon. 5
[0017]
The multilayer structure of claim 1, wherein the pores are filled with a semiconductor oxide.
[0018]
The multilayer structure of claim 1, wherein the pores are filled with silicon dioxide.
[0019]
The multilayer structure of claim 1, wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, oxide titanium, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof.
[0020]
The multilayer structure of claim 1, wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, silicon nitride, and any combination thereof .
[0021]
The multilayer structure of claim 1, wherein the dielectric layer comprises a plurality of layers, each insulating layer in the plurality of layers comprising a material selected from the group consisting of silicon dioxide, silicon oxynitride, and silicon nitride.
[0022]
The multilayer structure of claim 1, wherein the dielectric layer has a thickness of at least about 10 nanometers, for example between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, for example about 50 nanometers, 100 nanometers, or 200 nanometers.
[0023]
23. A method of forming a multilayer structure, the method comprising: contacting a front surface of a monocrystalline semiconductor support substrate with an etching solution to thereby etch pores in a front surface region of the monocrystalline semiconductor support substrate, wherein the single crystal semiconductor support substrate comprises two generally parallel major surfaces, one of which is the front surface of the single crystal semiconductor support substrate and the other is a back surface of the monocrystalline semiconductor support substrate; monocrystalline semi-conductive support substrate, a circumferential edge joining the front and rear surfaces of the monocrystalline semiconductor carrier substrate, a central plane between the front surface and the back surface of the monocrystalline semiconductor support substrate, the surface region. front having a depth, D, as measured from the front surface and towards the central plane, and a body region between the front and rear surfaces of the monocrystalline semiconductor support substrate, wherein each of the pores comprises a bottom surface and a sidewall surface; oxidation of the bottom surface and the sidewall surface of each of the pores; filling each of the pores having the oxidized bottom surface and the oxidized sidewall surface with an amorphous semiconductor material, a polycrystalline semiconductor material, or a semiconductor oxide; and bonding a dielectric layer on a front surface of a monocrystalline semiconductor donor substrate to the front surface of the monocrystalline semiconductor support substrate to thereby form a bonded structure, wherein the semiconductor donor substrate is Monocrystalline conductor comprises two generally parallel main surfaces, one of which is the front surface of the semiconductor donor substrate and the other is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and rear surfaces of the substrate. semiconductor donor, and a central plane between the front and back surfaces of the semiconductor donor substrate.
[0024]
24. The method of claim 23, wherein the monocrystalline semi-conductive support substrate and the monocrystalline semiconductor donor substrate comprise silicon.
[0025]
25. The method of claim 23, wherein the monocrystalline semiconductor carrier substrate and the monocrystalline semiconductor donor substrate comprise a silicon wafer cut in a monocrystalline silicon ingot obtained by the Czochralski method or the floating zone growth method. .
[0026]
The method of claim 23, wherein the monocrystalline semiconductor carrier substrate has a volume resistivity between about 500 Ohm-cm and about 100,000 Ohm-cm, or between about 1,000 Ohm-cm and about 100,000 Ohm-cm, or between about 1,000 Ohm-cm. Ohm-cm and about 10,000 Ohm-cm, or between about 2,000 Ohm-30 cm and about 10,000 Ohm-cm, or between about 3,000 Ohm-cm and about 10,000 Ohm-cm.
[0027]
The method of claim 23, wherein the monocrystalline semiconductor carrier substrate has a volume resistivity of between about 3,000 Ohm-cm and about 5,000 Ohm-cm. 3033933 32
[0028]
The method of claim 23, wherein the front surface region of the monocrystalline semiconductor support substrate is etched with a pore density between about 5% and about 80%, or between about 5% and about 50%.
[0029]
29. The method of claim 23, wherein the front surface region of the monocrystalline semiconductor support substrate is contacted with the etching solution for a time sufficient to etch pores to an average depth of between about 1 micron and about 10 micrometers, as measured from the front surface of the monocrystalline semiconductor support substrate to the bottom surfaces of the pores. 10
[0030]
The method of claim 23, wherein the front surface region of the monocrystalline semiconductor support substrate is contacted with the etching solution for a time sufficient to etch pores to an average depth of between about 1 micron and about 5 microns. micrometers, as measured from the front surface of the monocrystalline semiconductor support substrate to the bottom surfaces of the pores.
[0031]
The method of claim 23, wherein the front surface region of the monocrystalline semiconductor support substrate is contacted with the etching solution for a time sufficient to etch pores with an average diameter between about 1 nanometer and about 1,000. nanometers, as measured at any point along the side wall of the pores.
[0032]
The method of claim 23, wherein the front surface region of the monocrystalline semiconductor support substrate is contacted with the etching solution for a time sufficient to etch pores with an average diameter between about 2 nanometers and about 200 nanometers. nanometers, as measured at any point along the side wall of the pores.
[0033]
The method of claim 23, wherein the front surface region of the monocrystalline semiconductor support substrate comprising pores is dried after etching.
[0034]
34. The method of claim 23, wherein the bottom surface and the sidewall surface of each of the pores are oxidized by placing the monocrystalline semiconductor support substrate comprising the pores in the front surface region thereof. contact with an ambient atmosphere comprising oxygen.
[0035]
The method of claim 34, wherein the ambient atmosphere comprising oxygen is air. 35
[0036]
36. The method of claim 23, wherein the bottom surface and the sidewall surface of each of the pores are oxidized by anodic oxidation. 3033933 33
[0037]
37. The method of claim 36, wherein the anodic oxidation takes place in an anodizing electrolyte comprising sulfuric acid.
[0038]
The method of claim 23, wherein the pores are filled with an amorphous semiconductor material. 5
[0039]
39. The method of claim 23, wherein the pores are filled with amorphous silicon.
[0040]
40. The method of claim 23, wherein the pores are filled with a polycrystalline semiconductor material.
[0041]
41. The method of claim 23, wherein the pores are filled with polycrystalline silicon.
[0042]
42. The method of claim 23, wherein the pores are filled with a semiconductor oxide.
[0043]
The method of claim 23, wherein the pores are filled with silicon dioxide. 15
[0044]
44. The method of claim 24, further comprising heating the bonded structure at a temperature and for a time sufficient to enhance bonding between the dielectric layer of the semiconductor donor structure and the semiconductor oxide on the front surface of the substrate. monocrystalline semiconductor support substrate.
[0045]
45. The method of claim 23, wherein the monocrystalline semiconductor donor substrate comprises a cleavage plane.
[0046]
The method of claim 45, further comprising mechanically cleaving the bound structure at the cleavage plane of the monocrystalline semiconductor donor substrate to thereby prepare a cleaved structure comprising the monocrystalline semiconductor support substrate, the semiconductor oxide layer, the dielectric layer in contact with the semiconductor oxide layer, and a monocrystalline semiconductor device layer in contact with the dielectric layer.
[0047]
47. The method of claim 46, further comprising heating the cleaved structure at a temperature and for a time sufficient to enhance the bond between the single crystal semiconductor device layer and the monocrystalline semi-conductive support substrate.

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引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

FR3067517A1|2017-06-13|2018-12-14|Commissariat A L'energie Atomique Et Aux Energies Alternatives|SUBSTRATE SOI COMPATIBLE WITH RFSOI AND FDSOI TECHNOLOGIES|US4501060A|1983-01-24|1985-02-26|At&T Bell Laboratories|Dielectrically isolated semiconductor devices|

---

US4755865A|1986-01-21|1988-07-05|Motorola Inc.|Means for stabilizing polycrystalline semiconductor layers|

---

JPH0648686B2|1988-03-30|1994-06-22|新日本製鐵株式会社|Silicon wafer having excellent gettering ability and method of manufacturing the same|

---

JPH06105691B2|1988-09-29|1994-12-21|株式会社富士電機総合研究所|Method for producing carbon-doped amorphous silicon thin film|

---

JP2808701B2|1989-08-01|1998-10-08|ソニー株式会社|Method for manufacturing semiconductor device|

---

JP2617798B2|1989-09-22|1997-06-04|三菱電機株式会社|Stacked semiconductor device and method of manufacturing the same|

---

US5436173A|1993-01-04|1995-07-25|Texas Instruments Incorporated|Method for forming a semiconductor on insulator device|

---

US6043138A|1996-09-16|2000-03-28|Advanced Micro Devices, Inc.|Multi-step polysilicon deposition process for boron penetration inhibition|

---

US5783469A|1996-12-10|1998-07-21|Advanced Micro Devices, Inc.|Method for making nitrogenated gate structure for improved transistor performance|

---

US6306729B1|1997-12-26|2001-10-23|Canon Kabushiki Kaisha|Semiconductor article and method of manufacturing the same|

---

US6068928A|1998-02-25|2000-05-30|Siemens Aktiengesellschaft|Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method|

---

JP3748500B2|1998-09-04|2006-02-22|キヤノン株式会社|Method for manufacturing semiconductor substrate|

---

US6268068B1|1998-10-06|2001-07-31|Case Western Reserve University|Low stress polysilicon film and method for producing same|

---

JP4313874B2|1999-02-02|2009-08-12|キヤノン株式会社|Substrate manufacturing method|

---

US6372600B1|1999-08-30|2002-04-16|Agere Systems Guardian Corp.|Etch stops and alignment marks for bonded wafers|

---

FR2810448B1|2000-06-16|2003-09-19|Soitec Silicon On Insulator|PROCESS FOR PRODUCING SUBSTRATES AND SUBSTRATES OBTAINED BY THIS PROCESS|

---

JP2002359247A|2000-07-10|2002-12-13|Canon Inc|Semiconductor member, semiconductor device and manufacturing method therefor|

---

US20020090758A1|2000-09-19|2002-07-11|Silicon Genesis Corporation|Method and resulting device for manufacturing for double gated transistors|

---

US6562127B1|2002-01-16|2003-05-13|The United States Of America As Represented By The Secretary Of The Navy|Method of making mosaic array of thin semiconductor material of large substrates|

---

US6995430B2|2002-06-07|2006-02-07|Amberwave Systems Corporation|Strained-semiconductor-on-insulator device structures|

---

US7074623B2|2002-06-07|2006-07-11|Amberwave Systems Corporation|Methods of forming strained-semiconductor-on-insulator finFET device structures|

---

US6743662B2|2002-07-01|2004-06-01|Honeywell International, Inc.|Silicon-on-insulator wafer for RF integrated circuit|

---

US7057234B2|2002-12-06|2006-06-06|Cornell Research Foundation, Inc.|Scalable nano-transistor and memory using back-side trapping|

---

DE602004020181D1|2003-01-07|2009-05-07|Soitec Silicon On Insulator|RECYCLING A WATER WITH A MULTILAYER STRUCTURE AFTER REMOVING A THIN LAYER|

---

FR2855650B1|2003-05-30|2006-03-03|Soitec Silicon On Insulator|SUBSTRATES FOR CONSTRAINTS SYSTEMS AND METHOD FOR CRYSTALLINE GROWTH ON SUCH A SUBSTRATE|

---

WO2005031842A2|2003-09-26|2005-04-07|Universite Catholique De Louvain|Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses|

---

US6992025B2|2004-01-12|2006-01-31|Sharp Laboratories Of America, Inc.|Strained silicon on insulator from film transfer and relaxation by hydrogen implantation|

---

US7279400B2|2004-08-05|2007-10-09|Sharp Laboratories Of America, Inc.|Method of fabricating single-layer and multi-layer single crystalline silicon and silicon devices on plastic using sacrificial glass|

---

US7312487B2|2004-08-16|2007-12-25|International Business Machines Corporation|Three dimensional integrated circuit|

---

US7476594B2|2005-03-30|2009-01-13|Cree, Inc.|Methods of fabricating silicon nitride regions in silicon carbide and resulting structures|

---

US20060270190A1|2005-05-25|2006-11-30|The Regents Of The University Of California|Method of transferring a thin crystalline semiconductor layer|

---

FR2890489B1|2005-09-08|2008-03-07|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE HETEROSTRUCTURE ON INSULATION|

---

FR2902233B1|2006-06-09|2008-10-17|Soitec Silicon On Insulator|METHOD FOR LIMITING LACUNAR MODE BROADCAST DISTRIBUTION IN A HETEROSTRUCTURE|

---

FR2910702B1|2006-12-26|2009-04-03|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING A MIXED SUBSTRATE|

---

KR101400699B1|2007-05-18|2014-05-29|가부시키가이샤 한도오따이 에네루기 켄큐쇼|Semiconductor substrate, semiconductor device and manufacturing method thereof|

---

JP4445524B2|2007-06-26|2010-04-07|株式会社東芝|Manufacturing method of semiconductor memory device|

---

JP2009016692A|2007-07-06|2009-01-22|Toshiba Corp|Manufacturing method of semiconductor storage device, and semiconductor storage device|

---

US7915716B2|2007-09-27|2011-03-29|Stats Chippac Ltd.|Integrated circuit package system with leadframe array|

---

US7879699B2|2007-09-28|2011-02-01|Infineon Technologies Ag|Wafer and a method for manufacturing a wafer|

---

US8128749B2|2007-10-04|2012-03-06|International Business Machines Corporation|Fabrication of SOI with gettering layer|

---

US7868419B1|2007-10-18|2011-01-11|Rf Micro Devices, Inc.|Linearity improvements of semiconductor substrate based radio frequency devices|

---

US20090236689A1|2008-03-24|2009-09-24|Freescale Semiconductor, Inc.|Integrated passive device and method with low cost substrate|

---

FR2933234B1|2008-06-30|2016-09-23|S O I Tec Silicon On Insulator Tech|GOODLY DUAL STRUCTURE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME|

---

US9099526B2|2010-02-16|2015-08-04|Monolithic 3D Inc.|Integrated circuit device and structure|

---

US8642416B2|2010-07-30|2014-02-04|Monolithic 3D Inc.|Method of forming three dimensional integrated circuit devices using layer transfer technique|

---

US8058137B1|2009-04-14|2011-11-15|Monolithic 3D Inc.|Method for fabrication of a semiconductor device and structure|

---

JP2010258083A|2009-04-22|2010-11-11|Panasonic Corp|Soi wafer, method for producing the same, and method for manufacturing semiconductor device|

---

DE112010004241T5|2009-11-02|2013-05-08|Fuji Electric Co., Ltd.|Semiconductor component and method for producing the semiconductor device|

---

JP5644096B2|2009-11-30|2014-12-24|ソニー株式会社|Method for manufacturing bonded substrate and method for manufacturing solid-state imaging device|

---

US8252624B2|2010-01-18|2012-08-28|Applied Materials, Inc.|Method of manufacturing thin film solar cells having a high conversion efficiency|

---

US8859393B2|2010-06-30|2014-10-14|Sunedison Semiconductor Limited|Methods for in-situ passivation of silicon-on-insulator wafers|

---

JP5627649B2|2010-09-07|2014-11-19|株式会社東芝|Method for manufacturing nitride semiconductor crystal layer|

---

JP5117588B2|2010-09-07|2013-01-16|株式会社東芝|Method for manufacturing nitride semiconductor crystal layer|

---

FR2967812B1|2010-11-19|2016-06-10|S O I Tec Silicon On Insulator Tech|ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND METHOD OF MANUFACTURING SUCH A DEVICE|

---

US9287353B2|2010-11-30|2016-03-15|Kyocera Corporation|Composite substrate and method of manufacturing the same|

---

US8536021B2|2010-12-24|2013-09-17|Io Semiconductor, Inc.|Trap rich layer formation techniques for semiconductor devices|

---

US8466036B2|2010-12-24|2013-06-18|Io Semiconductor, Inc.|Trap rich layer for semiconductor devices|

---

US8481405B2|2010-12-24|2013-07-09|Io Semiconductor, Inc.|Trap rich layer with through-silicon-vias in semiconductor devices|

---

US8796116B2|2011-01-31|2014-08-05|Sunedison Semiconductor Limited|Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods|

---

JP5673170B2|2011-02-09|2015-02-18|信越半導体株式会社|Bonded substrate, method for manufacturing bonded substrate, semiconductor device, and method for manufacturing semiconductor device|

---

US20120235283A1|2011-03-16|2012-09-20|Memc Electronic Materials, Inc.|Silicon on insulator structures having high resistivity regions in the handle wafer|

---

FR2973158B1|2011-03-22|2014-02-28|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS|

---

FR2973159B1|2011-03-22|2013-04-19|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING BASE SUBSTRATE|

---

US9496255B2|2011-11-16|2016-11-15|Qualcomm Incorporated|Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same|

---

US8741739B2|2012-01-03|2014-06-03|International Business Machines Corporation|High resistivity silicon-on-insulator substrate and method of forming|

---

US20130193445A1|2012-01-26|2013-08-01|International Business Machines Corporation|Soi structures including a buried boron nitride dielectric|

---

US8921209B2|2012-09-12|2014-12-30|International Business Machines Corporation|Defect free strained silicon on insulator substrates|

---

US9202711B2|2013-03-14|2015-12-01|Sunedison Semiconductor Limited |Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness|

---

US8951896B2|2013-06-28|2015-02-10|International Business Machines Corporation|High linearity SOI wafer for low-distortion circuit applications|

---

US9768056B2|2013-10-31|2017-09-19|Sunedison Semiconductor Limited |Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition|

---

CN104409411B|2014-11-24|2017-12-08|上海华虹宏力半导体制造有限公司|Semiconductor devices and forming method thereof|SG11201907141XA|2017-02-10|2019-09-27|Globalwafers Co Ltd|Methods for assessing semiconductor structures|

---

US10784348B2|2017-03-23|2020-09-22|Qualcomm Incorporated|Porous semiconductor handle substrate|

---

FR3066858B1|2017-05-23|2019-06-21|Soitec|METHOD FOR MINIMIZING DISTORTION OF A SIGNAL IN A RADIO FREQUENCY CIRCUIT|

---

CN109270423B|2018-10-03|2020-11-20|大连理工大学|Evaluation test method for low-temperature stability of SiC MOSFET device|

---

CN109637971B|2018-12-07|2021-08-10|合肥市华达半导体有限公司|Semiconductor device with improved performance|

---

FR3098342B1|2019-07-02|2021-06-04|Soitec Silicon On Insulator|semiconductor structure comprising a buried porous layer, for RF applications|

---

CN113106542A|2021-04-06|2021-07-13|中国科学院苏州纳米技术与纳米仿生研究所|Large-area aluminum single crystal film and preparation method and application thereof|

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优先权:

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申请号 | 申请日 | 专利标题

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US201562134179P| true| 2015-03-17|2015-03-17|

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US62134179|2015-03-17|

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